I2S driver (over SPIv1) finished but untested.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6748 35acf78f-673a-0410-8e92-d51de3d6d3f4master
parent
5599a0f0c3
commit
8c4653a413
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@ -118,9 +118,9 @@ typedef enum {
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*
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* @notapi
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*/
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#define _i2S_isr_half_code(i2sp) { \
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if ((i2sp)->end_cb != NULL) { \
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(i2sp)->end_cb(i2sp, 0, (i2sp)->config->depth / 2); \
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#define _i2s_isr_half_code(i2sp) { \
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if ((i2sp)->config->end_cb != NULL) { \
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(i2sp)->config->end_cb(i2sp, 0, (i2sp)->config->size / 2); \
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} \
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}
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@ -137,7 +137,7 @@ typedef enum {
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*
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* @notapi
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*/
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#define _i2s_isr_code(i2sp) { \
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#define _i2s_isr_full_code(i2sp) { \
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if ((i2sp)->config->end_cb) { \
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(i2sp)->state = I2S_COMPLETE; \
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(i2sp)->config->end_cb(i2sp, \
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@ -118,22 +118,25 @@ I2SDriver I2SD3;
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*/
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static void i2s_lld_serve_rx_interrupt(I2SDriver *i2sp, uint32_t flags) {
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(void)i2sp;
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/* DMA errors handling.*/
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#if defined(STM32_I2S_DMA_ERROR_HOOK)
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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STM32_I2S_DMA_ERROR_HOOK(i2sp);
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}
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#else
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(void)flags;
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#endif
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/* Stop everything.*/
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dmaStreamDisable(i2sp->dmatx);
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dmaStreamDisable(i2sp->dmarx);
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/* Portable I2S ISR code defined in the high level driver, note, it is
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a macro.*/
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_i2s_isr_code(i2sp);
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/* Callbacks handling, note it is portable code defined in the high
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level driver.*/
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if ((flags & STM32_DMA_ISR_TCIF) != 0) {
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/* Transfer complete processing.*/
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_i2s_isr_full_code(i2sp);
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}
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else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
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/* Half transfer processing.*/
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_i2s_isr_half_code(i2sp);
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}
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}
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#endif
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@ -147,15 +150,25 @@ static void i2s_lld_serve_rx_interrupt(I2SDriver *i2sp, uint32_t flags) {
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*/
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static void i2s_lld_serve_tx_interrupt(I2SDriver *i2sp, uint32_t flags) {
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(void)i2sp;
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/* DMA errors handling.*/
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#if defined(STM32_I2S_DMA_ERROR_HOOK)
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(void)i2sp;
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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STM32_I2S_DMA_ERROR_HOOK(i2sp);
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}
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#else
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(void)flags;
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#endif
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/* Callbacks handling, note it is portable code defined in the high
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level driver.*/
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if ((flags & STM32_DMA_ISR_TCIF) != 0) {
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/* Transfer complete processing.*/
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_i2s_isr_full_code(i2sp);
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}
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else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
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/* Half transfer processing.*/
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_i2s_isr_half_code(i2sp);
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}
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}
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#endif
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@ -333,7 +346,7 @@ void i2s_lld_start(I2SDriver *i2sp) {
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dmaStreamSetMode(i2sp->dmatx, i2sp->txdmamode | dmasize);
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}
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/* I2S configuration.*/
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/* I2S (re)configuration.*/
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i2sp->spi->I2SPR = i2sp->config->i2spr;
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i2sp->spi->I2SCFGR = i2sp->config->i2scfgr | i2sp->cfg | SPI_I2SCFGR_I2SMOD;
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}
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@ -377,6 +390,22 @@ void i2s_lld_stop(I2SDriver *i2sp) {
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*/
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void i2s_lld_start_exchange(I2SDriver *i2sp) {
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/* RX DMA setup.*/
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if (NULL != i2sp->dmarx) {
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dmaStreamSetMemory0(i2sp->dmarx, i2sp->config->rx_buffer);
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dmaStreamSetTransactionSize(i2sp->dmarx, i2sp->config->size);
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dmaStreamEnable(i2sp->dmarx);
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}
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/* TX DMA setup.*/
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if (NULL != i2sp->dmatx) {
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dmaStreamSetMemory0(i2sp->dmatx, i2sp->config->tx_buffer);
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dmaStreamSetTransactionSize(i2sp->dmatx, i2sp->config->size);
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dmaStreamEnable(i2sp->dmatx);
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}
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/* Starting transfer.*/
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i2sp->spi->I2SCFGR |= SPI_I2SCFGR_I2SE;
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}
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/**
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@ -390,6 +419,14 @@ void i2s_lld_start_exchange(I2SDriver *i2sp) {
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*/
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void i2s_lld_stop_exchange(I2SDriver *i2sp) {
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/* Stop DMAs.*/
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if (NULL != i2sp->dmatx)
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dmaStreamDisable(i2sp->dmatx);
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if (NULL != i2sp->dmarx)
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dmaStreamDisable(i2sp->dmarx);
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/* Stop transfer.*/
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i2sp->spi->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
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}
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#endif /* HAL_USE_I2S */
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@ -134,6 +134,16 @@
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) && \
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STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
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#error "I2S2 RX and TX mode not supported in this driver implementation"
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#endif
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#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) && \
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STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
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#error "I2S3 RX and TX mode not supported in this driver implementation"
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#endif
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#if STM32_I2S_USE_SPI2 && !STM32_HAS_SPI2
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#error "SPI2 not present in the selected device"
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#endif
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