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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8480 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
Giovanni Di Sirio 2015-11-13 14:02:21 +00:00
parent f098e079d0
commit 8beb4eb166
3 changed files with 77 additions and 23 deletions
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52
demos/STM32/RT-STM32L476RG-NUCLEO/mcuconf.h
View File

@ -36,6 +36,58 @@
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_ADC_CLOCK_ENABLED TRUE
#define STM32_USB_CLOCK_ENABLED TRUE
#define STM32_SAI1_CLOCK_ENABLED TRUE
#define STM32_SAI2_CLOCK_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI16
#define STM32_PLLM_VALUE 4
#define STM32_PLLN_VALUE 40
#define STM32_PLLP_VALUE 7
#define STM32_PLLQ_VALUE 2
#define STM32_PLLR_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1N_VALUE 40
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 4
#define STM32_PLLSAI1R_VALUE 4
#define STM32_PLLSAI2N_VALUE 40
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2R_VALUE 4
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_CLK48SEL STM32_CLK48SEL_PLL
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*
* SERIAL driver system settings.

24
os/hal/ports/STM32/STM32L4xx/hal_lld.c
View File

@ -184,13 +184,17 @@ void stm32_clock_init(void) {
; /* Wait until LSI is stable. */
#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
#if STM32_ACTIVATE_PLL || STM32_ACTIVATE_PLLSAI1 || STM32_ACTIVATE_PLLSAI2
/* PLLM and PLLSRC are common to all PLLs.*/
RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN |
STM32_PLLQ | STM32_PLLQEN |
STM32_PLLP | STM32_PLLPEN |
STM32_PLLN | STM32_PLLM |
STM32_PLLSRC;
#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->CR |= RCC_CR_PLLON;
/* Waiting for PLL lock.*/
@ -227,22 +231,20 @@ void stm32_clock_init(void) {
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* DCKCFGR1 register initialization, note, must take care of the _OFF
/* CCIPR register initialization, note, must take care of the _OFF
pseudo settings.*/
{
uint32_t ccipr = 0;
uint32_t ccipr = STM32_DFSDMSEL | STM32_SWPMI1SEL | STM32_ADCSEL |
STM32_CLK48SEL | STM32_LPTIM2SEL | STM32_LPTIM1SEL |
STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
STM32_UART5SEL | STM32_UART4SEL | STM32_USART3SEL |
STM32_USART2SEL | STM32_USART1SEL;
#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
ccipr |= STM32_SAI2SEL;
#endif
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
ccipr |= STM32_SAI1SEL;
#endif
ccipr |= STM32_DFSDMSEL | STM32_SWPMI1SEL | STM32_ADCSEL |
STM32_CLK48SEL | STM32_SAI2SEL | STM32_SAI1SEL |
STM32_LPTIM2SEL | STM32_LPTIM1SEL | STM32_I2C3SEL |
STM32_I2C2SEL | STM32_I2C1SEL | STM32_UART5SEL |
STM32_UART4SEL | STM32_USART3SEL | STM32_USART2SEL |
STM32_USART1SEL;
RCC->CCIPR = ccipr;
}
@ -250,7 +252,7 @@ void stm32_clock_init(void) {
FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
STM32_FLASHBITS;
/* Switching to the configured clock source if it is different from HSI.*/
/* Switching to the configured clock source if it is different from MSI.*/
#if (STM32_SW != STM32_SW_MSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))

24
os/hal/ports/STM32/STM32L4xx/hal_lld.h
View File

@ -178,11 +178,11 @@
* @name RCC_PLLCFGR register bits definitions
* @{
*/
#define STM32_PLLSRC_MASK (3 << 16) /**< PLL clock source mask. */
#define STM32_PLLSRC_NOCLOCK (0 << 16) /**< PLL clock source disabled. */
#define STM32_PLLSRC_MSI (1 << 16) /**< PLL clock source is MSI. */
#define STM32_PLLSRC_HSI16 (2 << 16) /**< PLL clock source is HSI16. */
#define STM32_PLLSRC_HSE (3 << 16) /**< PLL clock source is HSE. */
#define STM32_PLLSRC_MASK (3 << 0) /**< PLL clock source mask. */
#define STM32_PLLSRC_NOCLOCK (0 << 0) /**< PLL clock source disabled. */
#define STM32_PLLSRC_MSI (1 << 0) /**< PLL clock source is MSI. */
#define STM32_PLLSRC_HSI16 (2 << 0) /**< PLL clock source is HSI16. */
#define STM32_PLLSRC_HSE (3 << 0) /**< PLL clock source is HSE. */
/** @} */
/**
@ -532,13 +532,6 @@
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#endif
/**
* @brief LSCO clock source.
*/
#if !defined(STM32_LSCOSEL) || defined(__DOXYGEN__)
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#endif
/**
* @brief MCO divider setting.
*/
@ -546,6 +539,13 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#endif
/**
* @brief LSCO clock source.
*/
#if !defined(STM32_LSCOSEL) || defined(__DOXYGEN__)
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#endif
/**
* @brief PLLSAI1N multiplier value.
* @note The allowed values are 8..86.