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DMAv1 fixes. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8395 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
Giovanni Di Sirio 2015-10-27 14:37:52 +00:00
parent c9a8ec92c8
commit 8b7474c1fc
5 changed files with 64 additions and 66 deletions
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56
os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
View File

@ -139,25 +139,25 @@
* instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
*/
const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
{DMA1_Channel1, DMA1_CH1_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 0, 0, STM32_DMA1_CH1_NUMBER},
{DMA1_Channel2, DMA1_CH2_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 4, 1, STM32_DMA1_CH2_NUMBER},
{DMA1_Channel3, DMA1_CH3_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 8, 2, STM32_DMA1_CH3_NUMBER},
{DMA1_Channel4, DMA1_CH4_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 12, 3, STM32_DMA1_CH4_NUMBER},
{DMA1_Channel5, DMA1_CH5_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 16, 4, STM32_DMA1_CH5_NUMBER},
{DMA1, DMA1_Channel1, DMA1_CH1_CMASK, ADDR_DMA1_CSELR, 0, 0, STM32_DMA1_CH1_NUMBER},
{DMA1, DMA1_Channel2, DMA1_CH2_CMASK, ADDR_DMA1_CSELR, 4, 1, STM32_DMA1_CH2_NUMBER},
{DMA1, DMA1_Channel3, DMA1_CH3_CMASK, ADDR_DMA1_CSELR, 8, 2, STM32_DMA1_CH3_NUMBER},
{DMA1, DMA1_Channel4, DMA1_CH4_CMASK, ADDR_DMA1_CSELR, 12, 3, STM32_DMA1_CH4_NUMBER},
{DMA1, DMA1_Channel5, DMA1_CH5_CMASK, ADDR_DMA1_CSELR, 16, 4, STM32_DMA1_CH5_NUMBER},
#if STM32_DMA1_NUM_CHANNELS > 5
{DMA1_Channel6, DMA1_CH6_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 20, 5, STM32_DMA1_CH6_NUMBER},
{DMA1, DMA1_Channel6, DMA1_CH6_CMASK, ADDR_DMA1_CSELR, 20, 5, STM32_DMA1_CH6_NUMBER},
#if STM32_DMA1_NUM_CHANNELS > 6
{DMA1_Channel7, DMA1_CH7_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 24, 6, STM32_DMA1_CH7_NUMBER},
{DMA1, DMA1_Channel7, DMA1_CH7_CMASK, ADDR_DMA1_CSELR, 24, 6, STM32_DMA1_CH7_NUMBER},
#if STM32_DMA2_NUM_CHANNELS > 0
{DMA2_Channel1, DMA2_CH1_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 0, 7, STM32_DMA2_CH1_NUMBER},
{DMA2_Channel2, DMA2_CH2_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 4, 8, STM32_DMA2_CH2_NUMBER},
{DMA2_Channel3, DMA2_CH3_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 8, 9, STM32_DMA2_CH3_NUMBER},
{DMA2_Channel4, DMA2_CH4_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 12, 10, STM32_DMA2_CH4_NUMBER},
{DMA2_Channel5, DMA2_CH5_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 16, 11, STM32_DMA2_CH5_NUMBER},
{DMA2, DMA2_Channel1, DMA2_CH1_CMASK, ADDR_DMA2_CSELR, 0, 7, STM32_DMA2_CH1_NUMBER},
{DMA2, DMA2_Channel2, DMA2_CH2_CMASK, ADDR_DMA2_CSELR, 4, 8, STM32_DMA2_CH2_NUMBER},
{DMA2, DMA2_Channel3, DMA2_CH3_CMASK, ADDR_DMA2_CSELR, 8, 9, STM32_DMA2_CH3_NUMBER},
{DMA2, DMA2_Channel4, DMA2_CH4_CMASK, ADDR_DMA2_CSELR, 12, 10, STM32_DMA2_CH4_NUMBER},
{DMA2, DMA2_Channel5, DMA2_CH5_CMASK, ADDR_DMA2_CSELR, 16, 11, STM32_DMA2_CH5_NUMBER},
#if STM32_DMA2_NUM_CHANNELS > 5
{DMA2_Channel6, DMA2_CH6_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 20, 12, STM32_DMA2_CH6_NUMBER},
{DMA2, DMA2_Channel6, DMA2_CH6_CMASK, ADDR_DMA2_CSELR, 20, 12, STM32_DMA2_CH6_NUMBER},
#if STM32_DMA2_NUM_CHANNELS > 6
{DMA2_Channel6, DMA2_CH7_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 24, 13, STM32_DMA2_CH7_NUMBER},
{DMA2, DMA2_Channel6, DMA2_CH7_CMASK, ADDR_DMA2_CSELR, 24, 13, STM32_DMA2_CH7_NUMBER},
#endif
#endif
#endif
@ -197,7 +197,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH1_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(DMA1, 1);
dmaServeInterrupt(STM32_DMA1_STREAM1);
OSAL_IRQ_EPILOGUE();
}
@ -213,7 +213,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH2_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(DMA1, 2);
dmaServeInterrupt(STM32_DMA1_STREAM2);
OSAL_IRQ_EPILOGUE();
}
@ -229,7 +229,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(DMA1, 3);
dmaServeInterrupt(STM32_DMA1_STREAM3);
OSAL_IRQ_EPILOGUE();
}
@ -245,7 +245,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH4_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(DMA1, 4);
dmaServeInterrupt(STM32_DMA1_STREAM4);
OSAL_IRQ_EPILOGUE();
}
@ -261,7 +261,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH5_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(DMA1, 5);
dmaServeInterrupt(STM32_DMA1_STREAM5);
OSAL_IRQ_EPILOGUE();
}
@ -277,7 +277,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH6_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(DMA1, 6);
dmaServeInterrupt(STM32_DMA1_STREAM6);
OSAL_IRQ_EPILOGUE();
}
@ -293,7 +293,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH7_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(DMA1, 7);
dmaServeInterrupt(STM32_DMA1_STREAM7);
OSAL_IRQ_EPILOGUE();
}
@ -309,7 +309,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH1_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(DMA2, 1);
dmaServeInterrupt(STM32_DMA2_STREAM1);
OSAL_IRQ_EPILOGUE();
}
@ -325,7 +325,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH2_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(DMA2, 2);
dmaServeInterrupt(STM32_DMA2_STREAM2);
OSAL_IRQ_EPILOGUE();
}
@ -341,7 +341,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(DMA2, 3);
dmaServeInterrupt(STM32_DMA2_STREAM3);
OSAL_IRQ_EPILOGUE();
}
@ -357,7 +357,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(DMA2, 4);
dmaServeInterrupt(STM32_DMA2_STREAM4);
OSAL_IRQ_EPILOGUE();
}
@ -373,7 +373,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(DMA2, 5);
dmaServeInterrupt(STM32_DMA2_STREAM5);
OSAL_IRQ_EPILOGUE();
}
@ -389,7 +389,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH6_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(DMA2, 6);
dmaServeInterrupt(STM32_DMA2_STREAM6);
OSAL_IRQ_EPILOGUE();
}
@ -405,7 +405,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(DMA2, 7);
dmaServeInterrupt(STM32_DMA2_STREAM7);
OSAL_IRQ_EPILOGUE();
}

23
os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h
View File

@ -217,13 +217,13 @@
* @brief STM32 DMA stream descriptor structure.
*/
typedef struct {
DMA_TypeDef *dma ; /**< @brief Associated DMA. */
DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */
uint32_t cmask; /**< @brief Mask of streams sharing
the same ISR. */
volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
volatile uint32_t *cselr; /**< @brief Associated CSELR reg. */
uint8_t shift; /**< @brief Bit offset in IFCR and
CSELR registers. */
uint8_t shift; /**< @brief Bit offset in ISR, IFCR
and CSELR registers. */
uint8_t selfindex; /**< @brief Index to self in array. */
uint8_t vector; /**< @brief Associated IRQ vector. */
} stm32_dma_stream_t;
@ -381,7 +381,7 @@ typedef struct {
* @special
*/
#define dmaStreamClearInterrupt(dmastp) { \
*(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->shift; \
(dmastp)->dma->IFCR = STM32_DMA_ISR_MASK << (dmastp)->shift; \
}
/**
@ -428,18 +428,17 @@ typedef struct {
/**
* @brief Serves a DMA IRQ.
*
* @param[in] dma pointer to the DMA block
* @param[in] s stream to serve
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*/
#define dmaServeInterrupt(dma, s) { \
#define dmaServeInterrupt(dmastp) { \
uint32_t flags; \
uint32_t idx = (dmastp)->selfindex; \
\
flags = ((dma)->ISR >> STM32_DMA_ISR_SHIFT(s)) & STM32_DMA_ISR_MASK; \
flags = ((dmastp)->dma->ISR >> (dmastp)->shift) & STM32_DMA_ISR_MASK; \
if (flags & STM32_DMA_ISR_MASK) { \
(dma)->IFCR = flags << STM32_DMA_ISR_SHIFT(s); \
if (_stm32_dma_isr_redir[(s) - 1U].dma_func) { \
_stm32_dma_isr_redir[(s) - 1U].dma_func(_stm32_dma_isr_redir[(s) - \
1U].dma_param, flags); \
(dmastp)->dma->IFCR = flags << (dmastp)->shift; \
if (_stm32_dma_isr_redir[idx].dma_func) { \
_stm32_dma_isr_redir[idx].dma_func(_stm32_dma_isr_redir[idx].dma_param, flags); \
} \
} \
}

34
os/hal/ports/STM32/STM32F0xx/hal_lld.c
View File

@ -107,10 +107,10 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH23_HANDLER) {
OSAL_IRQ_PROLOGUE();
/* Check on channel 2.*/
dmaServeInterrupt(DMA1, 2);
dmaServeInterrupt(STM32_DMA1_STREAM2);
/* Check on channel 3.*/
dmaServeInterrupt(DMA1, 3);
dmaServeInterrupt(STM32_DMA1_STREAM3);
OSAL_IRQ_EPILOGUE();
}
@ -127,19 +127,19 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH4567_HANDLER) {
OSAL_IRQ_PROLOGUE();
/* Check on channel 4.*/
dmaServeInterrupt(DMA1, 4);
dmaServeInterrupt(STM32_DMA1_STREAM4);
/* Check on channel 5.*/
dmaServeInterrupt(DMA1, 5);
dmaServeInterrupt(STM32_DMA1_STREAM5);
#if STM32_DMA1_NUM_CHANNELS > 5
/* Check on channel 6.*/
dmaServeInterrupt(DMA1, 6);
dmaServeInterrupt(STM32_DMA1_STREAM6);
#endif
#if STM32_DMA1_NUM_CHANNELS > 6
/* Check on channel 7.*/
dmaServeInterrupt(DMA1, 7);
dmaServeInterrupt(STM32_DMA1_STREAM7);
#endif
OSAL_IRQ_EPILOGUE();
@ -159,16 +159,16 @@ OSAL_IRQ_HANDLER(STM32_DMA12_CH23_CH12_HANDLER) {
OSAL_IRQ_PROLOGUE();
/* Check on channel 2 of DMA1.*/
dmaServeInterrupt(DMA1, 2);
dmaServeInterrupt(STM32_DMA1_STREAM2);
/* Check on channel 3 of DMA1.*/
dmaServeInterrupt(DMA1, 3);
dmaServeInterrupt(STM32_DMA1_STREAM3);
/* Check on channel 1 of DMA2.*/
dmaServeInterrupt(DMA2, 1);
dmaServeInterrupt(STM32_DMA2_STREAM1);
/* Check on channel 2 of DMA2.*/
dmaServeInterrupt(DMA2, 2);
dmaServeInterrupt(STM32_DMA2_STREAM2);
OSAL_IRQ_EPILOGUE();
}
@ -187,25 +187,25 @@ OSAL_IRQ_HANDLER(STM32_DMA12_CH4567_CH345_HANDLER) {
OSAL_IRQ_PROLOGUE();
/* Check on channel 4 of DMA1.*/
dmaServeInterrupt(DMA1, 4);
dmaServeInterrupt(STM32_DMA1_STREAM4);
/* Check on channel 5 of DMA1.*/
dmaServeInterrupt(DMA1, 5);
dmaServeInterrupt(STM32_DMA1_STREAM5);
/* Check on channel 6 of DMA1.*/
dmaServeInterrupt(DMA1, 6);
dmaServeInterrupt(STM32_DMA1_STREAM6);
/* Check on channel 7 of DMA1.*/
dmaServeInterrupt(DMA1, 7);
dmaServeInterrupt(STM32_DMA1_STREAM7);
/* Check on channel 3 of DMA2.*/
dmaServeInterrupt(DMA2, 3);
dmaServeInterrupt(STM32_DMA1_STREAM3);
/* Check on channel 4 of DMA2.*/
dmaServeInterrupt(DMA2, 4);
dmaServeInterrupt(STM32_DMA1_STREAM4);
/* Check on channel 5 of DMA2.*/
dmaServeInterrupt(DMA2, 5);
dmaServeInterrupt(STM32_DMA1_STREAM5);
OSAL_IRQ_EPILOGUE();
}

4
os/hal/ports/STM32/STM32F1xx/hal_lld.c
View File

@ -104,10 +104,10 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH45_HANDLER) {
OSAL_IRQ_PROLOGUE();
/* Check on channel 4 of DMA2.*/
dmaServeInterrupt(DMA2, 4);
dmaServeInterrupt(STM32_DMA2_STREAM4);
/* Check on channel 5 of DMA2.*/
dmaServeInterrupt(DMA2, 5);
dmaServeInterrupt(STM32_DMA2_STREAM5);
OSAL_IRQ_EPILOGUE();
}

13
os/hal/ports/STM32/STM32L0xx/hal_lld.c
View File

@ -99,10 +99,10 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH23_HANDLER) {
OSAL_IRQ_PROLOGUE();
/* Check on channel 2.*/
dmaServeInterrupt(DMA1, 2);
dmaServeInterrupt(STM32_DMA1_STREAM2);
/* Check on channel 3.*/
dmaServeInterrupt(DMA1, 3);
dmaServeInterrupt(STM32_DMA1_STREAM3);
OSAL_IRQ_EPILOGUE();
}
@ -119,19 +119,19 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH4567_HANDLER) {
OSAL_IRQ_PROLOGUE();
/* Check on channel 4.*/
dmaServeInterrupt(DMA1, 4);
dmaServeInterrupt(STM32_DMA1_STREAM4);
/* Check on channel 5.*/
dmaServeInterrupt(DMA1, 5);
dmaServeInterrupt(STM32_DMA1_STREAM5);
#if STM32_DMA1_NUM_CHANNELS > 5
/* Check on channel 6.*/
dmaServeInterrupt(DMA1, 6);
dmaServeInterrupt(STM32_DMA1_STREAM6);
#endif
#if STM32_DMA1_NUM_CHANNELS > 6
/* Check on channel 7.*/
dmaServeInterrupt(DMA1, 7);
dmaServeInterrupt(STM32_DMA1_STREAM7);
#endif
OSAL_IRQ_EPILOGUE();
@ -139,7 +139,6 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH4567_HANDLER) {
#endif /* defined(STM32_DMA1_CH4567_HANDLER) */
#endif /* defined(STM32_DMA_REQUIRED) */
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/