diff --git a/os/hal/platforms/STM32F30x/adc_lld.c b/os/hal/platforms/STM32F30x/adc_lld.c index ba23febc3..40cd516a1 100644 --- a/os/hal/platforms/STM32F30x/adc_lld.c +++ b/os/hal/platforms/STM32F30x/adc_lld.c @@ -214,7 +214,7 @@ static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) { * @brief ADC ISR service routine. * * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] isr pre-shifted content of the ISR register + * @param[in] isr content of the ISR register */ static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) { diff --git a/os/hal/platforms/STM32F37x/adc_lld.c b/os/hal/platforms/STM32F37x/adc_lld.c index 47e2c332e..98af50a75 100644 --- a/os/hal/platforms/STM32F37x/adc_lld.c +++ b/os/hal/platforms/STM32F37x/adc_lld.c @@ -37,6 +37,21 @@ int debugzero = 0; /* Driver local definitions. */ /*===========================================================================*/ +#define SDADC_FORBIDDEN_CR1_FLAGS (SDADC_CR1_INIT | SDADC_CR1_RDMAEN | \ + SDADC_CR1_RSYNC | SDADC_CR1_JSYNC | \ + SDADC_CR1_ROVRIE | SDADC_CR1_REOCIE | \ + SDADC_CR1_JEOCIE | SDADC_CR1_EOCALIE) + +#define SDADC_ENFORCED_CR1_FLAGS (SDADC_CR1_JDMAEN | SDADC_CR1_JOVRIE) + +#define SDADC_FORBIDDEN_CR2_FLAGS (SDADC_CR2_RSWSTART | \ + SDADC_CR2_RCONT | \ + SDADC_CR2_RCH | \ + SDADC_CR2_JSWSTART | \ + SDADC_CR2_JCONT | \ + SDADC_CR2_STARTCALIB | \ + SDADC_CR2_CALIBCNT) + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -87,7 +102,7 @@ ADCDriver SDADCD3; * * @notapi */ -static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { +static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) { /* DMA errors handling.*/ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { /* DMA, this could help only if the DMA tries to access an unmapped @@ -110,26 +125,129 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { } } +#if STM32_ADC_USE_ADC +/** + * @brief ADC ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] sr content of the ISR register + */ +static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t sr) { + + /* It could be a spurious interrupt caused by overflows after DMA disabling, + just ignore it in this case.*/ + if (adcp->grpp != NULL) { + if (sr & ADC_SR_AWD) { + /* Analog watchdog error.*/ + _adc_isr_error_code(adcp, ADC_ERR_AWD1); + } + } +} +#endif /* STM32_ADC_USE_ADC */ + +#if STM32_ADC_USE_SDADC +/** + * @brief ADC ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] isr content of the ISR register + */ +static void sdadc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) { + + /* It could be a spurious interrupt caused by overflows after DMA disabling, + just ignore it in this case.*/ + if (adcp->grpp != NULL) { + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((isr & SDADC_ISR_JOVRF) && + (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW); + } + } +} +#endif /* STM32_ADC_USE_SDADC */ + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ #if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) /** - * @brief ADC interrupt handler. + * @brief ADC1 interrupt handler. * * @isr */ CH_IRQ_HANDLER(Vector88) { + uint32_t sr; + CH_IRQ_PROLOGUE(); -#if STM32_ADC_USE_ADC1 - /* TODO: Add here analog watchdog handling.*/ -#endif /* STM32_ADC_USE_ADC1 */ + sr = ADC1->SR; + ADC1->SR = 0; + adc_lld_serve_interrupt(&ADCD1, sr); CH_IRQ_EPILOGUE(); } -#endif +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__) +/** + * @brief SDADC1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector134) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = SDADC1->ISR; + SDADC1->CLRISR = isr; + sdadc_lld_serve_interrupt(&SDADCD1, isr); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ADC_USE_SDADC1 */ + +#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__) +/** + * @brief SDADC2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector138) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = SDADC2->ISR; + SDADC2->CLRISR = isr; + sdadc_lld_serve_interrupt(&SDADCD2, isr); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ADC_USE_SDADC2 */ + +#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__) +/** + * @brief SDADC3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector13C) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = SDADC3->ISR; + SDADC3->CLRISR = isr; + sdadc_lld_serve_interrupt(&SDADCD3, isr); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ADC_USE_SDADC3 */ /*===========================================================================*/ /* Driver exported functions. */ @@ -214,135 +332,84 @@ void adc_lld_init(void) { #endif } -#if 0 -/** - * @brief Initial config for SDADC peripheral. - * - * @param[in] adcdp pointer to the @p ADCDriver object - * @param[in] dmaPriority priority for the dma channel 0..3 - * @param[in] rxIsrFunc isr handler for dma, - * @param[in] dmaSrcLoc pointer to the @p SDADC data - * @param[in] periphEnableBit SDADC bit in rcc APB2 Enable register - * - * @notapi - */ -void sdadc_lld_start_cr_init_helper(ADCDriver* adcdp, - uint32_t dmaPriority, - stm32_dmaisr_t rxIsrFunc, - volatile void* dmaSrcLoc, - uint32_t periphEnableBit) { - bool_t b; - b = dmaStreamAllocate(adcdp->dmastp, - dmaPriority, - rxIsrFunc, - adcdp); - chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); - dmaStreamSetPeripheral(adcdp->dmastp, dmaSrcLoc); - rccEnableAPB2(periphEnableBit, FALSE); - rccResetAPB2(periphEnableBit); - - /* SDADC initial setup, starting the analog part here in order to reduce - the latency when starting a conversion.*/ - - /* - ====== SDADC CR1 settings breakdown ===== - Initialization mode request : disabled - DMA Enabled to read data for reg ch. grp : disabled - DMA Enabled to read data for inj ch. grp : disabled - Launch reg conv sync w SDADC1 : Do not - Launch injected conv sync w SDADC1 : Do not - Enter power down mode when idle : False - Enter standby mode when idle : False - Slow clock mode : fast mode - Reference voltage selection : external Vref - reg data overrun interrupt : disabled - reg data end of conversion interrupt : disabled - injected data overrun interrupt : disabled - injected data end of conversion interrupt : disabled - end of calibration interrupt : disabled - */ - adcdp->sdadc->CR1 = 0; - - /* - ====== SDADC CR1 settings breakdown ===== - SDADC enable : X - Number of calibration sequences to be performed : 0 - Start calibration : NO - Continuous mode selection for injected conv : once - Delay start of injected conversions : asap - Trig sig sel for launching inj conv : TIM13_CH1,TIM17_CH1, TIM16_CH1 - Trig en and trig edge sel for injected conv : disabled - Start a conv of the inj group of ch : 0 - Regular channel sel (0-8) : 0 - Continuous mode sel for regular conv : once - Software start of a conversion on the regular ch: 0 - Fast conv mode sel : disabled - */ - adcdp->sdadc->CR2 = 0; - adcdp->sdadc->CR2 = SDADC_CR2_ADON; -} -#endif - /** * @brief Configures and activates the ADC peripheral. * - * @param[in] adcdp pointer to the @p ADCDriver object + * @param[in] adcp pointer to the @p ADCDriver object * * @notapi */ -void adc_lld_start(ADCDriver *adcdp) { +void adc_lld_start(ADCDriver *adcp) { /* If in stopped state then enables the ADC and DMA clocks.*/ - if (adcdp->state == ADC_STOP) { + if (adcp->state == ADC_STOP) { #if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcdp) { + if (&ADCD1 == adcp) { bool_t b; - b = dmaStreamAllocate(adcdp->dmastp, + b = dmaStreamAllocate(adcp->dmastp, STM32_ADC_ADC1_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, - (void *)adcdp); + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); - dmaStreamSetPeripheral(adcdp->dmastp, &ADC1->DR); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); rccEnableADC1(FALSE); /* ADC initial setup, starting the analog part here in order to reduce the latency when starting a conversion.*/ - adcdp->adc->CR1 = 0; - adcdp->adc->CR2 = 0; - adcdp->adc->CR2 = ADC_CR2_ADON; + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; } #endif /* STM32_ADC_USE_ADC1 */ #if STM32_ADC_USE_SDADC1 - if (&SDADCD1 == adcdp) { - sdadc_lld_start_cr_init_helper(adcdp, - STM32_ADC_SDADC1_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t) adc_lld_serve_rx_interrupt, - &SDADC1->RDATAR, - RCC_APB2ENR_SDADC1EN); + if (&SDADCD1 == adcp) { + bool_t b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_SDADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &SDADC1->JDATAR); + rccEnableSDADC1(FALSE); PWR->CR |= PWR_CR_SDADC1EN; + adcp->sdadc->CR2 = 0; + adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & + ~SDADC_FORBIDDEN_CR1_FLAGS; + adcp->sdadc->CR2 = SDADC_CR2_ADON; } #endif /* STM32_ADC_USE_SDADC1 */ #if STM32_ADC_USE_SDADC2 - if (&SDADCD2 == adcdp) { - sdadc_lld_start_cr_init_helper(adcdp, - STM32_ADC_SDADC2_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t) adc_lld_serve_rx_interrupt, - &SDADC2->RDATAR, - RCC_APB2ENR_SDADC2EN); + if (&SDADCD2 == adcp) { + bool_t b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_SDADC2_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR); + rccEnableSDADC1(FALSE); PWR->CR |= PWR_CR_SDADC2EN; + adcp->sdadc->CR2 = 0; + adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & + ~SDADC_FORBIDDEN_CR1_FLAGS; + adcp->sdadc->CR2 = SDADC_CR2_ADON; } #endif /* STM32_ADC_USE_SDADC2 */ #if STM32_ADC_USE_SDADC3 - if (&SDADCD3 == adcdp) { - sdadc_lld_start_cr_init_helper(adcdp, - STM32_ADC_SDADC3_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t) adc_lld_serve_rx_interrupt, - &SDADC3->RDATAR, - RCC_APB2ENR_SDADC3EN); + if (&SDADCD3 == adcp) { + bool_t b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_SDADC3_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #4", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR); + rccEnableSDADC1(FALSE); PWR->CR |= PWR_CR_SDADC3EN; + adcp->sdadc->CR2 = 0; + adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & + ~SDADC_FORBIDDEN_CR1_FLAGS; + adcp->sdadc->CR2 = SDADC_CR2_ADON; } #endif /* STM32_ADC_USE_SDADC3 */ } @@ -351,46 +418,46 @@ void adc_lld_start(ADCDriver *adcdp) { /** * @brief Deactivates the ADC peripheral. * - * @param[in] adcdp pointer to the @p ADCDriver object + * @param[in] adcp pointer to the @p ADCDriver object * * @notapi */ -void adc_lld_stop(ADCDriver *adcdp) { +void adc_lld_stop(ADCDriver *adcp) { /* If in ready state then disables the ADC clock.*/ - if (adcdp->state == ADC_READY) { - dmaStreamRelease(adcdp->dmastp); + if (adcp->state == ADC_READY) { + dmaStreamRelease(adcp->dmastp); #if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcdp) { - adcdp->adc->CR1 = 0; - adcdp->adc->CR2 = 0; + if (&ADCD1 == adcp) { + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; rccDisableADC1(FALSE); } #endif #if STM32_ADC_USE_SDADC1 - if (&SDADCD1 == adcdp) { - adcdp->sdadc-CR1 = 0; - adcdp->sdadc-CR2 = 0; + if (&SDADCD1 == adcp) { + adcp->sdadc->CR1 = 0; + adcp->sdadc->CR2 = 0; rccDisableSDADC1(FALSE); PWR->CR &= ~PWR_CR_SDADC1EN; } #endif #if STM32_ADC_USE_SDADC2 - if (&SDADCD2 == adcdp) { - adcdp->sdadc-CR1 = 0; - adcdp->sdadc-CR2 = 0; + if (&SDADCD2 == adcp) { + adcp->sdadc->CR1 = 0; + adcp->sdadc->CR2 = 0; rccDisableSDADC2(FALSE); PWR->CR &= ~PWR_CR_SDADC2EN; } #endif #if STM32_ADC_USE_SDADC3 - if (&SDADCD3 == adcdp) { - adcdp->sdadc-CR1 = 0; - adcdp->sdadc-CR2 = 0; + if (&SDADCD3 == adcp) { + adcp->sdadc->CR1 = 0; + adcp->sdadc->CR2 = 0; rccDisableSDADC3(FALSE); PWR->CR &= ~PWR_CR_SDADC3EN; } @@ -401,77 +468,87 @@ void adc_lld_stop(ADCDriver *adcdp) { /** * @brief Starts an ADC conversion. * - * @param[in] adcdp pointer to the @p ADCDriver object + * @param[in] adcp pointer to the @p ADCDriver object * * @notapi */ -void adc_lld_start_conversion(ADCDriver *adcdp) { +void adc_lld_start_conversion(ADCDriver *adcp) { uint32_t mode; - const ADCConversionGroup* grpp = adcdp->grpp; + const ADCConversionGroup* grpp = adcp->grpp; /* DMA setup.*/ - mode = adcdp->dmamode; + mode = adcp->dmamode; if (grpp->circular) { mode |= STM32_DMA_CR_CIRC; } - if (adcdp->depth > 1) { + if (adcp->depth > 1) { /* If the buffer depth is greater than one then the half transfer interrupt interrupt is enabled in order to allows streaming processing.*/ mode |= STM32_DMA_CR_HTIE; } - dmaStreamSetMemory0(adcdp->dmastp, adcdp->samples); - dmaStreamSetTransactionSize(adcdp->dmastp, + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * - (uint32_t)adcdp->depth); - dmaStreamSetMode(adcdp->dmastp, mode); - dmaStreamEnable(adcdp->dmastp); + (uint32_t)adcp->depth); + dmaStreamSetMode(adcp->dmastp, mode); + dmaStreamEnable(adcp->dmastp); #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC - if (adcdp->adc != NULL) { + if (adcp->adc != NULL) #endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ #if STM32_ADC_USE_ADC - /* ADC setup.*/ - adcdp->adc->SR = 0; - adcdp->adc->SMPR1 = grpp->u.adc.smpr[0]; - adcdp->adc->SMPR2 = grpp->u.adc.smpr[1]; - adcdp->adc->SQR1 = grpp->u.adc.sqr[0] | - ADC_SQR1_NUM_CH(grpp->num_channels); - adcdp->adc->SQR2 = grpp->u.adc.sqr[1]; - adcdp->adc->SQR3 = grpp->u.adc.sqr[2]; + { + uint32_t cr2 = ADC_CR2_ADON; - /* ADC configuration and start, the start is performed using the method + /* ADC setup.*/ + adcp->adc->SR = 0; + adcp->adc->LTR = grpp->u.adc.htr; + adcp->adc->HTR = grpp->u.adc.htr; + adcp->adc->SMPR1 = grpp->u.adc.smpr[0]; + adcp->adc->SMPR2 = grpp->u.adc.smpr[1]; + adcp->adc->SQR1 = grpp->u.adc.sqr[0] | + ADC_SQR1_NUM_CH(grpp->num_channels); + adcp->adc->SQR2 = grpp->u.adc.sqr[1]; + adcp->adc->SQR3 = grpp->u.adc.sqr[2]; + + /* ADC conversion start, the start is performed using the method specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ - adcdp->adc->CR1 = grpp->u.adc.cr1 | ADC_CR1_SCAN; + adcp->adc->CR1 = grpp->u.adc.cr1 | ADC_CR1_AWDIE | ADC_CR1_SCAN; if ((grpp->u.adc.cr2 & ADC_CR2_SWSTART) != 0) - adcdp->adc->CR2 = grpp->u.adc.cr2 | ADC_CR2_CONT - | ADC_CR2_DMA | ADC_CR2_ADON; - else - adcdp->adc->CR2 = grpp->u.adc.cr2 | ADC_CR2_DMA | ADC_CR2_ADON; + cr2 |= ADC_CR2_CONT; + adcp->adc->CR2 = grpp->u.adc.cr2 | cr2 | ADC_CR2_DMA | ADC_CR2_ADON; + } #endif /* STM32_ADC_USE_ADC */ #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC - } - else if (adcdp->sdadc != NULL) { + else if (adcp->sdadc != NULL) #endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ #if STM32_ADC_USE_SDADC - /* SDADC setup.*/ - sdadcSTM32SetInitializationMode(adcdp, true); + { + uint32_t cr2 = SDADC_CR2_ADON; + + /* Entering initialization mode.*/ + adcp->sdadc->CR1 |= SDADC_CR1_INIT; + while ((adcp->sdadc->ISR & SDADC_ISR_INITRDY) == 0) + ; /* SDADC setup.*/ - adcdp->sdadc->CONF0R = grpp->ll.sdadc.conf0r; - adcdp->sdadc->CONF1R = grpp->ll.sdadc.conf1r; - adcdp->sdadc->CONF2R = grpp->ll.sdadc.conf2r; - adcdp->sdadc->CONFCHR1 = grpp->ll.sdadc.confchr1; - adcdp->sdadc->CONFCHR2 = grpp->ll.sdadc.confchr2; + adcp->sdadc->CONF0R = grpp->u.sdadc.confxr[0]; + adcp->sdadc->CONF1R = grpp->u.sdadc.confxr[1]; + adcp->sdadc->CONF2R = grpp->u.sdadc.confxr[2]; + adcp->sdadc->CONFCHR1 = grpp->u.sdadc.confchr[0]; + adcp->sdadc->CONFCHR2 = grpp->u.sdadc.confchr[1]; - sdadcSTM32SetInitializationMode(adcdp, false); + /* Leaving initialization mode.*/ + adcp->sdadc->CR1 &= ~SDADC_CR1_INIT; - /* SDADC configuration and start, the start is performed using the method - specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ - adcdp->sdadc->CR1 = grpp->ll.sdadc.cr1 | SDADC_CR1_RDMAEN; - adcdp->sdadc->CR2 = grpp->ll.sdadc.cr2 | SDADC_CR2_ADON; + /* SDADC conversion start, the start is performed using the method + specified in the CR2 configuration, usually SDADC_CR2_JSWSTART.*/ + if ((grpp->u.sdadc.cr2 & SDADC_CR2_JSWSTART) != 0) + cr2 |= SDADC_CR2_JCONT; + adcp->sdadc->CR2 = (grpp->u.sdadc.cr2 & ~SDADC_FORBIDDEN_CR2_FLAGS) | cr2; + } #endif /* STM32_ADC_USE_SDADC */ #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC - } else { chDbgAssert(FALSE, "adc_lld_start_conversion(), #1", "invalid state"); } @@ -481,117 +558,153 @@ void adc_lld_start_conversion(ADCDriver *adcdp) { /** * @brief Stops an ongoing conversion. * - * @param[in] adcdp pointer to the @p ADCDriver object + * @param[in] adcp pointer to the @p ADCDriver object * * @notapi */ -void adc_lld_stop_conversion(ADCDriver *adcdp) { +void adc_lld_stop_conversion(ADCDriver *adcp) { /* Disabling the associated DMA stream.*/ - dmaStreamDisable(adcdp->dmastp); + dmaStreamDisable(adcp->dmastp); #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC - if (adcdp->adc != NULL) { + if (adcp->adc != NULL) #endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ #if STM32_ADC_USE_ADC - adcdp->adc->CR1 = 0; - adcdp->adc->CR2 = 0; - adcdp->adc->CR2 = ADC_CR2_ADON; + { + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; + } #endif /* STM32_ADC_USE_ADC */ #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC - } - else if (adcdp->sdadc != NULL) { + else if (adcp->sdadc != NULL) #endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ #if STM32_ADC_USE_SDADC - adcdp->sdadc->CR1 = 0; - adcdp->sdadc->CR2 = 0; - adcdp->sdadc->CR2 = ADC_CR2_ADON; + { + adcp->sdadc->CR1 = 0; + adcp->sdadc->CR2 = 0; + adcp->sdadc->CR2 = ADC_CR2_ADON; + } #endif /* STM32_ADC_USE_SDADC */ #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC - } else { chDbgAssert(FALSE, "adc_lld_stop_conversion(), #1", "invalid state"); } #endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ } -#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__) /** - * @brief Sets the VREF for the 3 Sigma-Delta ADC Converters - * @details VREF can be changed only when all SDADCs are disabled. Disables all SDADCs, sets the value and then sleeps 5 ms waiting for the change to occur. - * @note This is an STM32-only functionality. - * @param[in] adcdp pointer to the @p ADCDriver object - * @param[in] enable true means init mode, false means exit init mode + * @brief Calibrates an ADC unit. + * @note The calibration must be performed after calling @p adcStart(). + * @note For SDADC units it is assumed that the field SDADC_CR2_CALIBCNT + * has been * - */ -void sdadcSTM32VREFSelect(SDADC_VREF_SEL svs) -{ - uint32_t tmpcr1, sdadc1_adon, sdadc2_adon, sdadc3_adon; - - sdadc1_adon = SDADC1->CR2 & SDADC_CR2_ADON; - sdadc2_adon = SDADC2->CR2 & SDADC_CR2_ADON; - sdadc3_adon = SDADC3->CR2 & SDADC_CR2_ADON; - - SDADC1->CR2 &= ~SDADC_CR2_ADON; - SDADC2->CR2 &= ~SDADC_CR2_ADON; - SDADC3->CR2 &= ~SDADC_CR2_ADON; - - /* Get SDADC1_CR1 register value */ - tmpcr1 = SDADC1->CR1; - - /* Clear the SDADC1_CR1_REFV bits */ - tmpcr1 &= (uint32_t) (~SDADC_CR1_REFV); - - /* Select the external reference voltage */ - tmpcr1 |= svs; - - /* Write in SDADC_CR1 */ - SDADC1->CR1 = tmpcr1; - - /* Insert delay equal to ~10 ms (4 ms required) */ - chThdSleepMilliseconds(5); - - SDADC1->CR2 |= sdadc1_adon; - SDADC2->CR2 |= sdadc2_adon; - SDADC3->CR2 |= sdadc3_adon; -} - -/** - * @brief Sets the Sigma-Delta ADC Converter into initialization mode - * @details The sdadc is either put into init mode or exits init mode. - * @note This is an STM32-only functionality. - * @note This function is meant to be called after @p adcStart(). - * @param[in] adcdp pointer to the @p ADCDriver object - * @param[in] enable true means init mode, false means exit init mode + * @param[in] adcp pointer to the @p ADCDriver object * + * @api */ -void sdadcSTM32SetInitializationMode(ADCDriver* adcdp, bool_t enterInitMode) -{ - uint32_t SDADCTimeout = 300000; +void adcSTM32Calibrate(ADCDriver *adcp) { - if ((adcdp == &SDADCD1) || - (adcdp == &SDADCD2) || - (adcdp == &SDADCD3)) { + chDbgAssert((adcp->state == ADC_READY) || + (adcp->state == ADC_COMPLETE) || + (adcp->state == ADC_ERROR), + "adcSTM32Calibrate(), #1", "not ready"); - if (enterInitMode) { - adcdp->sdadc->CR1 |= SDADC_CR1_INIT; +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + if (adcp->adc != NULL) +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_ADC + { + /* Resetting calibration just to be safe.*/ + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; + while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0) + ; - /* wait for INITRDY flag to be set */ - while (((adcdp->sdadc->ISR & SDADC_ISR_INITRDY) == 0) && - (--SDADCTimeout != 0)); - - if (SDADCTimeout == 0) - { - /* INITRDY flag can not set */ - port_halt(); - } - } - else { - adcdp->sdadc->CR1 &= ~SDADC_CR1_INIT; - } + /* Calibration.*/ + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL; + while ((ADC1->CR2 & ADC_CR2_CAL) != 0) + ; } +#endif /* STM32_ADC_USE_ADC */ +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + else if (adcp->sdadc != NULL) +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_SDADC + { + /* Selecting a full calibration in three steps.*/ + adcp->sdadc->CR2 = (adcp->sdadc->CR2 & ~SDADC_CR2_CALIBCNT) | + SDADC_CR2_CALIBCNT_1; + + /* Calibration.*/ + adcp->sdadc->CR2 |= SDADC_CR2_STARTCALIB; + while ((adcp->sdadc->ISR & SDADC_ISR_EOCALF) == 0) + ; + + /* Clearing the EOCALF flag.*/ + adcp->sdadc->CLRISR |= SDADC_ISR_CLREOCALF; + } +#endif /* STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + else { + chDbgAssert(FALSE, "adcSTM32Calibrate(), #2", "invalid state"); + } +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ } +#if STM32_ADC_USE_ADC || defined(__DOXYGEN__) +/** + * @brief Enables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + * + * @api + */ +void adcSTM32EnableTSVREFE(void) { + + ADC1->CR2 |= ADC_CR2_TSVREFE; +} + +/** + * @brief Disables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + * + * @api + */ +void adcSTM32DisableTSVREFE(void) { + + ADC1->CR2 &= ~ADC_CR2_TSVREFE; +} + +/** + * @brief Enables the VBATE bit. + * @details The VBATE bit is required in order to sample the VBAT channel. + * @note This is an STM32-only functionality. + * + * @api + */ +void adcSTM32EnableVBATE(void) { + + SYSCFG->CFGR1 |= SYSCFG_CFGR1_VBAT; +} + +/** + * @brief Disables the VBATE bit. + * @details The VBATE bit is required in order to sample the VBAT channel. + * @note This is an STM32-only functionality. + * + * @api + */ +void adcSTM32DisableVBATE(void) { + + SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_VBAT; +} +#endif /* STM32_ADC_USE_ADC */ + +#if 0 || defined(__DOXYGEN__) /** * @brief Configures the calibration sequence. * @note TODO - UPDATE @@ -608,33 +721,33 @@ void sdadcSTM32SetInitializationMode(ADCDriver* adcdp, bool_t enterInitMode) * and OFFSET2[11:0] (offsets that correspond to conf0, conf1 and conf2) * @retval None */ -void sdadcSTM32Calibrate(ADCDriver* adcdp, +void sdadcSTM32Calibrate(ADCDriver* adcp, SDADC_NUM_CALIB_SEQ numCalibSequences, ADCConversionGroup* grpp) { uint32_t SDADCTimeout = 0; uint32_t tmpcr2 = 0; - if (!(adcdp == &SDADCD1 || - adcdp == &SDADCD2 || - adcdp == &SDADCD3)) + if (!(adcp == &SDADCD1 || + adcp == &SDADCD2 || + adcp == &SDADCD3)) return; - sdadcSTM32SetInitializationMode(adcdp, true); + sdadcSTM32SetInitializationMode(adcp, true); /* SDADC setup.*/ - adcdp->sdadc->CR2 = grpp->ll.sdadc.cr2; - adcdp->sdadc->CONF0R = grpp->ll.sdadc.conf0r; - adcdp->sdadc->CONF1R = grpp->ll.sdadc.conf1r; - adcdp->sdadc->CONF2R = grpp->ll.sdadc.conf2r; - adcdp->sdadc->CONFCHR1 = grpp->ll.sdadc.confchr1; - adcdp->sdadc->CONFCHR2 = grpp->ll.sdadc.confchr2; + adcp->sdadc->CR2 = grpp->ll.sdadc.cr2; + adcp->sdadc->CONF0R = grpp->ll.sdadc.conf0r; + adcp->sdadc->CONF1R = grpp->ll.sdadc.conf1r; + adcp->sdadc->CONF2R = grpp->ll.sdadc.conf2r; + adcp->sdadc->CONFCHR1 = grpp->ll.sdadc.confchr1; + adcp->sdadc->CONFCHR2 = grpp->ll.sdadc.confchr2; - sdadcSTM32SetInitializationMode(adcdp, false); + sdadcSTM32SetInitializationMode(adcp, false); /* configure calibration to be performed on conf0 */ /* Get SDADC_CR2 register value */ - tmpcr2 = adcdp->sdadc->CR2; + tmpcr2 = adcp->sdadc->CR2; /* Clear the SDADC_CR2_CALIBCNT bits */ tmpcr2 &= (uint32_t) (~SDADC_CR2_CALIBCNT); @@ -645,13 +758,13 @@ void sdadcSTM32Calibrate(ADCDriver* adcdp, Write in SDADC_CR2 and start calibration */ - adcdp->sdadc->CR2 = tmpcr2 | SDADC_CR2_STARTCALIB; + adcp->sdadc->CR2 = tmpcr2 | SDADC_CR2_STARTCALIB; /* Set calibration timeout: 5.12 ms at 6 MHz in a single calibration sequence */ SDADCTimeout = SDADC_CAL_TIMEOUT; /* wait for SDADC Calibration process to end */ - while (((adcdp->sdadc->ISR & SDADC_ISR_EOCALF) == 0) && (--SDADCTimeout != 0)); + while (((adcp->sdadc->ISR & SDADC_ISR_EOCALF) == 0) && (--SDADCTimeout != 0)); if(SDADCTimeout == 0) { @@ -661,7 +774,7 @@ void sdadcSTM32Calibrate(ADCDriver* adcdp, } /* cleanup by clearing EOCALF flag */ - adcdp->sdadc->CLRISR |= SDADC_ISR_CLREOCALF; + adcp->sdadc->CLRISR |= SDADC_ISR_CLREOCALF; } #endif /* STM32_ADC_USE_SDADC */ diff --git a/os/hal/platforms/STM32F37x/adc_lld.h b/os/hal/platforms/STM32F37x/adc_lld.h index 252b07f08..240bd9a67 100644 --- a/os/hal/platforms/STM32F37x/adc_lld.h +++ b/os/hal/platforms/STM32F37x/adc_lld.h @@ -155,14 +155,6 @@ #define STM32_ADC_USE_SDADC3 FALSE #endif -/** - * @brief SDADC slow mode switch. - * @details If set to @p TRUE all SDADCs operate in slow mode. - */ -#if !defined(STM32_ADC_SDADC_SLOW_MODE) || defined(__DOXYGEN__) -#define STM32_ADC_SDADC_SLOW_MODE FALSE -#endif - /** * @brief ADC1 DMA priority (0..3|lowest..highest). */ @@ -369,7 +361,8 @@ typedef uint16_t adc_channels_num_t; */ typedef enum { ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ - ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */ + ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */ + ADC_ERR_AWD1 = 2 /**< Watchdog 1 triggered. */ } adcerror_t; /** @@ -445,6 +438,18 @@ typedef struct { * enforced inside the driver. */ uint32_t cr2; + /** + * @brief ADC LTR register initialization data. + * @note Set to zero in order to disable the low threshold of the + * analog watchdog. + */ + uint32_t ltr; + /** + * @brief ADC HTR register initialization data. + * @note Set to 4095 (0xFFF) in order to disable the high threshold + * of the analog watchdog. + */ + uint32_t htr; /** * @brief ADC SMPRx registers initialization data. */ @@ -459,9 +464,8 @@ typedef struct { struct { /** * @brief SDADC CR2 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are - * enforced inside the driver. + * @note Only the @p SDADC_CR2_JSWSTART, @p SDADC_CR2_JEXTSEL + * and @p SDADC_CR2_JEXTEN can be specified in this field. */ uint32_t cr2; /** @@ -469,25 +473,13 @@ typedef struct { */ uint32_t jchgr; /** - * @brief SDADC CONF0R register initialization data. + * @brief SDADC CONFxR registers initialization data. */ - uint32_t conf0r; + uint32_t confxr[3]; /** - * @brief SDADC CONF1R register initialization data. + * @brief SDADC CONFCHxR registers initialization data. */ - uint32_t conf1r; - /** - * @brief SDADC CONF2R register initialization data. - */ - uint32_t conf2r; - /** - * @brief SDADC CONFCH1R register initialization data. - */ - uint32_t confchr1; - /** - * @brief SDADC CONFCH2R register initialization data. - */ - uint32_t confchr2; + uint32_t confchr[2]; } sdadc; #endif /* STM32_ADC_USE_SDADC */ } u; @@ -663,8 +655,14 @@ extern "C" { void adc_lld_stop(ADCDriver *adcp); void adc_lld_start_conversion(ADCDriver *adcp); void adc_lld_stop_conversion(ADCDriver *adcp); -#if STM32_ADC_USE_SDADC - void sdadcSTM32SetInitializationMode(ADCDriver* adcdp, bool_t enterInitMode); + void adcSTM32Calibrate(ADCDriver *adcdp); +#if STM32_ADC_USE_ADC + void adcSTM32EnableTSVREFE(void); + void adcSTM32DisableTSVREFE(void); + void adcSTM32EnableVBATE(void); + void adcSTM32DisableVBATE(void); +#endif /* STM32_ADC_USE_ADC */ +#if 0 void sdadcSTM32VREFSelect(SDADC_VREF_SEL svs); void sdadcSTM32Calibrate(ADCDriver* adcdp, SDADC_NUM_CALIB_SEQ numCalibSequences, ADCConversionGroup* grpp); diff --git a/readme.txt b/readme.txt index f99828d42..93b100cd1 100644 --- a/readme.txt +++ b/readme.txt @@ -142,6 +142,7 @@ platforms, tests to be added on the various sub-families. - NEW: Added support for SPC56ELxx, SPC560BCxx, SPC560Pxx, SPC560Mxx and SPC564Axx platforms. +- NEW: Added ADC/SDADC driver for the STM32F37x family. - NEW: Added support for the STM32F37x family. - NEW: Now the general documentation includes data extracted from the low level driver templates. Per-platform/architecture documents are no more diff --git a/testhal/STM32F37x/ADC/main.c b/testhal/STM32F37x/ADC/main.c index fce807084..c2e81b4c3 100644 --- a/testhal/STM32F37x/ADC/main.c +++ b/testhal/STM32F37x/ADC/main.c @@ -62,13 +62,15 @@ static const ADCConversionGroup adcgrpcfg1 = { NULL, adcerrorcallback, .u.adc = { - 0, /* CR1 */ - 0, /* CR2 */ - { /* SMPR[2] */ + 0, /* CR1 */ + 0, /* CR2 */ + 0, /* LTR */ + 4095, /* HTR */ + { /* SMPR[2] */ 0, 0 }, - { /* SQR[3] */ + { /* SQR[3] */ 0, 0, 0 diff --git a/testhal/STM32F37x/SDADC/.cproject b/testhal/STM32F37x/SDADC/.cproject new file mode 100644 index 000000000..e3d709437 --- /dev/null +++ b/testhal/STM32F37x/SDADC/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F37x/SDADC/.project b/testhal/STM32F37x/SDADC/.project new file mode 100644 index 000000000..83a87eb03 --- /dev/null +++ b/testhal/STM32F37x/SDADC/.project @@ -0,0 +1,38 @@ + + + STM32F37x-SDADC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32373C_EVAL + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F37x/SDADC/Makefile b/testhal/STM32F37x/SDADC/Makefile new file mode 100644 index 000000000..782a3b3d7 --- /dev/null +++ b/testhal/STM32F37x/SDADC/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32373C_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F37x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F373xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F37x/SDADC/chconf.h b/testhal/STM32F37x/SDADC/chconf.h new file mode 100644 index 000000000..40bf50ea7 --- /dev/null +++ b/testhal/STM32F37x/SDADC/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/SDADC/halconf.h b/testhal/STM32F37x/SDADC/halconf.h new file mode 100644 index 000000000..d2db7fafa --- /dev/null +++ b/testhal/STM32F37x/SDADC/halconf.h @@ -0,0 +1,316 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/SDADC/main.c b/testhal/STM32F37x/SDADC/main.c new file mode 100644 index 000000000..c2e81b4c3 --- /dev/null +++ b/testhal/STM32F37x/SDADC/main.c @@ -0,0 +1,180 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +#define ADC_GRP1_NUM_CHANNELS 2 +#define ADC_GRP1_BUF_DEPTH 8 + +#define ADC_GRP2_NUM_CHANNELS 8 +#define ADC_GRP2_BUF_DEPTH 16 + +static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH]; + +/* + * ADC streaming callback. + */ +size_t nx = 0, ny = 0; +static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void)adcp; + if (samples2 == buffer) { + nx += n; + } + else { + ny += n; + } +} + +static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { + + (void)adcp; + (void)err; +} + +/* + * ADC conversion group. + * Mode: Linear buffer, 8 samples of 2 channels, SW triggered. + * Channels: IN7, IN8. + */ +static const ADCConversionGroup adcgrpcfg1 = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + NULL, + adcerrorcallback, + .u.adc = { + 0, /* CR1 */ + 0, /* CR2 */ + 0, /* LTR */ + 4095, /* HTR */ + { /* SMPR[2] */ + 0, + 0 + }, + { /* SQR[3] */ + 0, + 0, + 0 + } + } +}; + +#if 0 +/* + * ADC conversion group. + * Mode: Continuous, 16 samples of 8 channels, SW triggered. + * Channels: IN7, IN8, IN7, IN8, IN7, IN8, Sensor, VBat/2. + */ +static const ADCConversionGroup adcgrpcfg2 = { + TRUE, + ADC_GRP2_NUM_CHANNELS, + adccallback, + adcerrorcallback, + 0, /* CFGR */ + ADC_TR(0, 4095), /* TR1 */ + ADC_CCR_TSEN | ADC_CCR_VBATEN, /* CCR */ + { /* SMPR[2] */ + ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5) + | ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5), + ADC_SMPR2_SMP_AN16(ADC_SMPR_SMP_61P5) + | ADC_SMPR2_SMP_AN17(ADC_SMPR_SMP_61P5), + }, + { /* SQR[4] */ + ADC_SQR1_SQ1_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN8) | + ADC_SQR1_SQ3_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ4_N(ADC_CHANNEL_IN8), + ADC_SQR2_SQ5_N(ADC_CHANNEL_IN7) | ADC_SQR2_SQ6_N(ADC_CHANNEL_IN8) | + ADC_SQR2_SQ7_N(ADC_CHANNEL_IN16) | ADC_SQR2_SQ8_N(ADC_CHANNEL_IN17), + 0, + 0 + } +}; +#endif + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(500); + palSetPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Setting up analog inputs used by the demo. + */ + palSetGroupMode(GPIOC, PAL_PORT_BIT(1) | PAL_PORT_BIT(2), + 0, PAL_MODE_INPUT_ANALOG); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Activates the ADC1 driver and the temperature sensor. + */ + adcStart(&ADCD1, NULL); + + /* + * Linear conversion. + */ + adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH); + chThdSleepMilliseconds(1000); + + /* + * Starts an ADC continuous conversion. + */ +// adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_WKUP_BUTTON)) { +// adcStopConversion(&ADCD1); + } + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F37x/SDADC/mcuconf.h b/testhal/STM32F37x/SDADC/mcuconf.h new file mode 100644 index 000000000..c994b4d55 --- /dev/null +++ b/testhal/STM32F37x/SDADC/mcuconf.h @@ -0,0 +1,193 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F37x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_SDPRE STM32_SDPRE_DIV12 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_SDADC1 TRUE +#define STM32_ADC_USE_SDADC2 TRUE +#define STM32_ADC_USE_SDADC3 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_23_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F37x/SDADC/readme.txt b/testhal/STM32F37x/SDADC/readme.txt new file mode 100644 index 000000000..0e5191419 --- /dev/null +++ b/testhal/STM32F37x/SDADC/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - ADC driver demo for STM32F37x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32373C-EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32F37x ADC driver on the +SDADC peripheral. + +** Board Setup ** + +None. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com