git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3017 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
parent
d08ed6e93c
commit
8aa98a8b06
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@ -21,7 +21,7 @@
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* @file ARMCMx/crt0.c
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* @brief Generic ARMvx-M (Cortex-M0/M1/M3/M4) startup file for ChibiOS/RT.
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*
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* @addtogroup ARMCMx_CORE
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* @addtogroup ARMCMx_STARTUP
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* @{
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*/
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@ -159,17 +159,24 @@
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* - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
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* thread. Usually there is no need to change this value unless inserting
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* code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
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* - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
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* code. Code running at higher priority levels must not invoke any OS API.
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* This setting is specific to the ARMv7-M architecture.
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* - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
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* - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
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* - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
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* - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
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* @p <b>wfi</b> instruction from within the idle loop. This option is
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* defaulted to FALSE because it can create problems with some debuggers.
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* Setting this option to TRUE reduces the system power requirements.
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* .
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* @section ARMCMx_CONF_1 ARMv6-M specific options
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* The following options are specific for the ARMv6-M architecture:
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* - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV
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* exception instead of NMI as preemption handler.
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* .
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* @section ARMCMx_CONF_2 ARMv7-M specific options
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* The following options are specific for the ARMv6-M architecture:
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* - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
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* - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel
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* mode.
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* .
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* @ingroup ARMCMx
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*/
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@ -219,15 +226,19 @@
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* @section ARMCMx_STARTUP_2 Expected linker symbols
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* The startup code starts at the symbol @p ResetHandler and expects the
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* following symbols to be defined in the linker script:
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* - @p __ram_end__ RAM end location +1.
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* - @p __ram_end__ End of RAM.
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* - @p __main_stack_size__ Exception stack size.
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* - @p __process_stack_size__ Process stack size. This is the stack area used
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* by the @p main() function.
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* - @p _textdata address of the data segment source read only data.
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* - @p _data data segment start location.
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* - @p _edata data segment end location +1.
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* - @p _bss_start BSS start location.
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* - @p _bss_end BSS end location +1.
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* - @p _textdata Address of the data segment source read only data.
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* - @p _data Start of the data segment.
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* - @p _edata End of the data segment end location.
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* - @p _bss_start Start of the BSS.
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* - @p _bss_end End of the BSS segment.
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* - @p __init_array_start Start of the constructors array.
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* - @p __init_array_end End of the constructors array.
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* - @p __fini_array_start Start of the destructors array.
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* - @p __fini_array_end End of the destructors array.
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* .
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* @ingroup ARMCMx
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*/
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@ -26,9 +26,28 @@
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* This port supports all the cores implementing the ARMv6-M and ARMv7-M
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* architectures.
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*
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* @section IAR_ARMCMx_STATES_A System logical states in ARMv6-M mode
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* The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
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* Cortex-M0 port:
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* @section IAR_ARMCMx_MODES Kernel Modes
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* The Cortex-Mx port supports two distinct kernel modes:
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* - <b>Advanced Kernel</b> mode. In this mode the kernel only masks
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* interrupt sources with priorities below or equal to the
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* @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by
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* the kernel critical sections and can be used for fast interrupts.
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* This mode is not available in the ARMv6-M architecture which does not
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* support priority masking.
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* - <b>Compact Kernel</b> mode. In this mode the kernel handles IRQ priorities
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* in a simplified way, all interrupt sources are disabled when the kernel
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* enters into a critical zone and re-enabled on exit. This is simple and
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* adequate for most applications, this mode results in a more compact and
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* faster kernel.
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* .
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* The selection of the mode is performed using the port configuration option
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* @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of
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* interrupts there are no other differences between the two modes. The
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* kernel API is exactly the same.
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*
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* @section IAR_ARMCMx_STATES_A System logical states in Compact Kernel mode
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* The ChibiOS/RT logical @ref system_states are mapped as follow in Compact
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* Kernel mode:
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* - <b>Init</b>. This state is represented by the startup code and the
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* initialization code before @p chSysInit() is executed. It has not a
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* special hardware state associated.
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@ -53,21 +72,21 @@
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* mode.
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* - <b>Serving Fast Interrupt</b>. This state is not implemented in the
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* ARMv6-M implementation.
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* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
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* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
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* asynchronous NMI vector and several synchronous fault vectors that can
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* be considered belonging to this category.
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* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
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* the maskable interrupt sources. The ARM state is whatever the processor
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* was running when @p chSysHalt() was invoked.
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*
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* @section IAR_ARMCMx_STATES_B System logical states in ARMv7-M mode
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* The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
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* Cortex-M3 port:
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* @section IAR_ARMCMx_STATES_B System logical states in Advanced Kernel mode
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* The ChibiOS/RT logical @ref system_states are mapped as follow in the
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* Advanced Kernel mode:
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* - <b>Init</b>. This state is represented by the startup code and the
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* initialization code before @p chSysInit() is executed. It has not a
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* special hardware state associated.
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* - <b>Normal</b>. This is the state the system has after executing
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* @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register
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* @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register
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* set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
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* processor is running in thread-privileged mode.
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* - <b>Suspended</b>. In this state the interrupt sources are not globally
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@ -93,7 +112,7 @@
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* - <b>Serving Fast Interrupt</b>. It is basically the same of the SRI state
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* but it is not possible to switch to the I-Locked state because fast
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* interrupts can preempt the kernel critical zone.
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* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
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* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
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* asynchronous NMI vector and several synchronous fault vectors that can
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* be considered belonging to this category.
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* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
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@ -140,17 +159,24 @@
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* - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
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* thread. Usually there is no need to change this value unless inserting
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* code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
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* - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
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* code. Code running at higher priority levels must not invoke any OS API.
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* This setting is specific to the ARMv7-M architecture.
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* - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
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* - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
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* - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
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* - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
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* @p <b>wfi</b> instruction from within the idle loop. This option is
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* defaulted to FALSE because it can create problems with some debuggers.
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* Setting this option to TRUE reduces the system power requirements.
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* .
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* @section IAR_ARMCMx_CONF_1 ARMv6-M specific options
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* The following options are specific for the ARMv6-M architecture:
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* - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV
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* exception instead of NMI as preemption handler.
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* .
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* @section IAR_ARMCMx_CONF_2 ARMv7-M specific options
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* The following options are specific for the ARMv6-M architecture:
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* - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
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* - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel
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* mode.
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* .
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* @ingroup IAR_ARMCMx
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*/
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@ -26,9 +26,28 @@
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* This port supports all the cores implementing the ARMv6-M and ARMv7-M
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* architectures.
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*
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* @section RVCT_ARMCMx_STATES_A System logical states in ARMv6-M mode
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* The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
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* Cortex-M0 port:
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* @section RVCT_ARMCMx_MODES Kernel Modes
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* The Cortex-Mx port supports two distinct kernel modes:
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* - <b>Advanced Kernel</b> mode. In this mode the kernel only masks
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* interrupt sources with priorities below or equal to the
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* @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by
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* the kernel critical sections and can be used for fast interrupts.
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* This mode is not available in the ARMv6-M architecture which does not
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* support priority masking.
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* - <b>Compact Kernel</b> mode. In this mode the kernel handles IRQ priorities
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* in a simplified way, all interrupt sources are disabled when the kernel
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* enters into a critical zone and re-enabled on exit. This is simple and
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* adequate for most applications, this mode results in a more compact and
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* faster kernel.
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* .
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* The selection of the mode is performed using the port configuration option
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* @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of
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* interrupts there are no other differences between the two modes. The
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* kernel API is exactly the same.
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*
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* @section RVCT_ARMCMx_STATES_A System logical states in Compact Kernel mode
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* The ChibiOS/RT logical @ref system_states are mapped as follow in Compact
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* Kernel mode:
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* - <b>Init</b>. This state is represented by the startup code and the
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* initialization code before @p chSysInit() is executed. It has not a
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* special hardware state associated.
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@ -53,21 +72,21 @@
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* mode.
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* - <b>Serving Fast Interrupt</b>. This state is not implemented in the
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* ARMv6-M implementation.
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* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
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* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
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* asynchronous NMI vector and several synchronous fault vectors that can
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* be considered belonging to this category.
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* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
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* the maskable interrupt sources. The ARM state is whatever the processor
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* was running when @p chSysHalt() was invoked.
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*
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* @section RVCT_ARMCMx_STATES_B System logical states in ARMv7-M mode
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* The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
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* Cortex-M3 port:
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* @section RVCT_ARMCMx_STATES_B System logical states in Advanced Kernel mode
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* The ChibiOS/RT logical @ref system_states are mapped as follow in the
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* Advanced Kernel mode:
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* - <b>Init</b>. This state is represented by the startup code and the
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* initialization code before @p chSysInit() is executed. It has not a
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* special hardware state associated.
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* - <b>Normal</b>. This is the state the system has after executing
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* @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register
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* @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register
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* set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
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* processor is running in thread-privileged mode.
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* - <b>Suspended</b>. In this state the interrupt sources are not globally
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@ -93,7 +112,7 @@
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* - <b>Serving Fast Interrupt</b>. It is basically the same of the SRI state
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* but it is not possible to switch to the I-Locked state because fast
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* interrupts can preempt the kernel critical zone.
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* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
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* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
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* asynchronous NMI vector and several synchronous fault vectors that can
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* be considered belonging to this category.
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* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
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@ -140,17 +159,24 @@
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* - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
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* thread. Usually there is no need to change this value unless inserting
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* code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
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* - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
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* code. Code running at higher priority levels must not invoke any OS API.
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* This setting is specific to the ARMv7-M architecture.
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* - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
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* - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
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* - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
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* - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
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* @p <b>wfi</b> instruction from within the idle loop. This option is
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* defaulted to FALSE because it can create problems with some debuggers.
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* Setting this option to TRUE reduces the system power requirements.
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* .
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* @section RVCT_ARMCMx_CONF_1 ARMv6-M specific options
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* The following options are specific for the ARMv6-M architecture:
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* - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV
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* exception instead of NMI as preemption handler.
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* .
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* @section RVCT_ARMCMx_CONF_2 ARMv7-M specific options
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* The following options are specific for the ARMv6-M architecture:
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* - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
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* - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel
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* mode.
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* .
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* @ingroup RVCT_ARMCMx
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*/
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Optimized the driver for single block read and write operations.
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- NEW: Finished the reorganization of the Cortex-Mx ports, now also the
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IAR and RVCT ports support the new Compact mode.
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- NEW: Added to the ARMv6-M sub-port an option to use the PendSV exception
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instead of NMI for preemption (backported to 2.2.5).
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*** 2.3.3 ***
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- FIX: Fixed race condition in output queues (bug 3303908)(backported
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@ -86,12 +88,12 @@
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- FIX: Fixed timeout problem in the lwIP interface layer (bug 3302420)
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(backported to 2.2.4).
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- NEW: Reorganization of the Cortex-Mx ports in order to reduced code and
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comments duplication in the various headers.
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comments duplication in the various headers (backported to 2.2.5).
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- NEW: Improved the ARMv7-M sub-port now there are two modes: Compact and
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Advanced.
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The advanced mode is equivalent to the previous versions, the compact mode
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is new and makes the kernel *much* smaller and generally faster but does
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not support fast interrupts, see the reports for details.
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not support fast interrupts (backported to 2.2.5).
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- NEW: Now the port layer exports info regarding the compiler and the port
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options. The info are printed into the test reports.
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- CHANGE: Renamed the macros IDLE_THREAD_STACK_SIZE and INT_REQUIRED_STACK
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Loading…
Reference in New Issue