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STM32 HAL improvements (CL devices). 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2820 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
gdisirio 2011-03-12 11:19:24 +00:00
parent 3ed4800b9b
commit 887409c0c9
4 changed files with 144 additions and 45 deletions
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6
demos/ARMCM3-STM32F107/mcuconf.h
View File

@ -34,6 +34,9 @@
/*
* HAL driver system settings.
*/
#define STM32_ACTIVATE_PLL1 TRUE
#define STM32_ACTIVATE_PLL2 TRUE
#define STM32_ACTIVATE_PLL3 TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_PREDIV1
#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2
@ -41,12 +44,13 @@
#define STM32_PLLMUL_VALUE 9
#define STM32_PREDIV2_VALUE 5
#define STM32_PLL2MUL_VALUE 8
#define STM32_PLL3MUL_VALUE 10
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3
#define STM32_MCO STM32_MCO_NOCLOCK
#define STM32_MCO STM32_MCO_PLL3
/*
* ADC driver system settings.

50
os/hal/platforms/STM32/hal_lld.c
View File

@ -146,43 +146,51 @@ void stm32_clock_init(void) {
*/
void stm32_clock_init(void) {
/* HSI setup, it enforces the reset situation in order to handle possible
problems with JTAG probes and re-initializations.*/
/* HSI setup.*/
RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
while (!(RCC->CR & RCC_CR_HSIRDY))
; /* Wait until HSI is stable. */
RCC->CFGR = 0;
RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
RCC->CFGR = 0; /* CFGR reset value. */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
; /* Wait until HSI is the source.*/
RCC->CFGR2 = 0;
/* HSE setup, it is only performed if the HSE clock is selected as source
of the system clock (directly or through the PLLs).*/
#if (STM32_SW == STM32_SW_HSE) || \
((STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_PREDIV1))
/* HSE setup, it is only performed if the current configuration uses
it somehow.*/
#if STM32_ACTIVATE_PLL2 || \
STM32_ACTIVATE_PLL3 || \
(STM32_SW == STM32_SW_HSE) || \
((STM32_PREDIV1SRC == STM32_PREDIV1SRC_HSE) && \
(STM32_PLLSRC == STM32_PLLSRC_PREDIV1))
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY))
; /* Waits until HSE is stable. */
#endif
/* PLL2 setup, it is only performed if the PLL2 clock is selected as source
for the PLL clock else it is left disabled.*/
#if STM32_SW == STM32_SW_PLL
#if STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2
RCC->CFGR2 |= STM32_PREDIV2 | STM32_PLL2MUL;
RCC->CR |= RCC_CR_PLL2ON;
/* Settings of various dividers and multipliers in CFGR2.*/
RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 |
STM32_PREDIV1 | STM32_PREDIV1SRC;
/* PLL2 setup, if activated.*/
#if STM32_ACTIVATE_PLL2
RCC->CR |= RCC_CR_PLL2ON;
while (!(RCC->CR & RCC_CR_PLL2RDY))
; /* Waits until PLL is stable. */
; /* Waits until PLL2 is stable. */
#endif
/* PLL setup, it is only performed if the PLL is the selected source of
the system clock else it is left disabled.*/
RCC->CFGR2 |= STM32_PREDIV1 | STM32_PREDIV1SRC;
RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC;
RCC->CR |= RCC_CR_PLLON;
/* PLL3 setup, if activated.*/
#if STM32_ACTIVATE_PLL3
RCC->CR |= RCC_CR_PLL3ON;
while (!(RCC->CR & RCC_CR_PLL3RDY))
; /* Waits until PLL3 is stable. */
#endif
/* PLL1 setup, if activated.*/
#if STM32_ACTIVATE_PLL1
RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC;
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL2 is stable. */
; /* Waits until PLL1 is stable. */
#endif
/* Clock settings.*/

131
os/hal/platforms/STM32/hal_lld_f105_f107.h
View File

@ -170,10 +170,35 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @brief PLL1 main switch.
* @note If this constant is set to @p TRUE then the PLL1 is initialized
* and started.
*/
#if !defined(STM32_ACTIVATE_PLL1) || defined(__DOXYGEN__)
#define STM32_ACTIVATE_PLL1 TRUE
#endif
/**
* @brief PLL2 main switch.
* @note If this constant is set to @p TRUE then the PLL2 is initialized
* and started.
*/
#if !defined(STM32_ACTIVATE_PLL2) || defined(__DOXYGEN__)
#define STM32_ACTIVATE_PLL2 TRUE
#endif
/**
* @brief PLL3 main switch.
* @note If this constant is set to @p TRUE then the PLL3 is initialized
* and started.
*/
#if !defined(STM32_ACTIVATE_PLL3) || defined(__DOXYGEN__)
#define STM32_ACTIVATE_PLL3 TRUE
#endif
/**
* @brief Main clock source selection.
* @note If the selected clock source is not the PLL then the PLL is not
* initialized and started.
* @note The default value is calculated for a 72MHz system clock from
* a 25MHz crystal using both PLL and PLL2.
*/
@ -183,8 +208,6 @@
/**
* @brief Clock source for the PLL.
* @note This setting has only effect if the PLL is selected as the
* system clock source.
* @note The default value is calculated for a 72MHz system clock from
* a 25MHz crystal using both PLL and PLL2.
*/
@ -194,8 +217,6 @@
/**
* @brief PREDIV1 clock source.
* @note This setting has only effect if the PLL is selected as the
* system clock source.
* @note The default value is calculated for a 72MHz system clock from
* a 25MHz crystal using both PLL and PLL2.
*/
@ -205,8 +226,6 @@
/**
* @brief PREDIV1 division factor.
* @note This setting has only effect if the PLL is selected as the
* system clock source.
* @note The allowed range is 1...16.
* @note The default value is calculated for a 72MHz system clock from
* a 25MHz crystal using both PLL and PLL2.
@ -227,8 +246,6 @@
/**
* @brief PREDIV2 division factor.
* @note This setting has only effect if the PLL2 is selected as the
* clock source for the PLL.
* @note The allowed range is 1...16.
* @note The default value is calculated for a 72MHz system clock from
* a 25MHz crystal using both PLL and PLL2.
@ -246,6 +263,15 @@
#define STM32_PLL2MUL_VALUE 8
#endif
/**
* @brief PLL3 multiplier value.
* @note The default value is calculated for a 50MHz clock from
* a 25MHz crystal.
*/
#if !defined(STM32_PLL3MUL_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL3MUL_VALUE 10
#endif
/**
* @brief AHB prescaler value.
* @note The default value is calculated for a 72MHz system clock from
@ -294,6 +320,14 @@
/* Derived constants and error checks. */
/*===========================================================================*/
/* PLL2 usage check.*/
#if STM32_ACTIVATE_PLL2 && \
(STM32_PREDIV1SRC != STM32_PREDIV1SRC_PLL2) && \
(STM32_MCO != STM32_MCO_PLL2)
#error "PLL2 activated but not used"
#endif
/**
* @brief PREDIV1 field.
*/
@ -338,9 +372,22 @@
#error "invalid STM32_PLL2MUL_VALUE value specified"
#endif
/* The following values are only used if PLL2 clock is selected as source
for the PLL clock */
#if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) || defined(__DOXYGEN__)
/**
* @brief PLL3MUL field.
*/
#if ((STM32_PLL3MUL_VALUE >= 8) && (STM32_PLL3MUL_VALUE <= 14)) || \
defined(__DOXYGEN__)
#define STM32_PLL3MUL ((STM32_PLL3MUL_VALUE - 2) << 12)
#elif (STM32_PLL3MUL_VALUE == 16)
#define STM32_PLL3MUL (14 << 12)
#elif (STM32_PLL3MUL_VALUE == 20)
#define STM32_PLL3MUL (15 << 12)
#else
#error "invalid STM32_PLL3MUL_VALUE value specified"
#endif
/* The following values are only used if PLL2 is activated */
#if STM32_ACTIVATE_PLL2
/**
* @brief PLL2 input frequency.
*/
@ -356,11 +403,44 @@
*/
#define STM32_PLL2CLKOUT (STM32_PLL2CLKIN * STM32_PLL2MUL_VALUE)
/**
* @brief PLL2 VCO clock frequency.
*/
#define STM32_PLL2VCO (STM32_PLL2CLKOUT * 2)
/* PLL2 output frequency range check.*/
#if (STM32_PLL2CLKOUT < 40000000) || (STM32_PLL2CLKOUT > 74000000)
#error "STM32_PLL2CLKOUT outside acceptable range (40...74MHz)"
#if (STM32_PLL2VCO < 80000000) || (STM32_PLL2VCO > 148000000)
#error "STM32_PLL2VCO outside acceptable range (80...148MHz)"
#endif
#endif /* STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2 */
#endif /* STM32_ACTIVATE_PLL2 */
/* The following values are only used if PLL3 is activated */
#if STM32_ACTIVATE_PLL3
/**
* @brief PLL3 input frequency.
*/
#define STM32_PLL3CLKIN (STM32_HSECLK / STM32_PREDIV2_VALUE)
/* PLL3 input frequency range check.*/
#if (STM32_PLL3CLKIN < 3000000) || (STM32_PLL3CLKIN > 5000000)
#error "STM32_PLL3CLKIN outside acceptable range (3...5MHz)"
#endif
/**
* @brief PLL3 output clock frequency.
*/
#define STM32_PLL3CLKOUT (STM32_PLL3CLKIN * STM32_PLL3MUL_VALUE)
/**
* @brief PLL3 VCO clock frequency.
*/
#define STM32_PLL3VCO (STM32_PLL3CLKOUT * 2)
/* PLL3 output frequency range check.*/
#if (STM32_PLL3VCO < 80000000) || (STM32_PLL3VCO > 148000000)
#error "STM32_PLL3CLKOUT outside acceptable range (80...148MHz)"
#endif
#endif /* STM32_ACTIVATE_PLL3 */
/**
* @brief PREDIV1 input frequency.
@ -377,9 +457,9 @@
* @brief PLL input clock frequency.
*/
#if (STM32_PLLSRC == STM32_PLLSRC_PREDIV1) || defined(__DOXYGEN__)
#define STM32_PLLCLKIN (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE)
#define STM32_PLLCLKIN (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE)
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
#define STM32_PLLCLKIN (STM32_HSICLK / 2)
#define STM32_PLLCLKIN (STM32_HSICLK / 2)
#else
#error "invalid STM32_PLLSRC value specified"
#endif
@ -392,11 +472,16 @@
/**
* @brief PLL output clock frequency.
*/
#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
/**
* @brief PLL VCO clock frequency.
*/
#define STM32_PLLVCO (STM32_PLLCLKOUT * 2)
/* PLL output frequency range check.*/
#if (STM32_PLLCLKOUT < 18000000) || (STM32_PLLCLKOUT > 72000000)
#error "STM32_PLLCLKOUT outside acceptable range (18...72MHz)"
#if (STM32_PLLVCO < 36000000) || (STM32_PLLVCO > 144000000)
#error "STM32_PLLVCO outside acceptable range (36...144MHz)"
#endif
/**
@ -515,9 +600,9 @@
* @brief OTG frequency.
*/
#if (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV3) || defined(__DOXYGEN__)
#define STM32_OTGFSCLK ((STM32_PLLCLKOUT * 2) / 3)
#define STM32_OTGFSCLK (STM32_PLLVCO / 3)
#elif (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV2)
#define STM32_OTGFSCLK STM32_PLLCLKOUT
#define STM32_OTGFSCLK (STM32_PLLVCO / 2)
#else
#error "invalid STM32_OTGFSPRE value specified"
#endif

2
readme.txt
View File

@ -73,6 +73,8 @@
*** 2.3.1 ***
- FIX: Fixed invalid assertion in adcConvert() (bug 3205410)(backported
to 2.2.3).
- NEW: Added support for PLL3 in STM32 HAL driver. Note, the format of the
mcuconf.h file is changed for STM32F105/STM32F107 devices.
- NEW: Added board files for the Olimex STM32-P107.
- NEW: Improved setup packets handling in the USB driver through a specific
callback.