Feature request #28 merged.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5914 35acf78f-673a-0410-8e92-d51de3d6d3f4master
barthess
parent
1e412cad0d
commit
7fadc40371
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@ -55,6 +55,22 @@
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STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \
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STM32_USART3_TX_DMA_CHN)
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#define UART4_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_UART4_RX_DMA_STREAM, \
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STM32_UART4_RX_DMA_CHN)
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#define USART4_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART4_TX_DMA_STREAM, \
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STM32_UART4_TX_DMA_CHN)
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#define UART5_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_UART5_RX_DMA_STREAM, \
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STM32_UART5_RX_DMA_CHN)
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#define USART5_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART5_TX_DMA_STREAM, \
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STM32_UART5_TX_DMA_CHN)
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#define USART6_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART6_RX_DMA_STREAM, \
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STM32_USART6_RX_DMA_CHN)
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@ -63,6 +79,14 @@
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STM32_DMA_GETCHANNEL(STM32_UART_USART6_TX_DMA_STREAM, \
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STM32_USART6_TX_DMA_CHN)
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#if (STM32_UART_USE_UART4 || STM32_UART_USE_UART5)
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#define STM32_UART45_CR2_CHECK_MASK (USART_CR2_STOP_0 | USART_CR2_CLKEN | \
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USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL)
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#define STM32_UART45_CR3_CHECK_MASK (USART_CR3_CTSIE | USART_CR3_CTSE | \
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USART_CR3_RTSE | USART_CR3_SCEN | USART_CR3_NACK)
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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@ -82,6 +106,15 @@ UARTDriver UARTD2;
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UARTDriver UARTD3;
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#endif
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/** @brief UART4 UART driver identifier.*/
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#if STM32_UART_USE_UART4 || defined(__DOXYGEN__)
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UARTDriver UARTD4;
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#endif
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/** @brief UART5 UART driver identifier.*/
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#if STM32_UART_USE_UART5 || defined(__DOXYGEN__)
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UARTDriver UARTD5;
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#endif
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/** @brief USART6 UART driver identifier.*/
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#if STM32_UART_USE_USART6 || defined(__DOXYGEN__)
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@ -358,6 +391,44 @@ CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
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}
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#endif /* STM32_UART_USE_USART3 */
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#if STM32_UART_USE_UART4 || defined(__DOXYGEN__)
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#if !defined(STM32_UART4_HANDLER)
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#error "STM32_USART4_HANDLER not defined"
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#endif
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/**
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* @brief UART4 IRQ handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(STM32_UART4_HANDLER) {
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CH_IRQ_PROLOGUE();
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serve_usart_irq(&UARTD4);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_UART_USE_UART4 */
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#if STM32_UART_USE_UART5 || defined(__DOXYGEN__)
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#if !defined(STM32_UART5_HANDLER)
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#error "STM32_USART5_HANDLER not defined"
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#endif
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/**
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* @brief UART5 IRQ handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(STM32_UART5_HANDLER) {
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CH_IRQ_PROLOGUE();
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serve_usart_irq(&UARTD5);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_UART_USE_UART5 */
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#if STM32_UART_USE_USART6 || defined(__DOXYGEN__)
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#if !defined(STM32_USART6_HANDLER)
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#error "STM32_USART6_HANDLER not defined"
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@ -412,6 +483,22 @@ void uart_lld_init(void) {
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UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
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#endif
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#if STM32_UART_USE_UART4
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uartObjectInit(&UARTD4);
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UARTD4.usart = UART4;
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UARTD4.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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UARTD4.dmarx = STM32_DMA_STREAM(STM32_UART_UART4_RX_DMA_STREAM);
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UARTD4.dmatx = STM32_DMA_STREAM(STM32_UART_UART4_TX_DMA_STREAM);
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#endif
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#if STM32_UART_USE_UART5
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uartObjectInit(&UARTD5);
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UARTD5.usart = UART5;
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UARTD5.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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UARTD5.dmarx = STM32_DMA_STREAM(STM32_UART_UART5_RX_DMA_STREAM);
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UARTD5.dmatx = STM32_DMA_STREAM(STM32_UART_UART5_TX_DMA_STREAM);
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#endif
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#if STM32_UART_USE_USART6
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uartObjectInit(&UARTD6);
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UARTD6.usart = USART6;
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@ -420,6 +507,28 @@ void uart_lld_init(void) {
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#endif
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}
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/**
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* @brief Check CR2 and CR3 values for compatibility with UART4, UART5.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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*
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* @notapi
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*/
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#if (STM32_UART_USE_UART4 || STM32_UART_USE_UART5)
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static void uart_check_config(const UARTDriver *uartp) {
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uint16_t cr;
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cr = uartp->config->cr2;
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chDbgCheck((cr & STM32_UART45_CR2_CHECK_MASK) == 0,
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"Some flags from CR2 unavailable for this UART");
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cr = uartp->config->cr3;
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chDbgCheck((cr & STM32_UART45_CR3_CHECK_MASK) == 0,
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"Some flags from CR3 unavailable for this UART");
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}
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#endif /* (STM32_UART_USE_USART4 || STM32_UART_USE_USART5) */
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/**
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* @brief Configures and activates the UART peripheral.
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*
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@ -429,6 +538,14 @@ void uart_lld_init(void) {
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*/
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void uart_lld_start(UARTDriver *uartp) {
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#if STM32_UART_USE_UART4
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if (uartp == &UARTD4)
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uart_check_config(uartp);
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#elif STM32_UART_USE_UART5
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else if (uartp == &UARTD5)
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uart_check_config(uartp);
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#endif
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if (uartp->state == UART_STOP) {
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#if STM32_UART_USE_USART1
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if (&UARTD1 == uartp) {
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@ -493,6 +610,48 @@ void uart_lld_start(UARTDriver *uartp) {
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}
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#endif
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#if STM32_UART_USE_UART4
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if (&UARTD4 == uartp) {
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bool_t b;
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b = dmaStreamAllocate(uartp->dmarx,
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STM32_UART_UART4_IRQ_PRIORITY,
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(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #7", "stream already allocated");
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b = dmaStreamAllocate(uartp->dmatx,
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STM32_UART_UART4_IRQ_PRIORITY,
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(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #8", "stream already allocated");
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rccEnableUART4(FALSE);
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nvicEnableVector(STM32_UART4_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_UART_UART4_IRQ_PRIORITY));
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uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY);
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}
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#endif
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#if STM32_UART_USE_UART5
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if (&UARTD5 == uartp) {
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bool_t b;
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b = dmaStreamAllocate(uartp->dmarx,
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STM32_UART_UART5_IRQ_PRIORITY,
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(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #9", "stream already allocated");
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b = dmaStreamAllocate(uartp->dmatx,
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STM32_UART_UART5_IRQ_PRIORITY,
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(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #10", "stream already allocated");
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rccEnableUART5(FALSE);
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nvicEnableVector(STM32_UART5_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_UART_UART5_IRQ_PRIORITY));
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uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY);
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}
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#endif
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#if STM32_UART_USE_USART6
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if (&UARTD6 == uartp) {
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bool_t b;
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@ -500,12 +659,12 @@ void uart_lld_start(UARTDriver *uartp) {
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STM32_UART_USART6_IRQ_PRIORITY,
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(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated");
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chDbgAssert(!b, "uart_lld_start(), #11", "stream already allocated");
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b = dmaStreamAllocate(uartp->dmatx,
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STM32_UART_USART6_IRQ_PRIORITY,
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(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
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chDbgAssert(!b, "uart_lld_start(), #12", "stream already allocated");
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rccEnableUSART6(FALSE);
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nvicEnableVector(STM32_USART6_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_UART_USART6_IRQ_PRIORITY));
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@ -566,6 +725,22 @@ void uart_lld_stop(UARTDriver *uartp) {
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}
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#endif
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#if STM32_UART_USE_UART4
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if (&UARTD4 == uartp) {
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nvicDisableVector(STM32_UART4_NUMBER);
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rccDisableUART4(FALSE);
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return;
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}
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#endif
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#if STM32_UART_USE_UART5
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if (&UARTD5 == uartp) {
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nvicDisableVector(STM32_UART5_NUMBER);
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rccDisableUART5(FALSE);
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return;
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}
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#endif
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#if STM32_UART_USE_USART6
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if (&UARTD6 == uartp) {
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nvicDisableVector(STM32_USART6_NUMBER);
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@ -66,6 +66,24 @@
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#define STM32_UART_USE_USART3 FALSE
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#endif
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/**
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* @brief UART driver on UART4 enable switch.
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* @details If set to @p TRUE the support for UART4 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_UART_USE_UART4) || defined(__DOXYGEN__)
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#define STM32_UART_USE_UART4 FALSE
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#endif
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/**
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* @brief UART driver on UART5 enable switch.
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* @details If set to @p TRUE the support for UART5 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_UART_USE_UART4) || defined(__DOXYGEN__)
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#define STM32_UART_USE_UART5 FALSE
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#endif
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/**
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* @brief UART driver on USART6 enable switch.
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* @details If set to @p TRUE the support for USART6 is included.
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@ -96,6 +114,20 @@
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#endif
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/**
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* @brief UART4 interrupt priority level setting.
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*/
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#if !defined(STM32_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_UART_UART4_IRQ_PRIORITY 12
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#endif
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/**
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* @brief UART5 interrupt priority level setting.
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*/
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#if !defined(STM32_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_UART_UART5_IRQ_PRIORITY 12
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#endif
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/**
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* @brief USART6 interrupt priority level setting.
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*/
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@ -133,6 +165,26 @@
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#endif
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/**
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* @brief UART4 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA channels but
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* because of the channels ordering the RX channel has always priority
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* over the TX channel.
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*/
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#if !defined(STM32_UART_UART4_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_UART_UART4_DMA_PRIORITY 0
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#endif
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/**
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* @brief UART5 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA channels but
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* because of the channels ordering the RX channel has always priority
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* over the TX channel.
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*/
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#if !defined(STM32_UART_UART5_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_UART_UART5_DMA_PRIORITY 0
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#endif
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/**
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* @brief USART6 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA channels but
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@ -144,7 +196,7 @@
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#endif
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/**
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* @brief USART1 DMA error hook.
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* @brief USART DMA error hook.
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* @note The default action for DMA errors is a system halt because DMA
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* error can only happen because programming errors.
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*/
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@ -202,6 +254,38 @@
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#endif
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/**
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* @brief DMA stream used for UART4 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_UART_UART4_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#endif
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/**
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* @brief DMA stream used for UART4 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_UART_UART4_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#endif
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/**
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* @brief DMA stream used for UART5 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_UART_UART5_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#endif
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/**
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* @brief DMA stream used for UART5 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_UART_UART5_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#endif
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/**
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* @brief DMA stream used for USART6 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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@ -228,6 +312,8 @@
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#endif /* !STM32_ADVANCED_DMA*/
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/** @} */
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@ -248,12 +334,33 @@
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#error "USART3 not present in the selected device"
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#endif
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#if STM32_UART_USE_UART4
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#if !STM32_HAS_UART4
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#error "UART4 not present in the selected device"
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#endif
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#if !defined(STM32F4XX) || !defined(STM32F4XX)
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#error "UART4 DMA access not supported in this platform"
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#endif
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#endif
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#if STM32_UART_USE_UART5
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#if !STM32_HAS_UART5
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#error "UART5 not present in the selected device"
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#endif
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#if !defined(STM32F4XX) || !defined(STM32F4XX)
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#error "UART5 DMA access not supported in this platform"
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#endif
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#endif
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#if STM32_UART_USE_USART6 && !STM32_HAS_USART6
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#error "USART6 not present in the selected device"
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#endif
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#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \
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!STM32_UART_USE_USART3 && !STM32_UART_USE_USART6
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!STM32_UART_USE_USART3 && !STM32_UART_USE_UART4 && \
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!STM32_UART_USE_UART5 && !STM32_UART_USE_USART6
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#error "UART driver activated but no USART/UART peripheral assigned"
|
||||
#endif
|
||||
|
||||
|
|
@ -272,6 +379,16 @@
|
|||
#error "Invalid IRQ priority assigned to USART3"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_UART4 && \
|
||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_UART4_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to UART4"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_UART5 && \
|
||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_UART5_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to UART5"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART6 && \
|
||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART6_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to USART6"
|
||||
|
|
@ -292,6 +409,16 @@
|
|||
#error "Invalid DMA priority assigned to USART3"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_UART4 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART4_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to UART4"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_UART5 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART5_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to UART5"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART6 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART6_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to USART6"
|
||||
|
|
@ -333,6 +460,30 @@
|
|||
#error "invalid DMA stream associated to USART3 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_UART4 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_UART_UART4_RX_DMA_STREAM, \
|
||||
STM32_UART4_RX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to UART4 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_UART4 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_UART_UART4_TX_DMA_STREAM, \
|
||||
STM32_UART4_TX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to UART4 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_UART5 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_UART_UART5_RX_DMA_STREAM, \
|
||||
STM32_UART5_RX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to UART5 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_UART5 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_UART_UART5_TX_DMA_STREAM, \
|
||||
STM32_UART5_TX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to UART5 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART6 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_UART_USART6_RX_DMA_STREAM, \
|
||||
STM32_USART6_RX_DMA_MSK)
|
||||
|
|
@ -496,6 +647,14 @@ extern UARTDriver UARTD2;
|
|||
extern UARTDriver UARTD3;
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_UART4 && !defined(__DOXYGEN__)
|
||||
extern UARTDriver UARTD4;
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_UART5 && !defined(__DOXYGEN__)
|
||||
extern UARTDriver UARTD5;
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART6 && !defined(__DOXYGEN__)
|
||||
extern UARTDriver UARTD6;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -89,6 +89,8 @@
|
|||
*****************************************************************************
|
||||
|
||||
*** 2.7.0 ***
|
||||
- NEW: Added support of UART4 and UART5 (STM32F4x and STM32F2x platforms).
|
||||
Feature request #28.
|
||||
- FIX: Fixed missing casts in time-conversion macros (bug #418)(backported
|
||||
to 2.6.1, 2.4.4 and 2.2.10).
|
||||
- FIX: Fixed STM32 Serial (v2) driver invalid CR registers size (bug #416)
|
||||
|
|
|
|||
Loading…
Reference in New Issue