git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5644 35acf78f-673a-0410-8e92-d51de3d6d3f4
parent
9bbb4ac554
commit
7f4de1c13e
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@ -6,7 +6,7 @@ Settings: SYSCLK=120
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*** ChibiOS/RT test suite
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***
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*** Kernel: 2.5.2unstable
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*** Compiled: Apr 29 2013 - 09:53:43
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*** Compiled: Apr 29 2013 - 11:20:37
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*** Compiler: GCC 4.6.3 build on 2013-01-07
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*** Architecture: Power Architecture
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*** Core Variant: e200z4
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@ -100,7 +100,7 @@ Settings: SYSCLK=120
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.1 (Benchmark, messages #1)
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--- Score : 379276 msgs/S, 758552 ctxswc/S
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--- Score : 379277 msgs/S, 758554 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.2 (Benchmark, messages #2)
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@ -108,7 +108,7 @@ Settings: SYSCLK=120
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.3 (Benchmark, messages #3)
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--- Score : 312930 msgs/S, 625860 ctxswc/S
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--- Score : 312931 msgs/S, 625862 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.4 (Benchmark, context switch)
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@ -120,7 +120,7 @@ Settings: SYSCLK=120
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.6 (Benchmark, threads, create only)
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--- Score : 369919 threads/S
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--- Score : 369918 threads/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
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@ -136,11 +136,11 @@ Settings: SYSCLK=120
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.10 (Benchmark, virtual timers set/reset)
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--- Score : 1309916 timers/S
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--- Score : 1309908 timers/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.11 (Benchmark, semaphores wait/signal)
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--- Score : 1762552 wait+signal/S
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--- Score : 1762548 wait+signal/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
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@ -208,7 +208,7 @@ _ramcode:
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.type _coreinit, @function
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_coreinit:
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/*
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* Invalidating all TLBs except one.
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* Invalidating all TLBs except TLB1.
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*/
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lis %r3, 0
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mtspr 625, %r3 /* MAS1 */
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@ -127,7 +127,7 @@
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#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
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#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_128K)
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#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE | MAS2_I)
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#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
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#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \
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MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
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MAS3_UR | MAS3_SR)
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@ -213,6 +213,59 @@ _ramcode:
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.globl _coreinit
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.type _coreinit, @function
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_coreinit:
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/*
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* Invalidating all TLBs except TLB0.
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*/
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lis %r3, 0
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mtspr 625, %r3 /* MAS1 */
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mtspr 626, %r3 /* MAS2 */
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mtspr 627, %r3 /* MAS3 */
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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/*
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* TLB1 allocated to internal RAM.
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*/
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@ -293,44 +346,6 @@ _coreinit:
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mtspr 627, %r3 /* MAS3 */
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tlbwe
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/*
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* Invalidating the remaining TLBs (because debuggers).
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*/
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lis %r3, 0
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mtspr 625, %r3 /* MAS1 */
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mtspr 626, %r3 /* MAS2 */
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mtspr 627, %r3 /* MAS3 */
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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/*
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* RAM clearing, this device requires a write to all RAM location in
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* order to initialize the ECC detection hardware, this is going to
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