git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2352 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
parent
8f4e3df95a
commit
7e5398c9b8
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@ -21,148 +21,95 @@
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#define _BOARD_H_
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/*
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* Setup for STMicroelectronics STM8L-Discovery board.
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* Setup for STMicroelectronics STM8S-Discovery board.
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*/
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/*
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* Board identifiers.
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*/
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#define BOARD_ST_STM8L_DISCOVERY
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#define BOARD_NAME "ST STM8L-Discovery"
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#define BOARD_ST_STM8S_DISCOVERY
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#define BOARD_NAME "ST STM8S-Discovery"
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/*
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* Board frequencies and bypass modes.
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*
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* The bypass must be set to TRUE if the chip is driven by an external
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* oscillator rather than a crystal. Frequency must be set to zero if
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* the clock source is not used at all.
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* The following constants are used by the HAL low level driver for
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* correct clock initialization.
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* Board frequencies.
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*/
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#define HSECLK 0
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#define HSEBYPASS FALSE
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#define LSECLK 32768
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#define LSEBYPASS FALSE
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#define HSECLK 16000000
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/*
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* MCU model used on the board.
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*/
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#define STM8L152C6
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#define STM8L15X_MD
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#define STM8S105
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/*
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* Pin definitions.
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*/
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#define PA_OSC_IN 2
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#define PA_OSC_OUT 3
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#define PA_LCD_COM0 4
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#define PA_LCD_COM1 5
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#define PA_LCD_COM2 6
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#define PA_LCD_SEG0 7
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#define PA_OSCIN 1
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#define PA_OSCOUT 2
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#define PB_LCD_SEG10 0
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#define PB_LCD_SEG11 1
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#define PB_LCD_SEG12 2
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#define PB_LCD_SEG13 3
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#define PB_LCD_SEG14 4
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#define PB_LCD_SEG15 5
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#define PB_LCD_SEG16 6
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#define PB_LCD_SEG17 7
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#define PC_TS_KEY 1
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#define PC_TS_LOADREF 2
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#define PC_TS_SHIELD 3
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#define PC_UNUSED 0
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#define PC_BUTTON 1
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#define PC_LCD_SEG22 2
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#define PC_LCD_SEG23 3
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#define PC_IDD_CNT_EN 4
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#define PC_LED4 7
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#define PD_LCD_SEG7 0
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#define PD_LCD_COM3 1
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#define PD_LCD_SEG8 2
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#define PD_LCD_SEG9 3
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#define PD_LCD_SEG18 4
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#define PD_LCD_SEG19 5
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#define PD_LCD_SEG20 6
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#define PD_LCD_SEG21 7
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#define PE_LCD_SEG1 0
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#define PE_LCD_SEG2 1
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#define PE_LCD_SEG3 2
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#define PE_LCD_SEG4 3
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#define PE_LCD_SEG5 4
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#define PE_LCD_SEG6 5
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#define PE_IDD_WAKEUP 6
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#define PE_LED3 7
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#define PF0_IDD_MEASUREMENT 0
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#define PD_LD10 0
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#define PD_SWIM 1
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#define PD_TX 5
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#define PD_RX 6
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/*
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* Port A initial setup.
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*/
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#define VAL_GPIOAODR 0
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#define VAL_GPIOADDR 0 /* All inputs. */
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#define VAL_GPIOACR1 0xFF /* All pull-up. */
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#define VAL_GPIOACR2 0
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#define VAL_GPIOAODR 0
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#define VAL_GPIOADDR 0 /* All inputs. */
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#define VAL_GPIOACR1 0xFF /* All pull-up or push-pull. */
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#define VAL_GPIOACR2 0
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/*
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* Port B initial setup.
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*/
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#define VAL_GPIOBODR 0
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#define VAL_GPIOBDDR 0 /* All inputs. */
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#define VAL_GPIOBCR1 0xFF /* All pull-up. */
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#define VAL_GPIOBCR2 0
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#define VAL_GPIOBODR 0
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#define VAL_GPIOBDDR 0 /* All inputs. */
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#define VAL_GPIOBCR1 0xFF /* All push-pull. */
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#define VAL_GPIOBCR2 0
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/*
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* Port C initial setup.
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*/
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#define VAL_GPIOCODR (1 < PC_LED4)
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#define VAL_GPIOCDDR (1 < PC_LED4)
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#define VAL_GPIOCCR1 0xFF /* All pull-up/open drain. */
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#define VAL_GPIOCCR2 0
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#define VAL_GPIOCODR 0
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#define VAL_GPIOCDDR 0 /* All inputs. */
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#define VAL_GPIOCCR1 0xFF /* All pull-up. */
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#define VAL_GPIOCCR2 0
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/*
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* Port D initial setup.
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*/
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#define VAL_GPIODODR 0
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#define VAL_GPIODDDR 0 /* All inputs. */
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#define VAL_GPIODCR1 0xFF /* All pull-up. */
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#define VAL_GPIODCR2 0
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#define VAL_GPIODODR (1 << PD_LD10) | (1 << PD_TX)
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#define VAL_GPIODDDR (1 << PD_LD10) | (1 << PD_TX)
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#define VAL_GPIODCR1 0xFF /* All pull-up. */
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#define VAL_GPIODCR2 0
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/*
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* Port E initial setup.
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*/
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#define VAL_GPIOEODR (1 < PE_LED3)
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#define VAL_GPIOEDDR (1 < PE_LED3)
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#define VAL_GPIOECR1 0xFF /* All pull-up/open drain. */
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#define VAL_GPIOECR2 0
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#define VAL_GPIOEODR 0
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#define VAL_GPIOEDDR 0 /* All inputs. */
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#define VAL_GPIOECR1 0xFF /* All pull-up. */
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#define VAL_GPIOECR2 0
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/*
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* Port F initial setup.
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*/
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#define VAL_GPIOFODR 0
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#define VAL_GPIOFDDR 0 /* All inputs. */
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#define VAL_GPIOFCR1 0xFF /* All pull-up. */
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#define VAL_GPIOFCR2 0
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#define VAL_GPIOFODR 0
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#define VAL_GPIOFDDR 0 /* All inputs. */
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#define VAL_GPIOFCR1 0xFF /* All pull-up. */
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#define VAL_GPIOFCR2 0
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/*
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* Port G initial setup (not present but still initialized).
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* Port G initial setup.
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*/
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#define VAL_GPIOGODR 0
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#define VAL_GPIOGDDR 0 /* All inputs. */
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#define VAL_GPIOGCR1 0xFF /* All pull-up. */
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#define VAL_GPIOGCR2 0
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/*
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* TIM2 interrupt handler segment.
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*/
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#define _TIM2_UPDATE_ISR() { \
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if ((TIM2->SR1 & TIM_SR1_UIF) != 0) { \
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chSysLockFromIsr(); \
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chSysTimerHandlerI(); \
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chSysUnlockFromIsr(); \
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TIM2->SR1 = 0; \
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} \
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}
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#define VAL_GPIOGODR 0
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#define VAL_GPIOGDDR 0 /* All inputs. */
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#define VAL_GPIOGCR1 0xFF /* All pull-up or push-pull. */
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#define VAL_GPIOGCR2 0
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#ifdef __cplusplus
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extern "C" {
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