Fixed wrong macro prefixes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3755 35acf78f-673a-0410-8e92-d51de3d6d3f4master
gdisirio
parent
c355f186d7
commit
7b14ebcc5f
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@ -1164,13 +1164,13 @@
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* @brief MCO1 divider clock.
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*/
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#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
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#define STM_MCO1DIVCLK STM32_HSICLK
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#define STM32_MCO1DIVCLK STM32_HSICLK
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#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
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#define STM_MCO1DIVCLK STM32_LSECLK
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#define STM32_MCO1DIVCLK STM32_LSECLK
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#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
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#define STM_MCO1DIVCLK STM32_HSECLK
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#define STM32_MCO1DIVCLK STM32_HSECLK
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#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
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#define STM_MCO1DIVCLK STM32_PLLCLKOUT
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#define STM32_MCO1DIVCLK STM32_PLLCLKOUT
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#else
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#error "invalid STM32_MCO1SEL value specified"
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#endif
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@ -1179,15 +1179,15 @@
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* @brief MCO1 output pin clock.
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*/
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#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
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#define STM_MCO1CLK STM_MCO1DIVCLK
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#define STM32_MCO1CLK STM32_MCO1DIVCLK
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#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
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#define STM_MCO1CLK (STM_MCO1DIVCLK / 2)
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#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
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#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
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#define STM_MCO1CLK (STM_MCO1DIVCLK / 3)
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#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
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#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
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#define STM_MCO1CLK (STM_MCO1DIVCLK / 4)
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#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
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#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
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#define STM_MCO1CLK (STM_MCO1DIVCLK / 5)
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#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
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#else
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#error "invalid STM32_MCO1PRE value specified"
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#endif
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@ -1196,13 +1196,13 @@
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* @brief MCO2 divider clock.
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*/
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#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
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#define STM_MCO2DIVCLK STM32_HSECLK
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#define STM32_MCO2DIVCLK STM32_HSECLK
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#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
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#define STM_MCO2DIVCLK STM32_PLLCLKOUT
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#define STM32_MCO2DIVCLK STM32_PLLCLKOUT
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#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
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#define STM_MCO2DIVCLK STM32_SYSCLK
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#define STM32_MCO2DIVCLK STM32_SYSCLK
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#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
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#define STM_MCO2DIVCLK STM32_PLLI2S
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#define STM32_MCO2DIVCLK STM32_PLLI2S
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#else
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#error "invalid STM32_MCO2SEL value specified"
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#endif
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@ -1211,15 +1211,15 @@
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* @brief MCO2 output pin clock.
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*/
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#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
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#define STM_MCO2CLK STM_MCO2DIVCLK
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#define STM32_MCO2CLK STM32_MCO2DIVCLK
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#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
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#define STM_MCO2CLK (STM_MCO2DIVCLK / 2)
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#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
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#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
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#define STM_MCO2CLK (STM_MCO2DIVCLK / 3)
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#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
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#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
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#define STM_MCO2CLK (STM_MCO2DIVCLK / 4)
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#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
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#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
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#define STM_MCO2CLK (STM_MCO2DIVCLK / 5)
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#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
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#else
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#error "invalid STM32_MCO2PRE value specified"
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#endif
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@ -1248,13 +1248,13 @@
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* @brief RTC clock.
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*/
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#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
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#define STM_RTCCLK 0
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#define STM32_RTCCLK 0
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#elif STM32_RTCSEL == STM32_RTCSEL_LSE
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#define STM_RTCCLK STM32_LSECLK
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#define STM32_RTCCLK STM32_LSECLK
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#elif STM32_RTCSEL == STM32_RTCSEL_LSI
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#define STM_RTCCLK STM32_LSICLK
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#define STM32_RTCCLK STM32_LSICLK
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#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
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#define STM_RTCCLK STM32_HSEDIVCLK
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#define STM32_RTCCLK STM32_HSEDIVCLK
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#else
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#error "invalid STM32_RTCSEL value specified"
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#endif
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@ -1184,13 +1184,13 @@
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* @brief MCO1 divider clock.
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*/
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#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
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#define STM_MCO1DIVCLK STM32_HSICLK
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#define STM32_MCO1DIVCLK STM32_HSICLK
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#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
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#define STM_MCO1DIVCLK STM32_LSECLK
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#define STM32_MCO1DIVCLK STM32_LSECLK
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#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
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#define STM_MCO1DIVCLK STM32_HSECLK
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#define STM32_MCO1DIVCLK STM32_HSECLK
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#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
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#define STM_MCO1DIVCLK STM32_PLLCLKOUT
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#define STM32_MCO1DIVCLK STM32_PLLCLKOUT
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#else
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#error "invalid STM32_MCO1SEL value specified"
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#endif
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@ -1199,15 +1199,15 @@
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* @brief MCO1 output pin clock.
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*/
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#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
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#define STM_MCO1CLK STM_MCO1DIVCLK
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#define STM32_MCO1CLK STM32_MCO1DIVCLK
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#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
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#define STM_MCO1CLK (STM_MCO1DIVCLK / 2)
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#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
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#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
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#define STM_MCO1CLK (STM_MCO1DIVCLK / 3)
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#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
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#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
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#define STM_MCO1CLK (STM_MCO1DIVCLK / 4)
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#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
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#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
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#define STM_MCO1CLK (STM_MCO1DIVCLK / 5)
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#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
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#else
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#error "invalid STM32_MCO1PRE value specified"
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#endif
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@ -1216,13 +1216,13 @@
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* @brief MCO2 divider clock.
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*/
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#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
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#define STM_MCO2DIVCLK STM32_HSECLK
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#define STM32_MCO2DIVCLK STM32_HSECLK
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#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
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#define STM_MCO2DIVCLK STM32_PLLCLKOUT
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#define STM32_MCO2DIVCLK STM32_PLLCLKOUT
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#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
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#define STM_MCO2DIVCLK STM32_SYSCLK
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#define STM32_MCO2DIVCLK STM32_SYSCLK
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#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
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#define STM_MCO2DIVCLK STM32_PLLI2S
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#define STM32_MCO2DIVCLK STM32_PLLI2S
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#else
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#error "invalid STM32_MCO2SEL value specified"
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#endif
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@ -1231,15 +1231,15 @@
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* @brief MCO2 output pin clock.
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*/
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#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
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#define STM_MCO2CLK STM_MCO2DIVCLK
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#define STM32_MCO2CLK STM32_MCO2DIVCLK
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#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
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#define STM_MCO2CLK (STM_MCO2DIVCLK / 2)
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#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
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#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
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#define STM_MCO2CLK (STM_MCO2DIVCLK / 3)
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#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
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#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
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#define STM_MCO2CLK (STM_MCO2DIVCLK / 4)
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#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
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#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
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#define STM_MCO2CLK (STM_MCO2DIVCLK / 5)
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#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
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#else
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#error "invalid STM32_MCO2PRE value specified"
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#endif
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@ -1268,13 +1268,13 @@
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* @brief RTC clock.
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*/
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#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
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#define STM_RTCCLK 0
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#define STM32_RTCCLK 0
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#elif STM32_RTCSEL == STM32_RTCSEL_LSE
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#define STM_RTCCLK STM32_LSECLK
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#define STM32_RTCCLK STM32_LSECLK
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#elif STM32_RTCSEL == STM32_RTCSEL_LSI
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#define STM_RTCCLK STM32_LSICLK
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#define STM32_RTCCLK STM32_LSICLK
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#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
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#define STM_RTCCLK STM32_HSEDIVCLK
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#define STM32_RTCCLK STM32_HSEDIVCLK
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#else
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#error "invalid STM32_RTCSEL value specified"
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#endif
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