git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5819 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
parent
f85a97a786
commit
7a3a252875
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@ -142,14 +142,22 @@ void spc_clock_init(void) {
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#endif /* SPC5_OSC_BYPASS */
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/* Setting the various dividers and source selectors.*/
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#if SPC5_HAS_AC0
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CGM.AC0DC.R = SPC5_CGM_AC0_DC0;
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CGM.AC0SC.R = SPC5_AUX0CLK_SRC;
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#endif
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#if SPC5_HAS_AC1
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CGM.AC1DC.R = SPC5_CGM_AC1_DC0;
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CGM.AC1SC.R = SPC5_AUX1CLK_SRC;
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#endif
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#if SPC5_HAS_AC2
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CGM.AC2DC.R = SPC5_CGM_AC2_DC0;
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CGM.AC2SC.R = SPC5_AUX2CLK_SRC;
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#endif
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#if SPC5_HAS_AC3
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CGM.AC3DC.R = SPC5_CGM_AC3_DC0;
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CGM.AC3SC.R = SPC5_AUX3CLK_SRC;
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#endif
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/* Enables the XOSC in order to check its functionality before proceeding
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with the initialization.*/
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@ -165,10 +173,12 @@ void spc_clock_init(void) {
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((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
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(SPC5_FMPLL0_NDIV_VALUE << 16);
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CGM.FMPLL[0].MR.R = 0; /* TODO: Add a setting. */
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#if SPC5_HAS_FMPLL1
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CGM.FMPLL[1].CR.R = SPC5_FMPLL1_ODF |
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((SPC5_FMPLL1_IDF_VALUE - 1) << 26) |
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(SPC5_FMPLL1_NDIV_VALUE << 16);
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CGM.FMPLL[1].MR.R = 0; /* TODO: Add a setting. */
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#endif
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/* Run modes initialization.*/
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ME.IS.R = 8; /* Resetting I_ICONF status.*/
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@ -281,8 +291,10 @@ uint32_t halSPCGetSystemClock(void) {
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return SPC5_XOSC_CLK;
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case SPC5_ME_GS_SYSCLK_FMPLL0:
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return SPC5_FMPLL0_CLK;
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#if SPC5_HAS_FMPLL1
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case SPC5_ME_GS_SYSCLK_FMPLL1:
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return SPC5_FMPLL1_CLK;
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#endif
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default:
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return 0;
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}
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@ -46,7 +46,11 @@
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* @name Platform identification
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* @{
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*/
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#if defined(_SPC560PXX_LARGE_) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "SPC56APxx Chassis and Safety"
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#else
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#define PLATFORM_NAME "SPC560Pxx Chassis and Safety"
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#endif
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/** @} */
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/**
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@ -90,11 +94,13 @@
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/**
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* @brief Maximum FMPLL1 output clock frequency.
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* @note FMPLL1 is not present on all devices.
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*/
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#define SPC5_FMPLL1_CLK_MAX 120000000
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/**
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* @brief Maximum FMPLL1 1D1 output clock frequency.
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* @note FMPLL1 is not present on all devices.
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*/
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#define SPC5_FMPLL1_1D1_CLK_MAX 80000000
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/** @} */
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@ -381,7 +387,6 @@
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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@ -402,7 +407,6 @@
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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@ -416,7 +420,6 @@
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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@ -430,7 +433,6 @@
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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@ -444,7 +446,6 @@
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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@ -458,7 +459,6 @@
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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@ -472,7 +472,6 @@
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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@ -486,7 +485,6 @@
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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@ -738,6 +736,7 @@
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#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
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#endif
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#if SPC5_HAS_FMPLL1
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/* Check on SPC5_FMPLL1_IDF_VALUE.*/
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#if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15)
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#error "invalid SPC5_FMPLL1_IDF_VALUE value specified"
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@ -783,7 +782,9 @@
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#if (SPC5_FMPLL1_CLK > SPC5_FMPLL1_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
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#error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)"
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#endif
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#endif /* SPC5_HAS_FMPLL1 */
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#if SPC5_HAS_AC0 || defined(__DOXYGEN__)
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/**
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* @brief AUX0 clock point.
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*/
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@ -799,6 +800,10 @@
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#error "invalid SPC5_AUX0CLK_SRC value specified"
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#endif
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#if !SPC5_HAS_FMPLL1 && (SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1)
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#error "SPC5_AUX0CLK_SRC, FMPLL1 not present"
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#endif
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/* Check on the AUX0 divider 0 settings.*/
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#if SPC5_MCONTROL_DIVIDER_VALUE == 0
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#define SPC5_CGM_AC0_DC0 0
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@ -816,7 +821,9 @@
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#else
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#define SPC5_MCONTROL_CLK 0
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#endif
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#endif /* #if SPC5_HAS_AC0 */
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#if SPC5_HAS_AC1 || defined(__DOXYGEN__)
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/**
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* @brief AUX1 clock point.
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*/
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@ -826,6 +833,10 @@
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#error "invalid SPC5_AUX1CLK_SRC value specified"
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#endif
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#if !SPC5_HAS_FMPLL1
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#error "SPC5_AUX1_CLK, FMPLL1 not present"
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#endif
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/* Check on the AUX1 divider 0 settings.*/
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#if SPC5_FMPLL1_CLK_DIVIDER_VALUE == 0
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#define SPC5_CGM_AC1_DC0 0
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@ -843,7 +854,9 @@
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#else
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#define SPC5_FMPLL1_DIV_CLK 0
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#endif
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#endif /* SPC5_HAS_AC1 */
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#if SPC5_HAS_AC2 || defined(__DOXYGEN__)
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/**
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* @brief AUX2 clock point.
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*/
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@ -861,6 +874,11 @@
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#error "invalid SPC5_AUX2CLK_SRC value specified"
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#endif
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#if !SPC5_HAS_FMPLL1 && ((SPC5_AUX2_CLK == SPC5_CGM_SS_FMPLL1) || \
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(SPC5_AUX2_CLK == SPC5_CGM_SS_FMPLL1_1D1))
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#error "SPC5_AUX2_CLK, FMPLL1 not present"
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#endif
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/* Check on the AUX2 divider 0 settings.*/
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#if SPC5_SP_CLK_DIVIDER_VALUE == 0
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#define SPC5_CGM_AC2_DC0 0
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@ -878,7 +896,9 @@
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#else
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#define SPC5_SP_CLK 0
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#endif
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#endif /* SPC5_HAS_AC2 */
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#if SPC5_HAS_AC3 || defined(__DOXYGEN__)
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/**
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* @brief AUX3 clock point.
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*/
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@ -896,6 +916,11 @@
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#error "invalid SPC5_AUX3CLK_SRC value specified"
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#endif
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#if !SPC5_HAS_FMPLL1 && ((SPC5_AUX2_CLK == SPC5_AUX3_CLK) || \
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(SPC5_AUX3_CLK == SPC5_CGM_SS_FMPLL1_1D1))
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#error "SPC5_AUX3_CLK, FMPLL1 not present"
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#endif
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/* Check on the AUX3 divider 0 settings.*/
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#if SPC5_FR_CLK_DIVIDER_VALUE == 0
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#define SPC5_CGM_AC3_DC0 0
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@ -913,6 +938,7 @@
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#else
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#define SPC5_FR_CLK 0
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#endif
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#endif /* SPC5_HAS_AC3 */
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/*===========================================================================*/
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/* Driver data structures and types. */
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@ -1,5 +1,6 @@
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# List of all the SPC560Pxx platform files.
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PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx/hal_lld.c \
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${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \
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${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
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${CHIBIOS}/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c \
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${CHIBIOS}/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c \
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@ -8,6 +9,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx/hal_lld.c \
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# Required include directories
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PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx \
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${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \
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${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \
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${CHIBIOS}/os/hal/platforms/SPC5xx/eTimer_v1 \
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${CHIBIOS}/os/hal/platforms/SPC5xx/FlexPWM_v1 \
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@ -25,6 +25,32 @@
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#ifndef _SPC560P_REGISTRY_H_
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#define _SPC560P_REGISTRY_H_
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if defined(_SPC560P34L1_) || defined(_SPC560P34L3_)
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#define _SPC560P34_
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#define _SPC560PXX_SMALL_
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#elif defined(_SPC560P40L1_) || defined(_SPC560P40L3_)
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#define _SPC560P40_
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#define _SPC560PXX_SMALL_
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#elif defined(_SPC560P44L3_) || defined(_SPC560P44L5_)
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#define _SPC560P44_
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#define _SPC560PXX_MEDIUM_
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#elif defined(_SPC560P50L3_) || defined(_SPC560P50L5_)
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#define _SPC560P50_
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#define _SPC560PXX_MEDIUM_
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#elif defined(_SPC560P54L5_) || defined(_SPC56AP54L3_) || defined(_SPC56AP54L5_)
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#define _SPC560P54_
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#define _SPC560PXX_LARGE_
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#elif defined(_SPC560P60L5_) || defined(_SPC56AP60L3_) || defined(_SPC56AP60L5_)
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#define _SPC560P60_
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#define _SPC560PXX_LARGE_
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#else
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#error "SPC56xPxx platform not defined"
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#endif
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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@ -33,6 +59,85 @@
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* @name SPC560Pxx capabilities
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* @{
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*/
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/* Clock attributes.*/
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#if defined(_SPC560PXX_SMALL_)
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#define SPC5_HAS_FMPLL1 FALSE
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#define SPC5_HAS_CLOCKOUT TRUE
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#define SPC5_HAS_AC0 FALSE
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#define SPC5_HAS_AC1 FALSE
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#define SPC5_HAS_AC2 FALSE
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#define SPC5_HAS_AC3 FALSE
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#elif defined(_SPC560PXX_MEDIUM_)
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#define SPC5_HAS_FMPLL1 TRUE
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#define SPC5_HAS_CLOCKOUT TRUE
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#define SPC5_HAS_AC0 TRUE
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#define SPC5_HAS_AC1 TRUE
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#define SPC5_HAS_AC2 TRUE
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#define SPC5_HAS_AC3 TRUE
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#else /* defined(_SPC560PXX_LARGE_) */
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#define SPC5_HAS_FMPLL1 FALSE
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#define SPC5_HAS_CLOCKOUT TRUE
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#define SPC5_HAS_AC0 FALSE
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#define SPC5_HAS_AC1 FALSE
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#define SPC5_HAS_AC2 FALSE
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#define SPC5_HAS_AC3 TRUE
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#endif
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/* DSPI attribures.*/
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#define SPC5_HAS_DSPI0 TRUE
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#define SPC5_HAS_DSPI1 TRUE
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#define SPC5_HAS_DSPI2 TRUE
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#define SPC5_DSPI_FIFO_DEPTH 5
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#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
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#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
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#define SPC5_DSPI0_RX_DMA_DEV_ID 2
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#define SPC5_DSPI1_TX1_DMA_DEV_ID 3
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#define SPC5_DSPI1_TX2_DMA_DEV_ID 0
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#define SPC5_DSPI1_RX_DMA_DEV_ID 4
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#define SPC5_DSPI2_TX1_DMA_DEV_ID 5
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#define SPC5_DSPI2_TX2_DMA_DEV_ID 0
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#define SPC5_DSPI2_RX_DMA_DEV_ID 6
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#define SPC5_DSPI0_TFFF_HANDLER vector76
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#define SPC5_DSPI0_TFFF_NUMBER 76
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#define SPC5_DSPI1_TFFF_HANDLER vector96
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#define SPC5_DSPI1_TFFF_NUMBER 96
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#define SPC5_DSPI2_TFFF_HANDLER vector116
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#define SPC5_DSPI2_TFFF_NUMBER 116
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#define SPC5_DSPI0_ENABLE_CLOCK()
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#define SPC5_DSPI0_DISABLE_CLOCK()
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#define SPC5_DSPI1_ENABLE_CLOCK()
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#define SPC5_DSPI1_DISABLE_CLOCK()
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#define SPC5_DSPI2_ENABLE_CLOCK()
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#define SPC5_DSPI2_DISABLE_CLOCK()
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#if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)
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#define SPC5_HAS_DSPI3 TRUE
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#define SPC5_DSPI3_TX1_DMA_DEV_ID 7
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#define SPC5_DSPI3_TX2_DMA_DEV_ID 0
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#define SPC5_DSPI3_RX_DMA_DEV_ID 8
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#define SPC5_DSPI3_TFFF_HANDLER vector219
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#define SPC5_DSPI3_TFFF_NUMBER 219
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#define SPC5_DSPI3_ENABLE_CLOCK()
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#define SPC5_DSPI3_DISABLE_CLOCK()
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#else
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#define SPC5_HAS_DSPI3 FALSE
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#endif
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#if defined(_SPC560PXX_LARGE_)
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#define SPC5_HAS_DSPI4 TRUE
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#define SPC5_DSPI4_TX1_DMA_DEV_ID 15
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#define SPC5_DSPI4_TX2_DMA_DEV_ID 0
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#define SPC5_DSPI4_RX_DMA_DEV_ID 21
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#define SPC5_DSPI4_TFFF_HANDLER vector258
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#define SPC5_DSPI4_TFFF_NUMBER 258
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#define SPC5_DSPI4_ENABLE_CLOCK()
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#define SPC5_DSPI4_DISABLE_CLOCK()
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#else
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#define SPC5_HAS_DSPI4 FALSE
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#endif
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/* eDMA attributes.*/
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#define SPC5_HAS_EDMA TRUE
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#define SPC5_EDMA_NCHANNELS 16
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@ -70,6 +175,7 @@
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#define SPC5_SIUL_NUM_PADSELS 36
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/* FlexPWM attributes.*/
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#if defined(_SPC560PXX_SMALL_) || defined(_SPC560PXX_MEDIUM_)
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||||
#define SPC5_HAS_FLEXPWM0 TRUE
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||||
#define SPC5_FLEXPWM0_PCTL 41
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#define SPC5_FLEXPWM0_RF0_HANDLER vector179
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|
@ -101,6 +207,9 @@
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#define SPC5_FLEXPWM0_FFLAG_NUMBER 191
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||||
#define SPC5_FLEXPWM0_REF_NUMBER 192
|
||||
#define SPC5_FLEXPWM0_CLK SPC5_MCONTROL_CLK
|
||||
#else /* defined(_SPC560PXX_LARGE_) */
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||||
#define SPC5_HAS_FLEXPWM0 FALSE
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#endif /* defined(_SPC560PXX_LARGE_) */
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||||
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||||
#define SPC5_HAS_FLEXPWM1 FALSE
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|
||||
|
|
@ -125,6 +234,7 @@
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#define SPC5_ETIMER0_RCF_NUMBER 167
|
||||
#define SPC5_ETIMER0_CLK SPC5_MCONTROL_CLK
|
||||
|
||||
#if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)
|
||||
#define SPC5_HAS_ETIMER1 TRUE
|
||||
#define SPC5_ETIMER1_PCTL 39
|
||||
#define SPC5_ETIMER1_TC0IR_HANDLER vector168
|
||||
|
|
@ -143,6 +253,10 @@
|
|||
#define SPC5_ETIMER1_RCF_NUMBER 178
|
||||
#define SPC5_ETIMER1_CLK SPC5_MCONTROL_CLK
|
||||
|
||||
#else /* !(defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)) */
|
||||
#define SPC5_HAS_ETIMER1 FALSE
|
||||
#endif /* !(defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)) */
|
||||
|
||||
#define SPC5_HAS_ETIMER2 FALSE
|
||||
|
||||
/* FlexCAN attributes.*/
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@
|
|||
#define SPC5_HAS_DSPI1 TRUE
|
||||
#define SPC5_HAS_DSPI2 TRUE
|
||||
#define SPC5_HAS_DSPI3 FALSE
|
||||
#define SPC5_HAS_DSPI4 FALSE
|
||||
#define SPC5_DSPI_FIFO_DEPTH 16
|
||||
#define SPC5_DSPI1_TX1_DMA_DEV_ID 12
|
||||
#define SPC5_DSPI1_TX2_DMA_DEV_ID 25
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@
|
|||
#define SPC5_HAS_DSPI1 TRUE
|
||||
#define SPC5_HAS_DSPI2 TRUE
|
||||
#define SPC5_HAS_DSPI3 TRUE
|
||||
#define SPC5_HAS_DSPI4 FALSE
|
||||
#define SPC5_DSPI_FIFO_DEPTH 16
|
||||
#define SPC5_DSPI1_TX1_DMA_DEV_ID 12
|
||||
#define SPC5_DSPI1_TX2_DMA_DEV_ID 24
|
||||
|
|
|
|||
|
|
@ -270,6 +270,10 @@ struct spc5_dspi {
|
|||
#if SPC5_HAS_DSPI3 || defined(__DOXYGEN__)
|
||||
#define SPC5_DSPI3 (*(struct spc5_dspi *)0xFFF9C000U)
|
||||
#endif
|
||||
|
||||
#if SPC5_HAS_DSPI4 || defined(__DOXYGEN__)
|
||||
#define SPC5_DSPI4 (*(struct spc5_dspi *)0x8FFA0000U)
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
#endif /* _SPC5_DSPI_H_ */
|
||||
|
|
|
|||
|
|
@ -1,15 +1,15 @@
|
|||
*****************************************************************************
|
||||
** ChibiOS/RT HAL - SPI driver demo for SPC563Mxx. **
|
||||
** ChibiOS/RT HAL - SPI driver demo for SPC564Axx. **
|
||||
*****************************************************************************
|
||||
|
||||
** TARGET **
|
||||
|
||||
The demo runs on an STMicroelectronics SPC563Mxx microcontroller installed on
|
||||
The demo runs on an STMicroelectronics SPC564Axx microcontroller installed on
|
||||
XPC56xx EVB Motherboard.
|
||||
|
||||
** The Demo **
|
||||
|
||||
The application demonstrates the use of the SPC563Mxx SPI driver.
|
||||
The application demonstrates the use of the SPC564Axx SPI driver.
|
||||
|
||||
** Board Setup **
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue