git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4689 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
parent
5d10f6a140
commit
7956cba1bf
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@ -55,6 +55,11 @@
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* @notapi
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* @notapi
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*/
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*/
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void hal_lld_init(void) {
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void hal_lld_init(void) {
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/* The system is switched to the RUN0 mode, the default for normal
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operations.*/
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if (halSPC560PSetRunMode(SPC560P_RUNMODE_RUN0) == CH_FAILED)
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chSysHalt();
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}
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}
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/**
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/**
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@ -66,6 +71,71 @@ void hal_lld_init(void) {
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* @special
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* @special
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*/
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*/
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void spc560p_clock_init(void) {
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void spc560p_clock_init(void) {
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/* Waiting for IRC stabilization before attempting anything else.*/
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while (!ME.GS.B.S_RC)
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;
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#if !SPC560P_NO_INIT
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#if defined(SPC560P_OSC_BYPASS)
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/* If the board is equipped with an oscillator instead of a xtal then the
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bypass must be activated.*/
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CGM.OSC_CTL.B.OSCBYP = TRUE;
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#endif /* SPC560P_ENABLE_XOSC */
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/* Initialization of the FMPLLs settings.*/
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CGM.FMPLL[0].CR.R = SPC560P_FMPLL0_ODF |
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(SPC560P_FMPLL0_IDF_VALUE << 26) |
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(SPC560P_FMPLL0_NDIV_VALUE << 16);
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CGM.FMPLL[0].MR.R = 0; /* TODO: Add a setting. */
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CGM.FMPLL[1].CR.R = SPC560P_FMPLL1_ODF |
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(SPC560P_FMPLL1_IDF_VALUE << 26) |
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(SPC560P_FMPLL1_NDIV_VALUE << 16);
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CGM.FMPLL[1].MR.R = 0; /* TODO: Add a setting. */
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/* Run modes initialization.*/
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ME.MER.R = SPC560P_ME_ME_BITS; /* Enabled run modes. */
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ME.TEST.R = SPC560P_ME_TEST_MC_BITS; /* TEST run mode. */
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ME.SAFE.R = SPC560P_ME_SAFE_MC_BITS; /* SAFE run mode. */
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ME.DRUN.R = SPC560P_ME_DRUN_MC_BITS; /* DRUN run mode. */
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ME.RUN[0].R = SPC560P_ME_RUN0_MC_BITS; /* RUN0 run mode. */
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ME.RUN[1].R = SPC560P_ME_RUN1_MC_BITS; /* RUN0 run mode. */
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ME.RUN[2].R = SPC560P_ME_RUN2_MC_BITS; /* RUN0 run mode. */
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ME.RUN[3].R = SPC560P_ME_RUN3_MC_BITS; /* RUN0 run mode. */
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ME.HALT0.R = SPC560P_ME_HALT0_MC_BITS; /* HALT0 run mode. */
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ME.STOP0.R = SPC560P_ME_STOP0_MC_BITS; /* STOP0 run mode. */
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/* Switches again to DRUN mode (current mode) in order to update the
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settings.*/
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if (halSPC560PSetRunMode(SPC560P_RUNMODE_DRUN) == CH_FAILED)
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chSysHalt();
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#endif /* !SPC560P_NO_INIT */
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}
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/**
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* @brief Switches the system to the specified run mode.
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*/
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bool_t halSPC560PSetRunMode(spc560prunmode_t mode) {
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/* Starts a transition process.*/
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ME.MCTL.R = SPC560P_ME_MCTL_MODE(mode) | SPC560P_ME_MCTL_KEY;
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ME.MCTL.R = SPC560P_ME_MCTL_MODE(mode) | SPC560P_ME_MCTL_KEY_INV;
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/* Waits the transition process to start.*/
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while (!ME.GS.B.S_MTRANS)
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;
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/* Waits the transition process to end.*/
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while (ME.GS.B.S_MTRANS)
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;
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/* Verifies that the mode has been effectively switched.*/
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if (ME.GS.B.S_CURRENTMODE != mode)
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return TRUE;
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return FALSE;
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}
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}
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/** @} */
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/** @} */
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@ -24,6 +24,7 @@
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* @pre This module requires the following macros to be defined in the
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* @p board.h file:
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* - SPC560P_XOSC_CLK.
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* - SPC560P_XOSC_CLK.
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* - SPC560P_OSC_BYPASS (optionally).
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* .
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* .
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*
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*
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* @addtogroup HAL
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* @addtogroup HAL
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@ -112,10 +113,65 @@
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* @name FMPLL_CR register bits definitions
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* @name FMPLL_CR register bits definitions
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* @{
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* @{
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*/
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*/
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#define SPC560P_FMPLL_ODF_DIV2 (0 << 24)
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#define SPC560P_FMPLL_ODF_DIV2 (0U << 24)
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#define SPC560P_FMPLL_ODF_DIV4 (1 << 24)
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#define SPC560P_FMPLL_ODF_DIV4 (1U << 24)
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#define SPC560P_FMPLL_ODF_DIV8 (2 << 24)
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#define SPC560P_FMPLL_ODF_DIV8 (2U << 24)
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#define SPC560P_FMPLL_ODF_DIV16 (3 << 24)
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#define SPC560P_FMPLL_ODF_DIV16 (3U << 24)
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/** @} */
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/**
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* @name ME_ME register bits definitions
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* @{
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*/
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#define SPC560P_ME_ME_RESET (1U << 0)
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#define SPC560P_ME_ME_TEST (2U << 0)
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#define SPC560P_ME_ME_SAFE (4U << 0)
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#define SPC560P_ME_ME_DRUN (8U << 0)
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#define SPC560P_ME_ME_RUN0 (16U << 0)
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#define SPC560P_ME_ME_RUN1 (32U << 0)
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#define SPC560P_ME_ME_RUN2 (64U << 0)
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#define SPC560P_ME_ME_RUN3 (128U << 0)
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#define SPC560P_ME_ME_HALT0 (256U << 0)
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#define SPC560P_ME_ME_STOP0 (1024U << 0)
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/** @} */
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/**
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* @name ME_xxx_MC registers bits definitions
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* @{
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*/
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#define SPC560P_ME_MC_SYSCLK_MASK (15U << 0)
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#define SPC560P_ME_MC_SYSCLK(n) ((n) << 0)
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#define SPC560P_ME_MC_SYSCLK_IRC SPC560P_ME_MC_SYSCLK(0)
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#define SPC560P_ME_MC_SYSCLK_XOSC SPC560P_ME_MC_SYSCLK(2)
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#define SPC560P_ME_MC_SYSCLK_FMPLL0 SPC560P_ME_MC_SYSCLK(4)
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#define SPC560P_ME_MC_SYSCLK_FMPLL1 SPC560P_ME_MC_SYSCLK(5)
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#define SPC560P_ME_MC_SYSCLK_DISABLED SPC560P_ME_MC_SYSCLK(15)
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#define SPC560P_ME_MC_IRCON (1U << 4)
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#define SPC560P_ME_MC_XOSC0ON (1U << 5)
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#define SPC560P_ME_MC_PLL0ON (1U << 6)
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#define SPC560P_ME_MC_PLL1ON (1U << 7)
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#define SPC560P_ME_MC_CFLAON_MASK (3U << 16)
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#define SPC560P_ME_MC_CFLAON(n) ((n) << 16)
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#define SPC560P_ME_MC_CFLAON_PD (1U << 16)
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#define SPC560P_ME_MC_CFLAON_LP (2U << 16)
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#define SPC560P_ME_MC_CFLAON_NORMAL (3U << 16)
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#define SPC560P_ME_MC_DFLAON_MASK (3U << 18)
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#define SPC560P_ME_MC_DFLAON(n) ((n) << 18)
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#define SPC560P_ME_MC_DFLAON_PD (1U << 18)
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#define SPC560P_ME_MC_DFLAON_LP (2U << 18)
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#define SPC560P_ME_MC_DFLAON_NORMAL (3U << 18)
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#define SPC560P_ME_MC_MVRON (1U << 20)
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#define SPC560P_ME_MC_PDO (1U << 23)
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/** @} */
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/**
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* @name ME_MCTL register bits definitions
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* @{
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*/
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#define SPC560P_ME_MCTL_KEY 0x5AF0U
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#define SPC560P_ME_MCTL_KEY_INV 0xA50FU
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#define SPC560P_ME_MCTL_MODE_MASK (15U << 28)
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#define SPC560P_ME_MCTL_MODE(n) ((n) << 28)
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/** @} */
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/** @} */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -123,13 +179,10 @@
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/*===========================================================================*/
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/*===========================================================================*/
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/**
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/**
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* @brief Clock bypass.
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* @brief Disables the clocks initialization in the HAL.
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* @note If set to @p TRUE then the PLL is not started and initialized, the
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* external clock is used as-is and the other clock-related settings
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* are ignored.
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*/
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*/
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#if !defined(SPC560P_CLK_BYPASS) || defined(__DOXYGEN__)
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#if !defined(SPC560P_NO_INIT) || defined(__DOXYGEN__)
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#define SPC560P_CLK_BYPASS FALSE
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#define SPC560P_NO_INIT FALSE
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#endif
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#endif
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/**
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/**
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@ -163,6 +216,159 @@
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#define SPC560P_FMPLL0_ODF SPC560P_FMPLL_ODF_DIV4
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#define SPC560P_FMPLL0_ODF SPC560P_FMPLL_ODF_DIV4
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#endif
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#endif
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/**
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* @brief FMPLL1 IDF divider value.
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* @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
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*/
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#if !defined(SPC560P_FMPLL1_IDF_VALUE) || defined(__DOXYGEN__)
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#define SPC560P_FMPLL1_IDF_VALUE 5
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#endif
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/**
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* @brief FMPLL1 NDIV divider value.
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* @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
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*/
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#if !defined(SPC560P_FMPLL1_NDIV_VALUE) || defined(__DOXYGEN__)
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#define SPC560P_FMPLL1_NDIV_VALUE 60
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#endif
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/**
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* @brief FMPLL1 ODF divider value.
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* @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
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*/
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#if !defined(SPC560P_FMPLL1_ODF) || defined(__DOXYGEN__)
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#define SPC560P_FMPLL1_ODF SPC560P_FMPLL_ODF_DIV4
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#endif
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/**
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* @brief Active run modes in ME_ME register.
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* @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
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* is no need to specify them.
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*/
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#if !defined(SPC560P_ME_ME_BITS) || defined(__DOXYGEN__)
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#define SPC560P_ME_ME_BITS 0
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#endif
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/**
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* @brief TEST mode settings.
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*/
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#if !defined(SPC560P_ME_TEST_MC_BITS) || defined(__DOXYGEN__)
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#define SPC560P_ME_TEST_MC_BITS (SPC560P_ME_MC_SYSCLK_IRC | \
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SPC560P_ME_MC_IRCON | \
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SPC560P_ME_MC_XOSC0ON | \
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SPC560P_ME_MC_PLL0ON | \
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SPC560P_ME_MC_PLL1ON | \
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SPC560P_ME_MC_CFLAON_NORMAL | \
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SPC560P_ME_MC_DFLAON_NORMAL | \
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SPC560P_ME_MC_MVRON)
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#endif
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/**
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* @brief SAFE mode settings.
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*/
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#if !defined(SPC560P_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
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#define SPC560P_ME_SAFE_MC_BITS (SPC560P_ME_MC_PDO)
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#endif
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/**
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* @brief DRUN mode settings.
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*/
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#if !defined(SPC560P_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
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#define SPC560P_ME_DRUN_MC_BITS (SPC560P_ME_MC_SYSCLK_FMPLL0 | \
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SPC560P_ME_MC_IRCON | \
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SPC560P_ME_MC_XOSC0ON | \
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SPC560P_ME_MC_PLL0ON | \
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SPC560P_ME_MC_PLL1ON | \
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SPC560P_ME_MC_CFLAON_NORMAL | \
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SPC560P_ME_MC_DFLAON_NORMAL | \
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SPC560P_ME_MC_MVRON)
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#endif
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/**
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* @brief RUN0 mode settings.
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*/
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#if !defined(SPC560P_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
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#define SPC560P_ME_RUN0_MC_BITS (SPC560P_ME_MC_SYSCLK_FMPLL0 | \
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SPC560P_ME_MC_IRCON | \
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SPC560P_ME_MC_XOSC0ON | \
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SPC560P_ME_MC_PLL0ON | \
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SPC560P_ME_MC_PLL1ON | \
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SPC560P_ME_MC_CFLAON_NORMAL | \
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SPC560P_ME_MC_DFLAON_NORMAL | \
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SPC560P_ME_MC_MVRON)
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#endif
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/**
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* @brief RUN1 mode settings.
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*/
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#if !defined(SPC560P_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
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#define SPC560P_ME_RUN1_MC_BITS (SPC560P_ME_MC_SYSCLK_FMPLL0 | \
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SPC560P_ME_MC_IRCON | \
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SPC560P_ME_MC_XOSC0ON | \
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SPC560P_ME_MC_PLL0ON | \
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SPC560P_ME_MC_PLL1ON | \
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SPC560P_ME_MC_CFLAON_NORMAL | \
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SPC560P_ME_MC_DFLAON_NORMAL | \
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SPC560P_ME_MC_MVRON)
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#endif
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/**
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* @brief RUN2 mode settings.
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*/
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#if !defined(SPC560P_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
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#define SPC560P_ME_RUN2_MC_BITS (SPC560P_ME_MC_SYSCLK_FMPLL0 | \
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SPC560P_ME_MC_IRCON | \
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SPC560P_ME_MC_XOSC0ON | \
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SPC560P_ME_MC_PLL0ON | \
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SPC560P_ME_MC_PLL1ON | \
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SPC560P_ME_MC_CFLAON_NORMAL | \
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SPC560P_ME_MC_DFLAON_NORMAL | \
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SPC560P_ME_MC_MVRON)
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#endif
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/**
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* @brief RUN3 mode settings.
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*/
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#if !defined(SPC560P_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
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#define SPC560P_ME_RUN3_MC_BITS (SPC560P_ME_MC_SYSCLK_FMPLL0 | \
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SPC560P_ME_MC_IRCON | \
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SPC560P_ME_MC_XOSC0ON | \
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SPC560P_ME_MC_PLL0ON | \
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SPC560P_ME_MC_PLL1ON | \
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SPC560P_ME_MC_CFLAON_NORMAL | \
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SPC560P_ME_MC_DFLAON_NORMAL | \
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SPC560P_ME_MC_MVRON)
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#endif
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/**
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* @brief HALT0 mode settings.
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*/
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#if !defined(SPC560P_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
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#define SPC560P_ME_HALT0_MC_BITS (SPC560P_ME_MC_SYSCLK_FMPLL0 | \
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SPC560P_ME_MC_IRCON | \
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SPC560P_ME_MC_XOSC0ON | \
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SPC560P_ME_MC_PLL0ON | \
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SPC560P_ME_MC_PLL1ON | \
|
||||||
|
SPC560P_ME_MC_CFLAON_NORMAL | \
|
||||||
|
SPC560P_ME_MC_DFLAON_NORMAL | \
|
||||||
|
SPC560P_ME_MC_MVRON)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STOP0 mode settings.
|
||||||
|
*/
|
||||||
|
#if !defined(SPC560P_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
|
||||||
|
#define SPC560P_ME_STOP0_MC_BITS (SPC560P_ME_MC_SYSCLK_FMPLL0 | \
|
||||||
|
SPC560P_ME_MC_IRCON | \
|
||||||
|
SPC560P_ME_MC_XOSC0ON | \
|
||||||
|
SPC560P_ME_MC_PLL0ON | \
|
||||||
|
SPC560P_ME_MC_PLL1ON | \
|
||||||
|
SPC560P_ME_MC_CFLAON_NORMAL | \
|
||||||
|
SPC560P_ME_MC_DFLAON_NORMAL | \
|
||||||
|
SPC560P_ME_MC_MVRON)
|
||||||
|
#endif
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Derived constants and error checks. */
|
/* Derived constants and error checks. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
@ -196,7 +402,6 @@
|
||||||
#error "invalid SPC560P_FMPLL0_ODF value specified"
|
#error "invalid SPC560P_FMPLL0_ODF value specified"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief SPC560P_FMPLL0_VCO_CLK clock point.
|
* @brief SPC560P_FMPLL0_VCO_CLK clock point.
|
||||||
*/
|
*/
|
||||||
|
|
@ -210,30 +415,78 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief SPC560P_XOSC_CLK clock point.
|
* @brief SPC560P_FMPLL0_CLK clock point.
|
||||||
*/
|
*/
|
||||||
#define SPC560P_FMPLL0_CLK \
|
#define SPC560P_FMPLL0_CLK \
|
||||||
(SPC560P_FMPLL0_VCO_CLK / SPC560P_FMPLL0_ODF_VALUE)
|
(SPC560P_FMPLL0_VCO_CLK / SPC560P_FMPLL0_ODF_VALUE)
|
||||||
|
|
||||||
/* Check on SPC560P_FMPLL0_CLK.*/
|
/* Check on SPC560P_FMPLL0_CLK.*/
|
||||||
#if SPC560P_FMPLL0_CLK > SPC560P_FMPLL0_CLK_MAX
|
#if (SPC560P_FMPLL0_CLK > SPC560P_FMPLL0_CLK_MAX) && !SPC560P_ALLOW_OVERCLOCK
|
||||||
#error "SPC560P_FMPLL0_CLK outside acceptable range (0...SPC560P_FMPLL0_CLK_MAX)"
|
#error "SPC560P_FMPLL0_CLK outside acceptable range (0...SPC560P_FMPLL0_CLK_MAX)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* FMPLL0 activation conditions.*/
|
/* Check on SPC560P_FMPLL1_IDF_VALUE.*/
|
||||||
#if 1 || defined(__DOXYGEN__)
|
#if (SPC560P_FMPLL1_IDF_VALUE < 1) || (SPC560P_FMPLL1_IDF_VALUE > 15)
|
||||||
/**
|
#error "invalid SPC560P_FMPLL1_IDF_VALUE value specified"
|
||||||
* @brief FMPLL0 activation flag.
|
#endif
|
||||||
*/
|
|
||||||
#define SPC560P_ACTIVATE_FMPLL0 TRUE
|
/* Check on SPC560P_FMPLL1_NDIV_VALUE.*/
|
||||||
|
#if (SPC560P_FMPLL1_NDIV_VALUE < 32) || (SPC560P_FMPLL1_NDIV_VALUE > 96)
|
||||||
|
#error "invalid SPC560P_FMPLL1_NDIV_VALUE value specified"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Check on SPC560P_FMPLL1_ODF.*/
|
||||||
|
#if (SPC560P_FMPLL1_ODF == SPC560P_FMPLL_ODF_DIV2)
|
||||||
|
#define SPC560P_FMPLL1_ODF_VALUE 2
|
||||||
|
#elif (SPC560P_FMPLL1_ODF == SPC560P_FMPLL_ODF_DIV4)
|
||||||
|
#define SPC560P_FMPLL1_ODF_VALUE 4
|
||||||
|
#elif (SPC560P_FMPLL1_ODF == SPC560P_FMPLL_ODF_DIV8)
|
||||||
|
#define SPC560P_FMPLL1_ODF_VALUE 8
|
||||||
|
#elif (SPC560P_FMPLL1_ODF == SPC560P_FMPLL_ODF_DIV16)
|
||||||
|
#define SPC560P_FMPLL1_ODF_VALUE 16
|
||||||
#else
|
#else
|
||||||
#define SPC560P_ACTIVATE_FMPLL0 FALSE
|
#error "invalid SPC560P_FMPLL1_ODF value specified"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SPC560P_FMPLL1_VCO_CLK clock point.
|
||||||
|
*/
|
||||||
|
#define SPC560P_FMPLL1_VCO_CLK \
|
||||||
|
((SPC560P_XOSC_CLK / SPC560P_FMPLL1_IDF_VALUE) * SPC560P_FMPLL1_NDIV_VALUE)
|
||||||
|
|
||||||
|
/* Check on FMPLL1 VCO output.*/
|
||||||
|
#if (SPC560P_FMPLL1_VCO_CLK < SPC560P_FMPLLVCO_MIN) || \
|
||||||
|
(SPC560P_FMPLL1_VCO_CLK > SPC560P_FMPLLVCO_MAX)
|
||||||
|
#error "SPC560P_FMPLL1_CLK outside acceptable range (SPC560P_FMPLLVCO_MIN...SPC560P_FMPLLVCO_MAX)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SPC560P_FMPLL1_CLK clock point.
|
||||||
|
*/
|
||||||
|
#define SPC560P_FMPLL1_CLK \
|
||||||
|
(SPC560P_FMPLL1_VCO_CLK / SPC560P_FMPLL1_ODF_VALUE)
|
||||||
|
|
||||||
|
/* Check on SPC560P_FMPLL1_CLK.*/
|
||||||
|
#if (SPC560P_FMPLL1_CLK > SPC560P_FMPLL1_CLK_MAX) && !SPC560P_ALLOW_OVERCLOCK
|
||||||
|
#error "SPC560P_FMPLL1_CLK outside acceptable range (0...SPC560P_FMPLL1_CLK_MAX)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver data structures and types. */
|
/* Driver data structures and types. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
SPC560P_RUNMODE_TEST = 1,
|
||||||
|
SPC560P_RUNMODE_SAFE = 2,
|
||||||
|
SPC560P_RUNMODE_DRUN = 3,
|
||||||
|
SPC560P_RUNMODE_RUN0 = 4,
|
||||||
|
SPC560P_RUNMODE_RUN1 = 5,
|
||||||
|
SPC560P_RUNMODE_RUN2 = 6,
|
||||||
|
SPC560P_RUNMODE_RUN3 = 7,
|
||||||
|
SPC560P_RUNMODE_HALT0 = 8,
|
||||||
|
SPC560P_RUNMODE_STOP0 = 10
|
||||||
|
} spc560prunmode_t;
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver macros. */
|
/* Driver macros. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
@ -247,6 +500,7 @@ extern "C" {
|
||||||
#endif
|
#endif
|
||||||
void hal_lld_init(void);
|
void hal_lld_init(void);
|
||||||
void spc560p_clock_init(void);
|
void spc560p_clock_init(void);
|
||||||
|
bool_t halSPC560PSetRunMode(spc560prunmode_t mode);
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue