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Nucleo32 fixed some pins, ADCv3 compiles. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8583 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
Giovanni Di Sirio 2015-12-11 11:11:45 +00:00
parent 129c0f14b0
commit 78fa3a2203
8 changed files with 55 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
os/hal/boards/ST_NUCLEO32_F031K6/board.h
View File

@ -222,8 +222,8 @@
* PA2 - VCP_TX (alternate 1).
* PA3 - ARD_A2 (input pullup).
* PA4 - ARD_A3 (input pullup).
* PA5 - ARD_A4 (input floating).
* PA6 - ARD_A5 (input floating).
* PA5 - ARD_A4 (input pullup).
* PA6 - ARD_A5 (input pullup).
* PA7 - ARD_A6 (input pullup).
* PA8 - ARD_D9 (input pullup).
* PA9 - ARD_D1 (input pullup).
@ -287,8 +287,8 @@
PIN_PUPDR_FLOATING(GPIOA_VCP_TX) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A2) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A3) | \
PIN_PUPDR_FLOATING(GPIOA_ARD_A4) | \
PIN_PUPDR_FLOATING(GPIOA_ARD_A5) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A4) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A5) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A6) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_D9) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_D1) | \
@ -342,7 +342,7 @@
* PB5 - ARD_D11 (input pullup).
* PB6 - ARD_D5 ARD_A5_ALT (input pullup).
* PB7 - ARD_D4 ARD_A4_ALT (input pullup).
* PB8 - PIN8 (input floating).
* PB8 - PIN8 (input pullup).
* PB9 - PIN9 (input pullup).
* PB10 - PIN10 (input pullup).
* PB11 - PIN11 (input pullup).
@ -407,7 +407,7 @@
PIN_PUPDR_PULLUP(GPIOB_ARD_D11) | \
PIN_PUPDR_PULLUP(GPIOB_ARD_D5) | \
PIN_PUPDR_PULLUP(GPIOB_ARD_D4) | \
PIN_PUPDR_FLOATING(GPIOB_PIN8) | \
PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
PIN_PUPDR_PULLUP(GPIOB_PIN11) | \

6
os/hal/boards/ST_NUCLEO32_F031K6/cfg/board.chcfg
View File

@ -61,7 +61,7 @@
Type="PushPull"
Level="Low"
Speed="High"
Resistor="Floating"
Resistor="PullUp"
Mode="Input"
Alternate="0" />
<pin6
@ -69,7 +69,7 @@
Type="PushPull"
Level="High"
Speed="Maximum"
Resistor="Floating"
Resistor="PullUp"
Mode="Input"
Alternate="0" />
<pin7
@ -215,7 +215,7 @@
Type="PushPull"
Level="High"
Speed="Maximum"
Resistor="Floating"
Resistor="PullUp"
Mode="Input"
Alternate="0" />
<pin9

12
os/hal/boards/ST_NUCLEO32_F042K6/board.h
View File

@ -222,8 +222,8 @@
* PA2 - VCP_TX (alternate 1).
* PA3 - ARD_A2 (input pullup).
* PA4 - ARD_A3 (input pullup).
* PA5 - ARD_A4 (input floating).
* PA6 - ARD_A5 (input floating).
* PA5 - ARD_A4 (input pullup).
* PA6 - ARD_A5 (input pullup).
* PA7 - ARD_A6 (input pullup).
* PA8 - ARD_D9 (input pullup).
* PA9 - ARD_D1 (input pullup).
@ -287,8 +287,8 @@
PIN_PUPDR_FLOATING(GPIOA_VCP_TX) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A2) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A3) | \
PIN_PUPDR_FLOATING(GPIOA_ARD_A4) | \
PIN_PUPDR_FLOATING(GPIOA_ARD_A5) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A4) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A5) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A6) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_D9) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_D1) | \
@ -342,7 +342,7 @@
* PB5 - ARD_D11 (input pullup).
* PB6 - ARD_D5 ARD_A5_ALT (input pullup).
* PB7 - ARD_D4 ARD_A4_ALT (input pullup).
* PB8 - PIN8 (input floating).
* PB8 - PIN8 (input pullup).
* PB9 - PIN9 (input pullup).
* PB10 - PIN10 (input pullup).
* PB11 - PIN11 (input pullup).
@ -407,7 +407,7 @@
PIN_PUPDR_PULLUP(GPIOB_ARD_D11) | \
PIN_PUPDR_PULLUP(GPIOB_ARD_D5) | \
PIN_PUPDR_PULLUP(GPIOB_ARD_D4) | \
PIN_PUPDR_FLOATING(GPIOB_PIN8) | \
PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
PIN_PUPDR_PULLUP(GPIOB_PIN11) | \

6
os/hal/boards/ST_NUCLEO32_F042K6/cfg/board.chcfg
View File

@ -61,7 +61,7 @@
Type="PushPull"
Level="Low"
Speed="High"
Resistor="Floating"
Resistor="PullUp"
Mode="Input"
Alternate="0" />
<pin6
@ -69,7 +69,7 @@
Type="PushPull"
Level="High"
Speed="Maximum"
Resistor="Floating"
Resistor="PullUp"
Mode="Input"
Alternate="0" />
<pin7
@ -215,7 +215,7 @@
Type="PushPull"
Level="High"
Speed="Maximum"
Resistor="Floating"
Resistor="PullUp"
Mode="Input"
Alternate="0" />
<pin9

12
os/hal/boards/ST_NUCLEO32_F303K8/board.h
View File

@ -222,8 +222,8 @@
* PA2 - VCP_TX (alternate 7).
* PA3 - ARD_A2 (input pullup).
* PA4 - ARD_A3 (input pullup).
* PA5 - ARD_A4 (input floating).
* PA6 - ARD_A5 (input floating).
* PA5 - ARD_A4 (input pullup).
* PA6 - ARD_A5 (input pullup).
* PA7 - ARD_A6 (input pullup).
* PA8 - ARD_D9 (input pullup).
* PA9 - ARD_D1 (input pullup).
@ -287,8 +287,8 @@
PIN_PUPDR_FLOATING(GPIOA_VCP_TX) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A2) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A3) | \
PIN_PUPDR_FLOATING(GPIOA_ARD_A4) | \
PIN_PUPDR_FLOATING(GPIOA_ARD_A5) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A4) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A5) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_A6) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_D9) | \
PIN_PUPDR_PULLUP(GPIOA_ARD_D1) | \
@ -342,7 +342,7 @@
* PB5 - ARD_D11 (input pullup).
* PB6 - ARD_D5 ARD_A5_ALT (input pullup).
* PB7 - ARD_D4 ARD_A4_ALT (input pullup).
* PB8 - PIN8 (input floating).
* PB8 - PIN8 (input pullup).
* PB9 - PIN9 (input pullup).
* PB10 - PIN10 (input pullup).
* PB11 - PIN11 (input pullup).
@ -407,7 +407,7 @@
PIN_PUPDR_PULLUP(GPIOB_ARD_D11) | \
PIN_PUPDR_PULLUP(GPIOB_ARD_D5) | \
PIN_PUPDR_PULLUP(GPIOB_ARD_D4) | \
PIN_PUPDR_FLOATING(GPIOB_PIN8) | \
PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
PIN_PUPDR_PULLUP(GPIOB_PIN11) | \

6
os/hal/boards/ST_NUCLEO32_F303K8/cfg/board.chcfg
View File

@ -61,7 +61,7 @@
Type="PushPull"
Level="Low"
Speed="High"
Resistor="Floating"
Resistor="PullUp"
Mode="Input"
Alternate="0" />
<pin6
@ -69,7 +69,7 @@
Type="PushPull"
Level="High"
Speed="Maximum"
Resistor="Floating"
Resistor="PullUp"
Mode="Input"
Alternate="0" />
<pin7
@ -215,7 +215,7 @@
Type="PushPull"
Level="High"
Speed="Maximum"
Resistor="Floating"
Resistor="PullUp"
Mode="Input"
Alternate="0" />
<pin9

16
os/hal/ports/STM32/LLD/ADCv3/adc_lld.h
View File

@ -35,6 +35,7 @@
* @name Available analog channels
* @{
*/
#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */
#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
@ -59,6 +60,7 @@
* @name Sampling rates
* @{
*/
#if defined(STM32F3XX)
#define ADC_SMPR_SMP_1P5 0 /**< @brief 14 cycles conversion time */
#define ADC_SMPR_SMP_2P5 1 /**< @brief 15 cycles conversion time. */
#define ADC_SMPR_SMP_4P5 2 /**< @brief 17 cycles conversion time. */
@ -67,6 +69,17 @@
#define ADC_SMPR_SMP_61P5 5 /**< @brief 74 cycles conversion time. */
#define ADC_SMPR_SMP_181P5 6 /**< @brief 194 cycles conversion time. */
#define ADC_SMPR_SMP_601P5 7 /**< @brief 614 cycles conversion time. */
#endif
#if defined(STM32L4XX)
#define ADC_SMPR_SMP_2P5 0 /**< @brief 15 cycles conversion time */
#define ADC_SMPR_SMP_6P5 1 /**< @brief 19 cycles conversion time. */
#define ADC_SMPR_SMP_12P5 2 /**< @brief 25 cycles conversion time. */
#define ADC_SMPR_SMP_24P5 3 /**< @brief 37 cycles conversion time. */
#define ADC_SMPR_SMP_47P5 4 /**< @brief 60 cycles conversion time. */
#define ADC_SMPR_SMP_92P5 5 /**< @brief 105 cycles conversion time. */
#define ADC_SMPR_SMP_247P5 6 /**< @brief 260 cycles conversion time. */
#define ADC_SMPR_SMP_640P5 7 /**< @brief 653 cycles conversion time. */
#endif
/** @} */
/**
@ -612,7 +625,7 @@ typedef struct {
* @note The bits DMAEN and DMACFG are enforced internally
* to the driver, keep them to zero.
* @note The bits @p ADC_CFGR_CONT or @p ADC_CFGR_DISCEN must be
* specified in continuous more or if the buffer depth is
* specified in continuous mode or if the buffer depth is
* greater than one.
*/
uint32_t cfgr;
@ -768,6 +781,7 @@ struct ADCDriver {
* @name Sampling rate settings helper macros
* @{
*/
#define ADC_SMPR1_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */
#define ADC_SMPR1_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
#define ADC_SMPR1_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
#define ADC_SMPR1_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */

21
testhal/STM32/STM32L4xx/GPT-ADC/main.c
View File

@ -91,20 +91,25 @@ static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) {
* ADC conversion group.
* Mode: Continuous, 16 samples of 2 channels, HS triggered by
* GPT4-TRGO.
* Channels: Sensor, VRef.
* Channels: VRef, PC1.
*/
static const ADCConversionGroup adcgrpcfg1 = {
true,
ADC_GRP1_NUM_CHANNELS,
adccallback,
adcerrorcallback,
0, /* CR1 */
ADC_CR2_EXTEN_RISING | ADC_CR2_EXTSEL_SRC(12), /* CR2 */
ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_144) | ADC_SMPR1_SMP_VREF(ADC_SAMPLE_144),
0, /* SMPR2 */
ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), /* SQR1 */
0, /* SQR1 */
ADC_SQR3_SQ2_N(ADC_CHANNEL_SENSOR) | ADC_SQR3_SQ1_N(ADC_CHANNEL_VREFINT)
ADC_CFGR_CONT | ADC_CFGR_EXTEN_RISING | ADC_CFGR_EXTSEL_SRC(12), /* CFGR */
ADC_TR(0, 4095), /* TR1 */
{ /* SMPR[2] */
ADC_SMPR1_SMP_AN0(ADC_SMPR_SMP_247P5),
ADC_SMPR2_SMP_AN11(ADC_SMPR_SMP_247P5)
},
{ /* SQR[4] */
ADC_SQR1_SQ1_N(ADC_CHANNEL_IN0) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN11),
0,
0,
0
}
};
/*===========================================================================*/