git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1367 35acf78f-673a-0410-8e92-d51de3d6d3f4

demos/ARM7-AT91SAM7X-GCC/board.c

@@ -45,6 +45,9 @@ static CH_IRQ_HANDLER(SYSIrqHandler) {
  */
 void hwinit0(void) {
   
+  /* Watchdog disabled.*/
+  AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+  
   at91sam7_clock_init();
 }
 

demos/ARM7-AT91SAM7X-LWIP-GCC/board.c

@@ -45,6 +45,9 @@ static CH_IRQ_HANDLER(SYSIrqHandler) {
  */
 void hwinit0(void) {
   
+  /* Watchdog disabled.*/
+  AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+  
   at91sam7_clock_init();
 }
 

demos/ARM7-AT91SAM7X-LWIP-GCC/main.c

@@ -21,8 +21,8 @@
 #include "hal.h"
 #include "test.h"
 
-#include "lwip\lwipthread.h"
+#include "lwip/lwipthread.h"
-#include "web\web.h"
+#include "web/web.h"
 
 static WORKING_AREA(waThread1, 64);
 static msg_t Thread1(void *arg) {

demos/ARM7-AT91SAM7X-UIP-GCC/board.c

@@ -45,6 +45,9 @@ static CH_IRQ_HANDLER(SYSIrqHandler) {
  */
 void hwinit0(void) {
 
+  /* Watchdog disabled.*/
+  AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+  
   at91sam7_clock_init();
 }
 

os/hal/platforms/AT91SAM7/hal_lld.c

@@ -100,9 +100,6 @@ void at91sam7_clock_init(void) {
   /* Flash Memory: 1 wait state, about 50 cycles in a microsecond.*/
   AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
 
-  /* Watchdog disabled.*/
-  AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
-
   /* Enables the main oscillator and waits 56 slow cycles as startup time.*/
   AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN;
   while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS))
@@ -112,6 +109,7 @@ void at91sam7_clock_init(void) {
      PLLfreq = 96109714 Hz (rounded).*/
   AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) |
                              (AT91C_CKGR_PLLCOUNT & (10 << 8)) |
+                             (AT91SAM7_USBDIV) |
                              (AT91C_CKGR_MUL & (72 << 16));
   while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK))
     ;

os/hal/platforms/AT91SAM7/hal_lld.h

@@ -41,6 +41,13 @@
 #define AT91SAM7_SPURIOUS_HANDLER_HOOK()
 #endif
 
+/**
+ * @brief Default divider for the USB clock - half the PLL clock.
+ */
+#if !defined(AT91SAM7_USBDIV) || defined(__DOXYGEN__)
+#define AT91SAM7_USBDIV AT91C_CKGR_USBDIV_1
+#endif
+
 /*===========================================================================*/
 /* Driver constants.                                                         */
 /*===========================================================================*/