diff --git a/os/hal/platforms/STM32F0xx/stm32_rcc.h b/os/hal/platforms/STM32F0xx/stm32_rcc.h index d10aa6de7..2db4b26fa 100644 --- a/os/hal/platforms/STM32F0xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F0xx/stm32_rcc.h @@ -528,6 +528,60 @@ * @api */ #define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the CRC peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp) + +/** + * @brief Disables the CRC peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCRC(lp) rccDisableAHB(RCC_AHBENR_CRCEN, lp) + +/** + * @brief Resets the CRC peripheral. + * + * @api + */ +#define rccResetCRC() rccResetAHB(RCC_AHBRSTR_CRCRST) + +/** + * @brief Enables the WWDG peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableWWDG(lp) rccEnableAPB1(RCC_APB1ENR_WWDGEN, lp) + +/** + * @brief Disables the WWDG peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableWWDG(lp) rccDisableAPB1(RCC_APB1ENR_WWDGEN, lp) + +/** + * @brief Resets the WWDG peripheral. + * + * @api + */ +#define rccResetWWDG() rccResetAPB1(RCC_APB1RSTR_WWDGRST) /** @} */ /*===========================================================================*/ diff --git a/readme.txt b/readme.txt index 6b632cf65..7cd483b38 100644 --- a/readme.txt +++ b/readme.txt @@ -82,6 +82,8 @@ ***************************************************************************** *** 2.5.2 *** +- FIX: Fixed STM32F0 RCC enable/disable/reset functions for CRC and WWDG + (bug 3602150). - FIX: Fixed missing parenthesis in use of macro arguments (bug 3601638). - FIX: Fixed compile errors in Posix-GCC demo (bug 3601621)(backported to 2.4.4).