I2C. Totally broken.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3546 35acf78f-673a-0410-8e92-d51de3d6d3f4master
barthess
parent
2ad41625e0
commit
7463a3f1ff
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@ -46,9 +46,6 @@
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver constants. */
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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#define I2C_STOP_GPT_TIMEOUT 50 /* waiting timer value */
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#define I2C_START_GPT_TIMEOUT 50 /* waiting timer value */
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#define I2C_POLLING_TIMEOUT 0xFFFF
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/* Driver exported variables. */
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@ -77,324 +74,13 @@ static volatile uint16_t dbgCR2 = 0;
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#endif /* CH_DBG_ENABLE_ASSERTS */
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#endif /* CH_DBG_ENABLE_ASSERTS */
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/* defines for convenience purpose */
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/* defines for convenience purpose */
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#if I2C_SUPPORTS_CALLBACKS
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#define txBuffp (i2cp->txbuff_p)
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#define txBuffp (i2cp->txbuff_p)
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#define rxBuffp (i2cp->rxbuff_p)
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#define rxBuffp (i2cp->rxbuff_p)
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#endif /* I2C_SUPPORTS_CALLBACKS */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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#if I2C_SUPPORTS_CALLBACKS
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#if (!(STM32_I2C_I2C1_USE_POLLING_WAIT)) && STM32_I2C_USE_I2C1
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/* I2C1 GPT callback. */
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static void i2c1gptcb(GPTDriver *gptp) {
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(void)gptp;
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I2CDriver *i2cp = &I2CD1;
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chSysLockFromIsr();
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i2cp->flags &= ~I2C_FLG_TIMER_ARMED;
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switch(i2cp->id_state){
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case I2C_ACTIVE_TRANSMIT:
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i2c_lld_master_transmit(i2cp, i2cp->slave_addr, i2cp->txbuf, i2cp->txbytes, i2cp->rxbuf, i2cp->rxbytes);
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break;
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case I2C_ACTIVE_RECEIVE:
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i2c_lld_master_receive(i2cp, i2cp->slave_addr, i2cp->rxbuf, i2cp->rxbytes);
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break;
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case I2C_ACTIVE_TRANSCEIVE:
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i2c_lld_master_transceive(i2cp);
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break;
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default:
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break;
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}
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chSysUnlockFromIsr();
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}
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/* I2C1 GPT configuration. */
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static const GPTConfig i2c1gptcfg = {
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1000000, /* 1MHz timer clock.*/
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i2c1gptcb /* Timer callback.*/
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};
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#endif /* STM32_I2C_I2C1_USE_POLLING_WAIT */
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#if (!(STM32_I2C_I2C2_USE_POLLING_WAIT)) && STM32_I2C_USE_I2C2
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/* I2C2 GPT callback. */
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static void i2c2gptcb(GPTDriver *gptp) {
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(void)gptp;
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I2CDriver *i2cp = &I2CD2;
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chSysLockFromIsr();
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i2cp->flags &= ~I2C_FLG_TIMER_ARMED;
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switch(i2cp->id_state){
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case I2C_ACTIVE_TRANSMIT:
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i2c_lld_master_transmit(i2cp, i2cp->slave_addr, i2cp->txbuf, i2cp->txbytes, i2cp->rxbuf, i2cp->rxbytes);
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break;
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case I2C_ACTIVE_RECEIVE:
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i2c_lld_master_receive(i2cp, i2cp->slave_addr, i2cp->rxbuf, i2cp->rxbytes);
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break;
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case I2C_ACTIVE_TRANSCEIVE:
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i2c_lld_master_transceive(i2cp);
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break;
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default:
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break;
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}
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chSysUnlockFromIsr();
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}
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/* I2C2 GPT configuration. */
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static const GPTConfig i2c2gptcfg = {
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1000000, /* 1MHz timer clock.*/
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i2c2gptcb /* Timer callback.*/
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};
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#endif /* STM32_I2C_I2C2_USE_POLLING_WAIT */
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#endif /* I2C_SUPPORTS_CALLBACKS */
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/**
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* @brief Function for I2C debugging purpose.
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* @note Internal use only.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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#if CH_DBG_ENABLE_ASSERTS
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void _i2c_unhandled_case(I2CDriver *i2cp){
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dbgCR1 = i2cp->id_i2c->CR1;
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dbgCR2 = i2cp->id_i2c->CR2;
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chDbgAssert((dbgSR1 + dbgSR2) == 0,
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"i2c_serve_event_interrupt(), #1",
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"unhandled case");
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}
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#else
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#define _i2c_unhandled_case(i2cp)
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#endif /* CH_DBG_ENABLE_ASSERTS */
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#if I2C_SUPPORTS_CALLBACKS
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/**
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* @brief Return the last event value from I2C status registers.
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* @note Internal use only.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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static uint32_t i2c_get_event(I2CDriver *i2cp){
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uint16_t regSR1 = i2cp->id_i2c->SR1;
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uint16_t regSR2 = i2cp->id_i2c->SR2;
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#if CH_DBG_ENABLE_ASSERTS
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dbgSR1 = regSR1;
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dbgSR2 = regSR2;
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#endif /* CH_DBG_ENABLE_ASSERTS */
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return (I2C_EV_MASK & (regSR1 | (regSR2 << 16)));
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}
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/**
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* @brief Handle the flags/interrupts.
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* @note Internal use only.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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void _i2c_ev6_master_rec_mode_selected(I2CDriver *i2cp){
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I2C_TypeDef *dp = i2cp->id_i2c;
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switch(i2cp->flags & EV6_SUBEV_MASK) {
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case I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED: /* only an single byte to receive */
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dp->CR1 &= (uint16_t)~I2C_CR1_ACK; /* Clear ACK */
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dp->CR1 |= I2C_CR1_STOP; /* Program the STOP */
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break;
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case I2C_EV6_1_MASTER_REC_2BTR_MODE_SELECTED: /* only two bytes to receive */
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dp->CR1 &= (uint16_t)~I2C_CR1_ACK; /* Clear ACK */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; /* Disable the ITBUF in order to have only the BTF interrupt */
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break;
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default: /* more than 2 bytes to receive */
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break;
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}
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}
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/**
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* @brief Handle cases of 2 or 3 bytes receiving.
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* @note Internal use only.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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void _i2c_ev7_master_rec_byte_qued(I2CDriver *i2cp){
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I2C_TypeDef *dp = i2cp->id_i2c;
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switch(i2cp->flags & EV7_SUBEV_MASK) {
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case I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS:
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/* Only for case of three bytes to be received.
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* DataN-2 and DataN-1 already received. */
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dp->CR1 &= (uint16_t)~I2C_CR1_ACK; /* Clear ACK */
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*rxBuffp = dp->DR; /* Read the DataN-2. This clear the RXE & BFT flags and launch the DataN exception in the shift register (ending the SCL stretch) */
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rxBuffp++;
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chSysLockFromIsr();
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dp->CR1 |= I2C_CR1_STOP; /* Program the STOP */
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*rxBuffp = dp->DR; /* Read the DataN-1 */
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chSysUnlockFromIsr();
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rxBuffp++;
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i2cp->rxbytes -= 2; /* Decrement the number of readed bytes */
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i2cp->flags = 0;
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dp->CR2 |= I2C_CR2_ITBUFEN; /* ready for read DataN. Enable interrupt for next (and last) RxNE event*/
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break;
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case I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS:
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/* only for case of two bytes to be received
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* DataN-1 and DataN are received */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN;
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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chSysLockFromIsr();
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dp->CR1 |= I2C_CR1_STOP; /* Program the STOP */
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*rxBuffp = dp->DR; /* Read the DataN-1*/
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rxBuffp++;
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*rxBuffp = dp->DR; /* Read the DataN*/
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chSysUnlockFromIsr();
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i2cp->rxbytes = 0;
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i2cp->flags = 0;
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_i2c_isr_code(i2cp, i2cp->id_slave_config); /* Portable I2C ISR code defined in the high level driver. */
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break;
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case I2C_FLG_MASTER_RECEIVER:
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/* Some times in hi load scenarions it is possible to "miss" interrupt
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* because STM32 I2C has OR'ed interrupt sources. This case handle that
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* scenario. */
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if (i2cp->rxbytes > 3){
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*rxBuffp = dp->DR;
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rxBuffp++;
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(i2cp->rxbytes)--;
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}
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else{
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_i2c_unhandled_case(i2cp);
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}
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break;
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default:
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_i2c_unhandled_case(i2cp);
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break;
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}
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}
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/**
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* @brief Main I2C interrupt handler.
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* @note Internal use only.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
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I2C_TypeDef *dp = i2cp->id_i2c;
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switch(i2c_get_event(i2cp)) {
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case I2C_EV5_MASTER_MODE_SELECT:
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i2cp->flags &= ~I2C_FLG_HEADER_SENT;
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dp->DR = i2cp->slave_addr1;
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break;
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case I2C_EV9_MASTER_ADDR_10BIT:
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if(i2cp->flags & I2C_FLG_MASTER_RECEIVER) {
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i2cp->slave_addr1 |= 0x01;
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i2cp->flags |= I2C_FLG_HEADER_SENT;
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}
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dp->DR = i2cp->slave_addr2;
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break;
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/**************************************************************************
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* Master Transmitter part
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*/
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case I2C_EV6_MASTER_TRA_MODE_SELECTED:
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if(i2cp->flags & I2C_FLG_HEADER_SENT){
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dp->CR1 |= I2C_CR1_START; /* re-send the start in 10-Bit address mode */
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break;
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}
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txBuffp = (uint8_t*)i2cp->txbuf; /* Initialize the transmit buffer pointer */
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i2cp->txbytes--;
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if(i2cp->txbytes == 0) { /* If no further data to be sent, disable the I2C ITBUF in order to not have a TxE interrupt */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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}
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dp->DR = *txBuffp; /* EV8_1 write the first data */
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txBuffp++;
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break;
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case I2C_EV8_MASTER_BYTE_TRANSMITTING:
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if(i2cp->txbytes > 0) {
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i2cp->txbytes--;
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if(i2cp->txbytes == 0) { /* If no further data to be sent, disable the ITBUF in order to not have a TxE interrupt */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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}
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dp->DR = *txBuffp;
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txBuffp++;
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}
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break;
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case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
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dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN; /* Disable ITEVT In order to not have again a BTF IT */
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if (i2cp->rxbytes == 0){ /* if nothing to read then generate stop */
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dp->CR1 |= I2C_CR1_STOP;
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_i2c_isr_code(i2cp, i2cp->id_slave_config); /* Portable I2C ISR code defined in the high level driver. */
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}
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else{ /* start reading operation */
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i2cp->id_i2c->CR1 |= I2C_CR1_START; /* send start bit */
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i2c_lld_master_transceive(i2cp);
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}
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break;
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/**************************************************************************
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* Master Receiver part
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*/
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case I2C_EV6_MASTER_REC_MODE_SELECTED:
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_i2c_ev6_master_rec_mode_selected(i2cp);
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rxBuffp = i2cp->rxbuf; /* Initialize receive buffer pointer */
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break;
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case I2C_EV7_MASTER_REC_BYTE_RECEIVED:
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if(i2cp->rxbytes > 3) {
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*rxBuffp = dp->DR; /* Read the data register */
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rxBuffp++;
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i2cp->rxbytes--;
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if(i2cp->rxbytes == 3){ /* Disable the ITBUF in order to have only the BTF interrupt */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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i2cp->flags |= I2C_FLG_3BTR;
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}
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}
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else if (i2cp->rxbytes == 3){ /* Disable the ITBUF in order to have only the BTF interrupt */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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i2cp->flags |= I2C_FLG_3BTR;
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}
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break;
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case I2C_EV7_MASTER_REC_BYTE_QUEUED:
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_i2c_ev7_master_rec_byte_qued(i2cp);
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break;
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default: /* only 1 byte must to be read to complete trasfer. Stop already sent to bus. */
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chDbgAssert((i2cp->rxbytes) == 1,
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"i2c_serve_event_interrupt(), #1",
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"more than 1 byte to be received");
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*rxBuffp = dp->DR; /* Read the data register */
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i2cp->rxbytes = 0;
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dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN; /* disable interrupts */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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_i2c_isr_code(i2cp, i2cp->id_slave_config); /* Portable I2C ISR code defined in the high level driver.*/
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break;
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}
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}
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#endif /* I2C_SUPPORTS_CALLBACKS */
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static void i2c_serve_error_interrupt(I2CDriver *i2cp) {
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static void i2c_serve_error_interrupt(I2CDriver *i2cp) {
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i2cflags_t flags;
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i2cflags_t flags;
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@ -447,28 +133,10 @@ static void i2c_serve_error_interrupt(I2CDriver *i2cp) {
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#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
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#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
|
||||||
/**
|
#error "Unrealized yet"
|
||||||
* @brief I2C1 event interrupt handler.
|
|
||||||
*/
|
|
||||||
#if I2C_SUPPORTS_CALLBACKS
|
|
||||||
CH_IRQ_HANDLER(VectorBC) {
|
|
||||||
|
|
||||||
CH_IRQ_PROLOGUE();
|
|
||||||
i2c_serve_event_interrupt(&I2CD1);
|
|
||||||
CH_IRQ_EPILOGUE();
|
|
||||||
}
|
|
||||||
#endif /* I2C_SUPPORTS_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @brief I2C1 error interrupt handler.
|
|
||||||
*/
|
|
||||||
CH_IRQ_HANDLER(VectorC0) {
|
|
||||||
|
|
||||||
CH_IRQ_PROLOGUE();
|
|
||||||
i2c_serve_error_interrupt(&I2CD1);
|
|
||||||
CH_IRQ_EPILOGUE();
|
|
||||||
}
|
|
||||||
#endif /* STM32_I2C_USE_I2C1 */
|
#endif /* STM32_I2C_USE_I2C1 */
|
||||||
|
|
||||||
|
|
||||||
#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
|
#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
|
||||||
/**
|
/**
|
||||||
* @brief I2C2 event interrupt handler.
|
* @brief I2C2 event interrupt handler.
|
||||||
|
|
@ -546,10 +214,10 @@ void i2c_lld_start(I2CDriver *i2cp) {
|
||||||
if (&I2CD2 == i2cp) {
|
if (&I2CD2 == i2cp) {
|
||||||
#if I2C_SUPPORTS_CALLBACKS
|
#if I2C_SUPPORTS_CALLBACKS
|
||||||
NVICEnableVector(I2C2_EV_IRQn,
|
NVICEnableVector(I2C2_EV_IRQn,
|
||||||
CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
|
CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
|
||||||
#endif /* I2C_SUPPORTS_CALLBACKS */
|
#endif /* I2C_SUPPORTS_CALLBACKS */
|
||||||
NVICEnableVector(I2C2_ER_IRQn,
|
NVICEnableVector(I2C2_ER_IRQn,
|
||||||
CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
|
CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
|
||||||
rccEnableI2C2(FALSE);
|
rccEnableI2C2(FALSE);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -566,7 +234,9 @@ void i2c_lld_reset(I2CDriver *i2cp){
|
||||||
chDbgCheck((i2cp->id_state == I2C_STOP)||(i2cp->id_state == I2C_READY),
|
chDbgCheck((i2cp->id_state == I2C_STOP)||(i2cp->id_state == I2C_READY),
|
||||||
"i2c_lld_reset: invalid state");
|
"i2c_lld_reset: invalid state");
|
||||||
|
|
||||||
|
/*TODO: Check what interface we must reset */
|
||||||
rccResetI2C1();
|
rccResetI2C1();
|
||||||
|
rccResetI2C2();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -717,6 +387,29 @@ void i2c_lld_stop(I2CDriver *i2cp) {
|
||||||
|
|
||||||
|
|
||||||
#if I2C_SUPPORTS_CALLBACKS
|
#if I2C_SUPPORTS_CALLBACKS
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Transmits data via the I2C bus as master.
|
||||||
|
*
|
||||||
|
* @param[in] i2cp pointer to the @p I2CDriver object
|
||||||
|
* @param[in] slave_addr Slave device address. Bits 0-9 contain slave
|
||||||
|
* device address. Bit 15 must be set to 1 if 10-bit
|
||||||
|
* addressing modes used. Otherwise keep it cleared.
|
||||||
|
* Bits 10-14 unused.
|
||||||
|
* @param[in] txbuf pointer to the transmit buffer
|
||||||
|
* @param[in] txbytes number of bytes to be transmitted
|
||||||
|
* @param[in] rxbuf pointer to the receive buffer
|
||||||
|
* @param[in] rxbytes number of bytes to be received
|
||||||
|
*/
|
||||||
|
void i2c_lld_master_transmit_dma(I2CDriver *i2cp, uint16_t slave_addr,
|
||||||
|
uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes) {
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Transmits data via the I2C bus as master.
|
* @brief Transmits data via the I2C bus as master.
|
||||||
*
|
*
|
||||||
|
|
|
||||||
|
|
@ -308,6 +308,9 @@ void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr,
|
||||||
uint8_t *rxbuf, size_t rxbytes);
|
uint8_t *rxbuf, size_t rxbytes);
|
||||||
void i2c_lld_master_transceive(I2CDriver *i2cp);
|
void i2c_lld_master_transceive(I2CDriver *i2cp);
|
||||||
|
|
||||||
|
void i2c_lld_master_transmit_dma(I2CDriver *i2cp, uint16_t slave_addr,
|
||||||
|
uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes);
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue