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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6440 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-11-11 12:14:43 +00:00
parent 24d3ce6003
commit 744250d0e2
30 changed files with 6900 additions and 408 deletions
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5
demos/rt/RT-STM32F429-DISCOVERY/.project
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@ -76,11 +76,6 @@
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures> </natures>
<linkedResources> <linkedResources>
<link>
<name>board</name>
<type>2</type>
<locationURI>CHIBIOS/boards/ST_STM32F429I_DISCOVERY</locationURI>
</link>
<link> <link>
<name>os</name> <name>os</name>
<type>2</type> <type>2</type>

80
demos/rt/RT-STM32F429-DISCOVERY/Makefile
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@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes USE_LINK_GC = yes
endif endif
# Enable this if you want link time optimizations (LTO)
ifeq ($(USE_LTO),)
USE_LTO = yes
endif
# If enabled, this option allows to compile the application in THUMB mode. # If enabled, this option allows to compile the application in THUMB mode.
ifeq ($(USE_THUMB),) ifeq ($(USE_THUMB),)
USE_THUMB = yes USE_THUMB = yes
@ -41,15 +46,21 @@ endif
# Architecture or project specific options # Architecture or project specific options
# #
# Enables the use of FPU on Cortex-M4. # Stack size to be allocated to the Cortex-M process stack. This stack is
# Enable this if you really want to use the STM FWLib. # the stack used by the main() thread.
ifeq ($(USE_FPU),) ifeq ($(USE_PROCESS_STACKSIZE),)
USE_FPU = no USE_PROCESS_STACKSIZE = 0x400
endif endif
# Enable this if you really want to use the STM FWLib. # Stack size to the allocated to the Cortex-M main/exceptions stack. This
ifeq ($(USE_FWLIB),) # stack is used for processing interrupts and exceptions.
USE_FWLIB = no ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
USE_EXCEPTIONS_STACKSIZE = 0x400
endif
# Enables the use of FPU on Cortex-M4.
ifeq ($(USE_FPU),)
USE_FPU = no
endif endif
# #
@ -64,12 +75,13 @@ endif
PROJECT = ch PROJECT = ch
# Imported source files and paths # Imported source files and paths
CHIBIOS = ../.. CHIBIOS = ../../..
include $(CHIBIOS)/boards/ST_STM32F429I_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk include $(CHIBIOS)/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk
include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/os/hal/ports/STM32F4xx/platform.mk
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/rt/osal/osal.mk
include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk
include $(CHIBIOS)/test/test.mk include $(CHIBIOS)/test/test.mk
# Define linker script file here # Define linker script file here
@ -81,6 +93,7 @@ CSRC = $(PORTSRC) \
$(KERNSRC) \ $(KERNSRC) \
$(TESTSRC) \ $(TESTSRC) \
$(HALSRC) \ $(HALSRC) \
$(OSALSRC) \
$(PLATFORMSRC) \ $(PLATFORMSRC) \
$(BOARDSRC) \ $(BOARDSRC) \
$(CHIBIOS)/os/various/shell.c \ $(CHIBIOS)/os/various/shell.c \
@ -115,7 +128,7 @@ TCPPSRC =
ASMSRC = $(PORTASM) ASMSRC = $(PORTASM)
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \ $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \
$(CHIBIOS)/os/various/devices_lib/accel \ $(CHIBIOS)/os/various/devices_lib/accel \
$(CHIBIOS)/os/various $(CHIBIOS)/os/various
@ -141,6 +154,7 @@ LD = $(TRGT)gcc
CP = $(TRGT)objcopy CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp AS = $(TRGT)gcc -x assembler-with-cpp
OD = $(TRGT)objdump OD = $(TRGT)objdump
SZ = $(TRGT)size
HEX = $(CP) -O ihex HEX = $(CP) -O ihex
BIN = $(CP) -O binary BIN = $(CP) -O binary
@ -160,29 +174,6 @@ CPPWARN = -Wall -Wextra
# Compiler settings # Compiler settings
############################################################################## ##############################################################################
##############################################################################
# Start of default section
#
# List all default C defines here, like -D_DEBUG=1
DDEFS =
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =
# List all default directories to look for include files here
DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
DLIBS =
#
# End of default section
##############################################################################
############################################################################## ##############################################################################
# Start of user section # Start of user section
# #
@ -206,18 +197,5 @@ ULIBS =
# End of user defines # End of user defines
############################################################################## ##############################################################################
ifeq ($(USE_FPU),yes) RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant include $(RULESPATH)/rules.mk
DDEFS += -DCORTEX_USE_FPU=TRUE
else
DDEFS += -DCORTEX_USE_FPU=FALSE
endif
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
INCDIR += $(STM32INC)
USE_OPT += -DUSE_STDPERIPH_DRIVER
endif
include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk

292
demos/rt/RT-STM32F429-DISCOVERY/chconf.h
View File

@ -30,19 +30,49 @@
/*===========================================================================*/ /*===========================================================================*/
/** /**
* @name Kernel parameters and options * @name System timers settings
* @{ * @{
*/ */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
*/
#define CH_CFG_ST_RESOLUTION 32
/** /**
* @brief System tick frequency. * @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This * @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit. * setting also defines the system tick time unit.
*/ */
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #define CH_CFG_ST_FREQUENCY 10000
#define CH_FREQUENCY 1000
#endif /**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#define CH_CFG_ST_TIMEDELTA 2
/**
* @brief Realtime Counter frequency.
* @details Frequency of the system counter used for realtime delays and
* measurements.
*/
#define CH_CFG_RTC_FREQUENCY 168000000
/** @} */
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/** /**
* @brief Round robin interval. * @brief Round robin interval.
@ -51,13 +81,12 @@
* disables the preemption for threads with equal priority and the * disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority * round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive. * threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact * @note Disabling the round robin preemption makes the kernel more compact
* and generally faster. * and generally faster.
* @note The round robin preemption is not supported in tickless mode and
* must be set to zero in that case.
*/ */
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_CFG_TIME_QUANTUM 0
#define CH_TIME_QUANTUM 20
#endif
/** /**
* @brief Managed RAM size. * @brief Managed RAM size.
@ -68,28 +97,17 @@
* *
* @note In order to let the OS manage the whole RAM the linker script must * @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols. * provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE. * @note Requires @p CH_CFG_USE_MEMCORE.
*/ */
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_CFG_MEMCORE_SIZE 0
#define CH_MEMCORE_SIZE 0
#endif
/** /**
* @brief Idle thread automatic spawn suppression. * @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit() * @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has * does not spawn the idle thread. The application @p main()
* then the responsibility to do one of the following: * function becomes the idle thread and must implement an
* - Spawn a custom idle thread at priority @p IDLEPRIO. * infinite loop. */
* - Change the main() thread priority to @p IDLEPRIO then enter #define CH_CFG_NO_IDLE_THREAD FALSE
* an endless loop. In this scenario the @p main() thread acts as
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif
/** @} */ /** @} */
@ -108,9 +126,7 @@
* @note This is not related to the compiler optimization options. * @note This is not related to the compiler optimization options.
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_CFG_OPTIMIZE_SPEED TRUE
#define CH_OPTIMIZE_SPEED TRUE
#endif
/** @} */ /** @} */
@ -121,15 +137,22 @@
*/ */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief Time Measurement APIs.
* @details If enabled then the time measurement APIs are included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_TM TRUE
/** /**
* @brief Threads registry APIs. * @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel. * @details If enabled then the registry APIs are included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_CFG_USE_REGISTRY TRUE
#define CH_USE_REGISTRY TRUE
#endif
/** /**
* @brief Threads synchronization APIs. * @brief Threads synchronization APIs.
@ -138,9 +161,7 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_CFG_USE_WAITEXIT TRUE
#define CH_USE_WAITEXIT TRUE
#endif
/** /**
* @brief Semaphores APIs. * @brief Semaphores APIs.
@ -148,33 +169,18 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_CFG_USE_SEMAPHORES TRUE
#define CH_USE_SEMAPHORES TRUE
#endif
/** /**
* @brief Semaphores queuing mode. * @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by * @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order. * priority rather than in FIFO order.
* *
* @note The default is @p FALSE. Enable this if you have special requirements. * @note The default is @p FALSE. Enable this if you have special
* @note Requires @p CH_USE_SEMAPHORES. * requirements.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/ */
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
#define CH_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif
/** /**
* @brief Mutexes APIs. * @brief Mutexes APIs.
@ -182,9 +188,7 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_CFG_USE_MUTEXES TRUE
#define CH_USE_MUTEXES TRUE
#endif
/** /**
* @brief Conditional Variables APIs. * @brief Conditional Variables APIs.
@ -192,11 +196,9 @@
* in the kernel. * in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES. * @note Requires @p CH_CFG_USE_MUTEXES.
*/ */
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_CFG_USE_CONDVARS TRUE
#define CH_USE_CONDVARS TRUE
#endif
/** /**
* @brief Conditional Variables APIs with timeout. * @brief Conditional Variables APIs with timeout.
@ -204,11 +206,9 @@
* specification are included in the kernel. * specification are included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS. * @note Requires @p CH_CFG_USE_CONDVARS.
*/ */
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
#define CH_USE_CONDVARS_TIMEOUT TRUE
#endif
/** /**
* @brief Events Flags APIs. * @brief Events Flags APIs.
@ -216,9 +216,7 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_CFG_USE_EVENTS TRUE
#define CH_USE_EVENTS TRUE
#endif
/** /**
* @brief Events Flags APIs with timeout. * @brief Events Flags APIs with timeout.
@ -226,11 +224,9 @@
* are included in the kernel. * are included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS. * @note Requires @p CH_CFG_USE_EVENTS.
*/ */
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_CFG_USE_EVENTS_TIMEOUT TRUE
#define CH_USE_EVENTS_TIMEOUT TRUE
#endif
/** /**
* @brief Synchronous Messages APIs. * @brief Synchronous Messages APIs.
@ -239,21 +235,18 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_CFG_USE_MESSAGES TRUE
#define CH_USE_MESSAGES TRUE
#endif
/** /**
* @brief Synchronous Messages queuing mode. * @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in * @details If enabled then messages are served by priority rather than in
* FIFO order. * FIFO order.
* *
* @note The default is @p FALSE. Enable this if you have special requirements. * @note The default is @p FALSE. Enable this if you have special
* @note Requires @p CH_USE_MESSAGES. * requirements.
* @note Requires @p CH_CFG_USE_MESSAGES.
*/ */
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_CFG_USE_MESSAGES_PRIORITY FALSE
#define CH_USE_MESSAGES_PRIORITY FALSE
#endif
/** /**
* @brief Mailboxes APIs. * @brief Mailboxes APIs.
@ -261,11 +254,9 @@
* included in the kernel. * included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES. * @note Requires @p CH_CFG_USE_SEMAPHORES.
*/ */
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_CFG_USE_MAILBOXES TRUE
#define CH_USE_MAILBOXES TRUE
#endif
/** /**
* @brief I/O Queues APIs. * @brief I/O Queues APIs.
@ -273,9 +264,7 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_CFG_USE_QUEUES TRUE
#define CH_USE_QUEUES TRUE
#endif
/** /**
* @brief Core Memory Manager APIs. * @brief Core Memory Manager APIs.
@ -284,9 +273,7 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_CFG_USE_MEMCORE TRUE
#define CH_USE_MEMCORE TRUE
#endif
/** /**
* @brief Heap Allocator APIs. * @brief Heap Allocator APIs.
@ -294,27 +281,11 @@
* in the kernel. * in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
* @p CH_USE_SEMAPHORES. * @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended. * @note Mutexes are recommended.
*/ */
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_CFG_USE_HEAP TRUE
#define CH_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif
/** /**
* @brief Memory Pools Allocator APIs. * @brief Memory Pools Allocator APIs.
@ -323,9 +294,7 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_CFG_USE_MEMPOOLS TRUE
#define CH_USE_MEMPOOLS TRUE
#endif
/** /**
* @brief Dynamic Threads APIs. * @brief Dynamic Threads APIs.
@ -333,12 +302,10 @@
* in the kernel. * in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT. * @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/ */
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_CFG_USE_DYNAMIC TRUE
#define CH_USE_DYNAMIC TRUE
#endif
/** @} */ /** @} */
@ -349,6 +316,13 @@
*/ */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief Debug option, kernel statistics.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_STATISTICS FALSE
/** /**
* @brief Debug option, system state check. * @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked * @details If enabled the correct call protocol for system APIs is checked
@ -356,9 +330,7 @@
* *
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) #define CH_DBG_SYSTEM_STATE_CHECK FALSE
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/** /**
* @brief Debug option, parameters checks. * @brief Debug option, parameters checks.
@ -367,9 +339,7 @@
* *
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/** /**
* @brief Debug option, consistency checks. * @brief Debug option, consistency checks.
@ -379,9 +349,7 @@
* *
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/** /**
* @brief Debug option, trace buffer. * @brief Debug option, trace buffer.
@ -390,9 +358,7 @@
* *
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE
#define CH_DBG_ENABLE_TRACE FALSE
#endif
/** /**
* @brief Debug option, stack checks. * @brief Debug option, stack checks.
@ -404,9 +370,7 @@
* @note The default failure mode is to halt the system with the global * @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL. * @p panic_msg variable set to @p NULL.
*/ */
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/** /**
* @brief Debug option, stacks initialization. * @brief Debug option, stacks initialization.
@ -416,22 +380,18 @@
* *
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE
#define CH_DBG_FILL_THREADS FALSE
#endif
/** /**
* @brief Debug option, threads profiling. * @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that * @details If enabled then a field is added to the @p thread_t structure that
* counts the system ticks occurred while executing the thread. * counts the system ticks occurred while executing the thread.
* *
* @note The default is @p TRUE. * @note The default is @p FALSE.
* @note This debug option is defaulted to TRUE because it is required by * @note This debug option is not currently compatible with the
* some test cases into the test suite. * tickless mode.
*/ */
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING FALSE
#define CH_DBG_THREADS_PROFILING TRUE
#endif
/** @} */ /** @} */
@ -444,12 +404,10 @@
/** /**
* @brief Threads descriptor structure extension. * @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure. * @details User fields added to the end of the @p thread_t structure.
*/ */
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define CH_CFG_THREAD_EXTRA_FIELDS \
#define THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/ /* Add threads custom fields here.*/
#endif
/** /**
* @brief Threads initialization hook. * @brief Threads initialization hook.
@ -458,11 +416,9 @@
* @note It is invoked from within @p chThdInit() and implicitly from all * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs. * the threads creation APIs.
*/ */
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) #define CH_CFG_THREAD_INIT_HOOK(tp) { \
#define THREAD_EXT_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \ /* Add threads initialization code here.*/ \
} }
#endif
/** /**
* @brief Threads finalization hook. * @brief Threads finalization hook.
@ -472,53 +428,61 @@
* @note It is also invoked when the threads simply return in order to * @note It is also invoked when the threads simply return in order to
* terminate. * terminate.
*/ */
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) #define CH_CFG_THREAD_EXIT_HOOK(tp) { \
#define THREAD_EXT_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \ /* Add threads finalization code here.*/ \
} }
#endif
/** /**
* @brief Context switch hook. * @brief Context switch hook.
* @details This hook is invoked just before switching between threads. * @details This hook is invoked just before switching between threads.
*/ */
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) #define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \ /* System halt code here.*/ \
} }
#endif
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#define CH_CFG_IDLE_ENTER_HOOK() { \
}
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#define CH_CFG_IDLE_LEAVE_HOOK() { \
}
/** /**
* @brief Idle Loop hook. * @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop. * @details This hook is continuously invoked by the idle thread loop.
*/ */
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define CH_CFG_IDLE_LOOP_HOOK() { \
#define IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \ /* Idle loop code here.*/ \
} }
#endif
/** /**
* @brief System tick event hook. * @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately * @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue. * after processing the virtual timers queue.
*/ */
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) #define CH_CFG_SYSTEM_TICK_HOOK() { \
#define SYSTEM_TICK_EVENT_HOOK() { \
/* System tick event code here.*/ \ /* System tick event code here.*/ \
} }
#endif
/** /**
* @brief System halt hook. * @brief System halt hook.
* @details This hook is invoked in case to a system halting error before * @details This hook is invoked in case to a system halting error before
* the system is halted. * the system is halted.
*/ */
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) #define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
#define SYSTEM_HALT_HOOK() { \
/* System halt code here.*/ \ /* System halt code here.*/ \
} }
#endif
/** @} */ /** @} */

7
demos/rt/RT-STM32F429-DISCOVERY/halconf.h
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@ -30,13 +30,6 @@
#include "mcuconf.h" #include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM FALSE
#endif
/** /**
* @brief Enables the PAL subsystem. * @brief Enables the PAL subsystem.
*/ */

24
demos/rt/RT-STM32F429-DISCOVERY/main.c
View File

@ -26,7 +26,7 @@
/* /*
* Red LED blinker thread, times are in milliseconds. * Red LED blinker thread, times are in milliseconds.
*/ */
static WORKING_AREA(waThread1, 128); static THD_WORKING_AREA(waThread1, 128);
static msg_t Thread1(void *arg) { static msg_t Thread1(void *arg) {
(void)arg; (void)arg;
@ -42,7 +42,7 @@ static msg_t Thread1(void *arg) {
/* /*
* Green LED blinker thread, times are in milliseconds. * Green LED blinker thread, times are in milliseconds.
*/ */
static WORKING_AREA(waThread2, 128); static THD_WORKING_AREA(waThread2, 128);
static msg_t Thread2(void *arg) { static msg_t Thread2(void *arg) {
(void)arg; (void)arg;
@ -62,8 +62,8 @@ static msg_t Thread2(void *arg) {
/* Virtual serial port over USB.*/ /* Virtual serial port over USB.*/
SerialUSBDriver SDU1; SerialUSBDriver SDU1;
#define SHELL_WA_SIZE THD_WA_SIZE(2048) #define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048)
#define TEST_WA_SIZE THD_WA_SIZE(256) #define TEST_WA_SIZE THD_WORKING_AREA_SIZE(256)
static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) {
size_t n, size; size_t n, size;
@ -80,8 +80,8 @@ static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) {
} }
static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) {
static const char *states[] = {THD_STATE_NAMES}; static const char *states[] = {CH_STATE_NAMES};
Thread *tp; thread_t *tp;
(void)argv; (void)argv;
if (argc > 0) { if (argc > 0) {
@ -91,23 +91,23 @@ static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) {
chprintf(chp, " addr stack prio refs state time\r\n"); chprintf(chp, " addr stack prio refs state time\r\n");
tp = chRegFirstThread(); tp = chRegFirstThread();
do { do {
chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s\r\n",
(uint32_t)tp, (uint32_t)tp->p_ctx.r13, (uint32_t)tp, (uint32_t)tp->p_ctx.r13,
(uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1),
states[tp->p_state], (uint32_t)tp->p_time); states[tp->p_state]);
tp = chRegNextThread(tp); tp = chRegNextThread(tp);
} while (tp != NULL); } while (tp != NULL);
} }
static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) {
Thread *tp; thread_t *tp;
(void)argv; (void)argv;
if (argc > 0) { if (argc > 0) {
chprintf(chp, "Usage: test\r\n"); chprintf(chp, "Usage: test\r\n");
return; return;
} }
tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriorityX(),
TestThread, chp); TestThread, chp);
if (tp == NULL) { if (tp == NULL) {
chprintf(chp, "out of memory\r\n"); chprintf(chp, "out of memory\r\n");
@ -136,7 +136,7 @@ static const ShellConfig shell_cfg1 = {
* Application entry point. * Application entry point.
*/ */
int main(void) { int main(void) {
Thread *shelltp = NULL; thread_t *shelltp = NULL;
/* /*
* System initializations. * System initializations.
@ -190,7 +190,7 @@ int main(void) {
} }
else { else {
/* If the previous shell exited.*/ /* If the previous shell exited.*/
if (chThdTerminated(shelltp)) { if (chThdTerminatedX(shelltp)) {
/* Recovers memory of the previous shell.*/ /* Recovers memory of the previous shell.*/
chThdRelease(shelltp); chThdRelease(shelltp);
shelltp = NULL; shelltp = NULL;

4
demos/rt/RT-STM32F429-DISCOVERY/usbcfg.c
View File

@ -270,7 +270,7 @@ static void usb_event(USBDriver *usbp, usbevent_t event) {
case USB_EVENT_ADDRESS: case USB_EVENT_ADDRESS:
return; return;
case USB_EVENT_CONFIGURED: case USB_EVENT_CONFIGURED:
chSysLockFromIsr(); chSysLockFromISR();
/* Enables the endpoints specified into the configuration. /* Enables the endpoints specified into the configuration.
Note, this callback is invoked from an ISR so I-Class functions Note, this callback is invoked from an ISR so I-Class functions
@ -281,7 +281,7 @@ static void usb_event(USBDriver *usbp, usbevent_t event) {
/* Resetting the state of the CDC subsystem.*/ /* Resetting the state of the CDC subsystem.*/
sduConfigureHookI(&SDU1); sduConfigureHookI(&SDU1);
chSysUnlockFromIsr(); chSysUnlockFromISR();
return; return;
case USB_EVENT_SUSPEND: case USB_EVENT_SUSPEND:
return; return;

31
os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld Normal file
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@ -0,0 +1,31 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* ST32F429xI memory setup.
*/
MEMORY
{
flash : org = 0x08000000, len = 2M
ram : org = 0x20000000, len = 192k
ccmram : org = 0x10000000, len = 64k
}
INCLUDE rules.ld

2111
os/ext/CMSIS/ST/stm32f4xx.h
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4
os/ext/CMSIS/ST/system_stm32f4xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f4xx.h * @file system_stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.1.0 * @version V1.2.1
* @date 11-January-2013 * @date 19-September-2013
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention

4
os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.h
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@ -41,9 +41,9 @@
#define STM32_VDD 300 #define STM32_VDD 300
/* /*
* MCU type as defined in the ST header file stm32f4xx.h. * MCU type as defined in the ST header.
*/ */
#define STM32F4XX #define STM32F40_41xxx
/* /*
* IO pins assignments. * IO pins assignments.

4
os/hal/boards/OLIMEX_STM32_E407/board.h
View File

@ -52,9 +52,9 @@
#define STM32_VDD 330 #define STM32_VDD 330
/* /*
* MCU type as defined in the ST header file stm32f4xx.h. * MCU type as defined in the ST header.
*/ */
#define STM32F4XX #define STM32F401xx
/* /*
* IO pins assignments. * IO pins assignments.

1
os/hal/boards/OLIMEX_STM32_E407/cfg/board.chcfg
View File

@ -22,6 +22,7 @@
<identifier>MII_KS8721_ID</identifier> <identifier>MII_KS8721_ID</identifier>
<bus_type>RMII</bus_type> <bus_type>RMII</bus_type>
</ethernet_phy> </ethernet_phy>
<subtype>STM32F40_41xxx</subtype>
<clocks HSEFrequency="12000000" HSEBypass="false" LSEFrequency="32768" <clocks HSEFrequency="12000000" HSEBypass="false" LSEFrequency="32768"
VDD="330" /> VDD="330" />
<ports> <ports>

107
os/hal/boards/OLIMEX_STM32_H407/board.c Normal file
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@ -0,0 +1,107 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config =
{
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
};
#endif
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
static bool_t last_status = FALSE;
if (blkIsTransferring(sdcp))
return last_status;
return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3);
}
/**
* @brief SDC card write protection detection.
*/
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
return FALSE;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
*/
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return TRUE;
}
/**
* @brief MMC_SPI card write protection detection.
*/
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return FALSE;
}
#endif
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
}

1301
os/hal/boards/OLIMEX_STM32_H407/board.h Normal file
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5
os/hal/boards/OLIMEX_STM32_H407/board.mk Normal file
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@ -0,0 +1,5 @@
# List of all the board related files.
BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_H407/board.c
# Required include directories
BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_H407

336
os/hal/boards/OLIMEX_STM32_H407/cfg/board.chcfg Normal file
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@ -0,0 +1,336 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- STM32F4xx board Template -->
<board xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f4xx_board.xsd">
<configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
<output_path>..</output_path>
</configuration_settings>
<board_name>Olimex STM32-H407</board_name>
<board_id>OLIMEX_STM32_H407</board_id>
<board_functions>
<sdc_lld_is_card_inserted><![CDATA[ static bool_t last_status = FALSE;
if (blkIsTransferring(sdcp))
return last_status;
return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3);]]></sdc_lld_is_card_inserted>
<sdc_lld_is_write_protected>
<![CDATA[ (void)sdcp;
return FALSE;]]></sdc_lld_is_write_protected>
</board_functions>
<ethernet_phy>
<identifier>MII_KS8721_ID</identifier>
<bus_type>RMII</bus_type>
</ethernet_phy>
<subtype>STM32F40_41xxx</subtype>
<clocks HSEFrequency="12000000" HSEBypass="false" LSEFrequency="32768"
VDD="330" />
<ports>
<GPIOA>
<pin0 ID="BUTTON_WKUP" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Input" Alternate="0" />
<pin1 ID="ETH_RMII_REF_CLK" Type="PushPull" Speed="Maximum"
Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
<pin2 ID="ETH_RMII_MDIO" Type="PushPull" Speed="Maximum"
Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
<pin3 ID="ETH_RMII_MDINT" Type="PushPull" Speed="Maximum"
Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
<pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin7 ID="ETH_RMII_CRS_DV" Type="PushPull" Speed="Maximum"
Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
<pin8 ID="USB_HS_BUSON" Type="PushPull" Speed="Maximum"
Resistor="Floating" Level="High" Mode="Output" Alternate="0" />
<pin9 ID="OTG_FS_VBUS" Type="PushPull" Speed="Maximum" Resistor="PullDown"
Level="High" Mode="Input" Alternate="0" />
<pin10 ID="OTG_FS_ID" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="10" />
<pin11 ID="OTG_FS_DM" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="10" />
<pin12 ID="OTG_FS_DP" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="10" />
<pin13 ID="JTAG_TMS" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="0" />
<pin14 ID="JTAG_TCK" Type="PushPull" Speed="Maximum" Resistor="PullDown"
Level="High" Mode="Alternate" Alternate="0" />
<pin15 ID="JTAG_TDI" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="0" />
</GPIOA>
<GPIOB>
<pin0 ID="USB_FS_BUSON" Type="PushPull" Speed="Maximum"
Resistor="Floating" Level="High" Mode="Output" Alternate="0" />
<pin1 ID="USB_HS_FAULT" Type="PushPull" Speed="Maximum"
Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
<pin2 ID="BOOT1" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Input" Alternate="0" />
<pin3 ID="JTAG_TDO" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="0" />
<pin4 ID="JTAG_TRST" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="0" />
<pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin8 ID="I2C1_SCL" Type="OpenDrain" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="4" />
<pin9 ID="I2C1_SDA" Type="OpenDrain" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="4" />
<pin10 ID="SPI2_SCK" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="5" />
<pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin12 ID="OTG_HS_ID" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="12" />
<pin13 ID="OTG_HS_VBUS" Type="PushPull" Speed="Maximum"
Resistor="PullDown" Level="High" Mode="Input" Alternate="0" />
<pin14 ID="OTG_HS_DM" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="12" />
<pin15 ID="OTG_HS_DP" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="12" />
</GPIOB>
<GPIOC>
<pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin1 ID="ETH_RMII_MDC" Type="PushPull" Speed="Maximum"
Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
<pin2 ID="SPI2_MISO" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="5" />
<pin3 ID="SPI2_MOSI" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="5" />
<pin4 ID="ETH_RMII_RXD0" Type="PushPull" Speed="Maximum"
Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
<pin5 ID="ETH_RMII_RXD1" Type="PushPull" Speed="Maximum"
Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
<pin6 ID="USART6_TX" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="8" />
<pin7 ID="USART6_RX" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="8" />
<pin8 ID="SD_D0" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="12" />
<pin9 ID="SD_D1" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="12" />
<pin10 ID="SD_D2" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="12" />
<pin11 ID="SD_D3" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="12" />
<pin12 ID="SD_CLK" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="12" />
<pin13 ID="LED" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Output" Alternate="0" />
<pin14 ID="OSC32_IN" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Input" Alternate="0" />
<pin15 ID="OSC32_OUT" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Input" Alternate="0" />
</GPIOC>
<GPIOD>
<pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin2 ID="SD_CMD" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Alternate" Alternate="12" />
<pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
</GPIOD>
<GPIOE>
<pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
</GPIOE>
<GPIOF>
<pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin11 ID="USB_FS_FAULT" Type="PushPull" Speed="Maximum"
Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
<pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
</GPIOF>
<GPIOG>
<pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin10 ID="SPI2_CS" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Output" Alternate="0" />
<pin11 ID="ETH_RMII_TXEN" Type="PushPull" Speed="Maximum"
Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
<pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin13 ID="ETH_RMII_TXD0" Type="PushPull" Speed="Maximum"
Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
<pin14 ID="ETH_RMII_TXD1" Type="PushPull" Speed="Maximum"
Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
<pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
</GPIOG>
<GPIOH>
<pin0 ID="OSC_IN" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Input" Alternate="0"></pin0>
<pin1 ID="OSC_OUT" Type="PushPull" Speed="Maximum" Resistor="Floating"
Level="High" Mode="Input" Alternate="0" />
<pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
</GPIOH>
<GPIOI>
<pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
</GPIOI>
</ports>
</board>

4
os/hal/boards/OLIMEX_STM32_P407/board.h
View File

@ -49,9 +49,9 @@
#define STM32_VDD 330 #define STM32_VDD 330
/* /*
* MCU type as defined in the ST header file stm32f4xx.h. * MCU type as defined in the ST header.
*/ */
#define STM32F4XX #define STM32F40_41xxx
/* /*
* IO pins assignments. * IO pins assignments.

107
os/hal/boards/ST_STM32F429I_DISCOVERY/board.c Normal file
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@ -0,0 +1,107 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config =
{
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
};
#endif
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return TRUE;
}
/**
* @brief SDC card write protection detection.
*/
bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return FALSE;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
*/
bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return TRUE;
}
/**
* @brief MMC_SPI card write protection detection.
*/
bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return FALSE;
}
#endif
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
}

1297
os/hal/boards/ST_STM32F429I_DISCOVERY/board.h Normal file
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5
os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk Normal file
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@ -0,0 +1,5 @@
# List of all the board related files.
BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32F429I_DISCOVERY/board.c
# Required include directories
BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32F429I_DISCOVERY

1192
os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg Normal file
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4
os/hal/boards/ST_STM32F4_DISCOVERY/board.h
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@ -48,9 +48,9 @@
#define STM32_VDD 300 #define STM32_VDD 300
/* /*
* MCU type as defined in the ST header file stm32f4xx.h. * MCU type as defined in the ST header.
*/ */
#define STM32F40XX #define STM32F40_41xxx
/* /*
* IO pins assignments. * IO pins assignments.

8
os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg
View File

@ -10,7 +10,13 @@
<board_name>STMicroelectronics STM32F4-Discovery</board_name> <board_name>STMicroelectronics STM32F4-Discovery</board_name>
<board_id>ST_STM32F4_DISCOVERY</board_id> <board_id>ST_STM32F4_DISCOVERY</board_id>
<board_functions></board_functions> <board_functions></board_functions>
<clocks HSEFrequency="8000000" HSEBypass="false" LSEFrequency="0" VDD="300" /> <subtype>STM32F40_41xxx</subtype>
<clocks
HSEFrequency="8000000"
HSEBypass="false"
LSEFrequency="0"
LSEBypass="false"
VDD="300" />
<ports> <ports>
<GPIOA> <GPIOA>
<pin0 <pin0

4
os/hal/ports/STM32/OTGv1/usb_lld.c
View File

@ -112,14 +112,14 @@ static const stm32_otg_params_t hsparams = {
static void otg_core_reset(USBDriver *usbp) { static void otg_core_reset(USBDriver *usbp) {
stm32_otg_t *otgp = usbp->otg; stm32_otg_t *otgp = usbp->otg;
halPolledDelay(32); osalSysPolledDelayX(32);
/* Core reset and delay of at least 3 PHY cycles.*/ /* Core reset and delay of at least 3 PHY cycles.*/
otgp->GRSTCTL = GRSTCTL_CSRST; otgp->GRSTCTL = GRSTCTL_CSRST;
while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0) while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0)
; ;
halPolledDelay(12); osalSysPolledDelayX(12);
/* Wait AHB idle condition.*/ /* Wait AHB idle condition.*/
while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0)

4
os/hal/ports/STM32F0xx/hal_lld.c
View File

@ -61,10 +61,10 @@ static void hal_lld_backup_domain_init(void) {
#if STM32_LSE_ENABLED #if STM32_LSE_ENABLED
#if defined(STM32_LSE_BYPASS) #if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/ /* LSE Bypass.*/
RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else #else
/* No LSE Bypass.*/ /* No LSE Bypass.*/
RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON; RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
#endif #endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */ ; /* Waits until LSE is stable. */

4
os/hal/ports/STM32F30x/hal_lld.c
View File

@ -61,10 +61,10 @@ static void hal_lld_backup_domain_init(void) {
#if STM32_LSE_ENABLED #if STM32_LSE_ENABLED
#if defined(STM32_LSE_BYPASS) #if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/ /* LSE Bypass.*/
RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else #else
/* No LSE Bypass.*/ /* No LSE Bypass.*/
RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON; RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
#endif #endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */ ; /* Waits until LSE is stable. */

4
os/hal/ports/STM32F37x/hal_lld.c
View File

@ -61,10 +61,10 @@ static void hal_lld_backup_domain_init(void) {
#if STM32_LSE_ENABLED #if STM32_LSE_ENABLED
#if defined(STM32_LSE_BYPASS) #if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/ /* LSE Bypass.*/
RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else #else
/* No LSE Bypass.*/ /* No LSE Bypass.*/
RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON; RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
#endif #endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */ ; /* Waits until LSE is stable. */

55
os/hal/ports/STM32F4xx/hal_lld.c
View File

@ -22,8 +22,6 @@
* @{ * @{
*/ */
/* TODO: LSEBYP like in F3.*/
#include "hal.h" #include "hal.h"
/*===========================================================================*/ /*===========================================================================*/
@ -60,7 +58,13 @@ static void hal_lld_backup_domain_init(void) {
} }
#if STM32_LSE_ENABLED #if STM32_LSE_ENABLED
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->BDCR |= RCC_BDCR_LSEON; RCC->BDCR |= RCC_BDCR_LSEON;
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */ ; /* Waits until LSE is stable. */
#endif #endif
@ -142,17 +146,19 @@ void stm32_clock_init(void) {
/* PWR initialization.*/ /* PWR initialization.*/
#if defined(STM32F4XX) || defined(__DOXYGEN__) #if defined(STM32F4XX) || defined(__DOXYGEN__)
PWR->CR = STM32_VOS; PWR->CR = STM32_VOS;
while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
; /* Waits until power regulator is stable. */
#else #else
PWR->CR = 0; PWR->CR = 0;
#endif #endif
/* Initial clocks setup and wait for HSI stabilization, the MSI clock is /* HSI setup, it enforces the reset situation in order to handle possible
always enabled because it is the fallback clock when PLL the fails.*/ problems with JTAG probes and re-initializations.*/
RCC->CR |= RCC_CR_HSION; RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
while ((RCC->CR & RCC_CR_HSIRDY) == 0) while (!(RCC->CR & RCC_CR_HSIRDY))
; /* Waits until HSI is stable. */ ; /* Wait until HSI is stable. */
RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
RCC->CFGR = 0; /* CFGR reset value. */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
; /* Waits until HSI is selected. */
#if STM32_HSE_ENABLED #if STM32_HSE_ENABLED
/* HSE activation.*/ /* HSE activation.*/
@ -179,21 +185,42 @@ void stm32_clock_init(void) {
RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN | RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
STM32_PLLM; STM32_PLLM;
RCC->CR |= RCC_CR_PLLON; RCC->CR |= RCC_CR_PLLON;
/* Synchronization with voltage regulator stabilization.*/
#if defined(STM32F4XX)
while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
; /* Waits until power regulator is stable. */
#if STM32_OVERDRIVE_REQUIRED
/* Overdrive activation performed after activating the PLL in order to save
time as recommended in RM in "Entering Over-drive mode" paragraph.*/
PWR->CR |= PWR_CR_ODEN;
while (!(PWR->CSR & PWR_CSR_ODRDY))
;
PWR->CR |= PWR_CR_ODSWEN;
while (!(PWR->CSR & PWR_CSR_ODSWRDY))
;
#endif /* STM32_OVERDRIVE_REQUIRED */
#endif /* defined(STM32F4XX) */
/* Waiting for PLL lock.*/
while (!(RCC->CR & RCC_CR_PLLRDY)) while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL is stable. */ ;
#endif #endif /* STM32_OVERDRIVE_REQUIRED */
#if STM32_ACTIVATE_PLLI2S #if STM32_ACTIVATE_PLLI2S
/* PLLI2S activation.*/ /* PLLI2S activation.*/
RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN; RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN;
RCC->CR |= RCC_CR_PLLI2SON; RCC->CR |= RCC_CR_PLLI2SON;
/* Waiting for PLL lock.*/
while (!(RCC->CR & RCC_CR_PLLI2SRDY)) while (!(RCC->CR & RCC_CR_PLLI2SRDY))
; /* Waits until PLLI2S is stable. */ ;
#endif #endif
/* Other clock-related settings (dividers, MCO etc).*/ /* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* Flash setup.*/ /* Flash setup.*/
#if defined(STM32_USE_REVISION_A_FIX) #if defined(STM32_USE_REVISION_A_FIX)

300
os/hal/ports/STM32F4xx/hal_lld.h
View File

@ -20,14 +20,17 @@
* @pre This module requires the following macros to be defined in the * @pre This module requires the following macros to be defined in the
* @p board.h file: * @p board.h file:
* - STM32_LSECLK. * - STM32_LSECLK.
* - STM32_LSE_BYPASS (optionally).
* - STM32_HSECLK. * - STM32_HSECLK.
* - STM32_HSE_BYPASS (optionally). * - STM32_HSE_BYPASS (optionally).
* - STM32_VDD (as hundredths of Volt). * - STM32_VDD (as hundredths of Volt).
* . * .
* One of the following macros must also be defined: * One of the following macros must also be defined:
* - STM32F2XX for High-performance STM32 F-2 devices. * - STM32F2XX for High-performance STM32 F-2 devices.
* - STM32F40XX for High-performance STM32 F-4 devices. * - STM32F401xx for High-performance STM32 F-4 devices.
* - STM32F42XX for High-performance STM32 F-4 devices. * - STM32F40_41xxx for High-performance STM32 F-4 devices.
* - STM32F427_437xx for High-performance STM32 F-4 devices.
* - STM32F429_439xx for High-performance STM32 F-4 devices.
* . * .
* *
* @addtogroup HAL * @addtogroup HAL
@ -44,37 +47,77 @@
/*===========================================================================*/ /*===========================================================================*/
/** /**
* @name Platform identification * @brief Defines the support for realtime counters in the HAL.
*/
#define HAL_IMPLEMENTS_COUNTERS TRUE
/**
* @name Platform identification macros
* @{ * @{
*/ */
#if defined(STM32F40XX) || defined(__DOXYGEN__) #if defined(STM32F429_439xx) || defined(__DOXYGEN__)
#define PLATFORM_NAME "STM32F40x/STM32F41x High Performance" #define PLATFORM_NAME "STM32F429/F439 High Performance with DSP and FPU"
#elif defined(STM32F42XX) #define STM32F4XX
#define PLATFORM_NAME "STM32F42x/STM32F43x High Performance" #elif defined(STM32F427_437xx) || defined(__DOXYGEN__)
#else /* !defined(STM32F40XX) */ #define PLATFORM_NAME "STM32F427/F437 High Performance with DSP and FPU"
#define STM32F4XX
#elif defined(STM32F40_41xxx) || defined(__DOXYGEN__)
#define PLATFORM_NAME "STM32F407/F417 High Performance with DSP and FPU"
#define STM32F4XX
#elif defined(STM32F401xx) || defined(__DOXYGEN__)
#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU"
#define STM32F4XX
#elif defined(STM32F2XX) || defined(__DOXYGEN__)
#define PLATFORM_NAME "STM32F2xx High Performance" #define PLATFORM_NAME "STM32F2xx High Performance"
#endif /* !defined(STM32F40XX) */ #else
#error "STM32F2xx/F4xx device not specified"
#endif
/** @} */ /** @} */
/** /**
* @name Absolute Maximum Ratings * @name Absolute Maximum Ratings
* @{ * @{
*/ */
#if defined(STM32F40XX) || defined(__DOXYGEN__) /**
* @name Absolute Maximum Ratings
* @{
*/
#if defined(STM32F429_439xx) || defined(STM32F429_439xx) || \
defined(__DOXYGEN__)
/**
* @brief Absolute maximum system clock.
*/
#define STM32_SYSCLK_MAX 180000000
/** /**
* @brief Maximum HSE clock frequency. * @brief Maximum HSE clock frequency.
*/ */
#define STM32_HSECLK_MAX 26000000 #define STM32_HSECLK_MAX 26000000
/**
* @brief Maximum HSE clock frequency using an external source.
*/
#define STM32_HSECLK_BYP_MAX 50000000
/** /**
* @brief Minimum HSE clock frequency. * @brief Minimum HSE clock frequency.
*/ */
#define STM32_HSECLK_MIN 1000000 #define STM32_HSECLK_MIN 4000000
/**
* @brief Minimum HSE clock frequency.
*/
#define STM32_HSECLK_BYP_MIN 1000000
/** /**
* @brief Maximum LSE clock frequency. * @brief Maximum LSE clock frequency.
*/ */
#define STM32_LSECLK_MAX 1000000 #define STM32_LSECLK_MAX 32768
/**
* @brief Maximum LSE clock frequency.
*/
#define STM32_LSECLK_BYP_MAX 1000000
/** /**
* @brief Minimum LSE clock frequency. * @brief Minimum LSE clock frequency.
@ -84,7 +127,7 @@
/** /**
* @brief Maximum PLLs input clock frequency. * @brief Maximum PLLs input clock frequency.
*/ */
#define STM32_PLLIN_MAX 2000000 #define STM32_PLLIN_MAX 2100000
/** /**
* @brief Minimum PLLs input clock frequency. * @brief Minimum PLLs input clock frequency.
@ -104,7 +147,7 @@
/** /**
* @brief Maximum PLL output clock frequency. * @brief Maximum PLL output clock frequency.
*/ */
#define STM32_PLLOUT_MAX 168000000 #define STM32_PLLOUT_MAX 180000000
/** /**
* @brief Minimum PLL output clock frequency. * @brief Minimum PLL output clock frequency.
@ -114,23 +157,67 @@
/** /**
* @brief Maximum APB1 clock frequency. * @brief Maximum APB1 clock frequency.
*/ */
#define STM32_PCLK1_MAX 42000000 #define STM32_PCLK1_MAX (STM32_PLLOUT_MAX /4)
/** /**
* @brief Maximum APB2 clock frequency. * @brief Maximum APB2 clock frequency.
*/ */
#define STM32_PCLK2_MAX 84000000 #define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2)
/** /**
* @brief Maximum SPI/I2S clock frequency. * @brief Maximum SPI/I2S clock frequency.
*/ */
#define STM32_SPII2S_MAX 37500000 #define STM32_SPII2S_MAX 45000000
#endif /* STM32F40_41xxx */
#else /* !defined(STM32F40XX) */ #if defined(STM32F40_41xxx) || defined(__DOXYGEN__)
#define STM32_SYSCLK_MAX 168000000
#define STM32_HSECLK_MAX 26000000
#define STM32_HSECLK_BYP_MAX 50000000
#define STM32_HSECLK_MIN 4000000
#define STM32_HSECLK_BYP_MIN 1000000
#define STM32_LSECLK_MAX 32768
#define STM32_LSECLK_BYP_MAX 1000000
#define STM32_LSECLK_MIN 32768
#define STM32_PLLIN_MAX 2100000
#define STM32_PLLIN_MIN 950000
#define STM32_PLLVCO_MAX 432000000
#define STM32_PLLVCO_MIN 192000000
#define STM32_PLLOUT_MAX 168000000
#define STM32_PLLOUT_MIN 24000000
#define STM32_PCLK1_MAX 42000000
#define STM32_PCLK2_MAX 84000000
#define STM32_SPII2S_MAX 42000000
#endif /* STM32F40_41xxx */
#if defined(STM32F401xx) || defined(__DOXYGEN__)
#define STM32_SYSCLK_MAX 84000000
#define STM32_HSECLK_MAX 26000000
#define STM32_HSECLK_BYP_MAX 50000000
#define STM32_HSECLK_MIN 4000000
#define STM32_HSECLK_BYP_MIN 1000000
#define STM32_LSECLK_MAX 32768
#define STM32_LSECLK_BYP_MAX 1000000
#define STM32_LSECLK_MIN 32768
#define STM32_PLLIN_MAX 2100000
#define STM32_PLLIN_MIN 950000
#define STM32_PLLVCO_MAX 432000000
#define STM32_PLLVCO_MIN 192000000
#define STM32_PLLOUT_MAX 84000000
#define STM32_PLLOUT_MIN 24000000
#define STM32_PCLK1_MAX 42000000
#define STM32_PCLK2_MAX 84000000
#define STM32_SPII2S_MAX 42000000
#endif /* STM32F40_41xxx */
#if defined(STM32F2XX)
#define STM32_SYSCLK_MAX 120000000 #define STM32_SYSCLK_MAX 120000000
#define STM32_HSECLK_MAX 26000000 #define STM32_HSECLK_MAX 26000000
#define STM32_HSECLK_BYP_MAX 26000000
#define STM32_HSECLK_MIN 1000000 #define STM32_HSECLK_MIN 1000000
#define STM32_LSECLK_MAX 1000000 #define STM32_HSECLK_BYP_MIN 1000000
#define STM32_LSECLK_MAX 32768
#define STM32_LSECLK_BYP_MAX 1000000
#define STM32_LSECLK_MIN 32768 #define STM32_LSECLK_MIN 32768
#define STM32_PLLIN_MAX 2000000 #define STM32_PLLIN_MAX 2000000
#define STM32_PLLIN_MIN 950000 #define STM32_PLLIN_MIN 950000
@ -140,8 +227,8 @@
#define STM32_PLLOUT_MIN 24000000 #define STM32_PLLOUT_MIN 24000000
#define STM32_PCLK1_MAX 30000000 #define STM32_PCLK1_MAX 30000000
#define STM32_PCLK2_MAX 60000000 #define STM32_PCLK2_MAX 60000000
#define STM32_SPII2S_MAX 37500000 #define STM32_SPII2S_MAX 30000000
#endif /* !defined(STM32F40XX) */ #endif /* defined(STM32F2XX) */
/** @} */ /** @} */
/** /**
@ -156,11 +243,9 @@
* @name PWR_CR register bits definitions * @name PWR_CR register bits definitions
* @{ * @{
*/ */
#if defined(STM32F40XX) || defined(__DOXYGEN__) #define STM32_VOS_SCALE3 (PWR_CR_VOS_0)
#define STM32_VOS_MASK (1 << 14) /**< Core voltage mask. */ #define STM32_VOS_SCALE2 (PWR_CR_VOS_1)
#define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */ #define STM32_VOS_SCALE1 (PWR_CR_VOS_1 | PWR_CR_VOS_0)
#define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */
#endif
#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ #define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ #define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ #define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
@ -306,6 +391,13 @@
#define STM32_PLS STM32_PLS_LEV0 #define STM32_PLS STM32_PLS_LEV0
#endif #endif
/**
* @brief Enables the backup RAM regulator.
*/
#if !defined(STM32_BKPRAM_ENABLE) || defined(__DOXYGEN__)
#define STM32_BKPRAM_ENABLE FALSE
#endif
/** /**
* @brief Enables or disables the HSI clock source. * @brief Enables or disables the HSI clock source.
*/ */
@ -352,17 +444,7 @@
#define STM32_SW STM32_SW_PLL #define STM32_SW STM32_SW_PLL
#endif #endif
#if defined(STM32F40XX) || defined(__DOXYGEN__) #if defined(STM32F4XX) || defined(__DOXYGEN__)
/**
* @brief Core voltage selection.
* @note This setting affects all the performance and clock related
* settings, the maximum performance is only obtainable selecting
* the maximum voltage.
*/
#if !defined(STM32_VOS) || defined(__DOXYGEN__)
#define STM32_VOS STM32_VOS_HIGH
#endif
/** /**
* @brief Clock source for the PLLs. * @brief Clock source for the PLLs.
* @note This setting has only effect if the PLL is selected as the * @note This setting has only effect if the PLL is selected as the
@ -414,7 +496,7 @@
#define STM32_PLLQ_VALUE 7 #define STM32_PLLQ_VALUE 7
#endif #endif
#else /* !defined(STM32F40XX) */ #else /* !defined(STM32F4XX) */
/** /**
* @brief Clock source for the PLLs. * @brief Clock source for the PLLs.
* @note This setting has only effect if the PLL is selected as the * @note This setting has only effect if the PLL is selected as the
@ -465,7 +547,7 @@
#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) #if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLQ_VALUE 5 #define STM32_PLLQ_VALUE 5
#endif #endif
#endif /* !defined(STM32F40XX) */ #endif /* !defined(STM32F4XX) */
/** /**
* @brief AHB prescaler value. * @brief AHB prescaler value.
@ -562,14 +644,7 @@
/* Derived constants and error checks. */ /* Derived constants and error checks. */
/*===========================================================================*/ /*===========================================================================*/
/* #if defined(STM32F4XX) || defined(__DOXYGEN__)
* MCU variant check.
*/
#if defined(STM32F42XX)
#error "unsupported STM32F4XX variant"
#endif
#if defined(STM32F40XX) || defined(__DOXYGEN__)
/* /*
* Configuration-related checks. * Configuration-related checks.
*/ */
@ -577,39 +652,31 @@
#error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined" #error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined"
#endif #endif
/** #else /* !defined(STM32F4XX) */
* @brief Maximum SYSCLK.
* @note It is a function of the core voltage setting.
*/
#if (STM32_VOS == STM32_VOS_HIGH) || defined(__DOXYGEN__)
#define STM32_SYSCLK_MAX 168000000
#else
#define STM32_SYSCLK_MAX 144000000
#endif
#else /* !defined(STM32F40XX) */
/* /*
* Configuration-related checks. * Configuration-related checks.
*/ */
#if !defined(STM32F2xx_MCUCONF) #if !defined(STM32F2xx_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32F2xx_MCUCONF not defined" #error "Using a wrong mcuconf.h file, STM32F2xx_MCUCONF not defined"
#endif #endif
#endif /* !defined(STM32F40XX) */ #endif /* !defined(STM32F4XX) */
/** /**
* @brief Maximum frequency thresholds and wait states for flash access. * @brief Maximum frequency thresholds and wait states for flash access.
* @note The values are valid for 2.7V to 3.6V supply range. * @note The values are valid for 2.7V to 3.6V supply range.
*/ */
#if defined(STM32F40XX) || defined(__DOXYGEN__) #if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
defined(STM32F40_41xxx) || defined(__DOXYGEN__)
#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__) #if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)
#define STM32_0WS_THRESHOLD 30000000 #define STM32_0WS_THRESHOLD 30000000
#define STM32_1WS_THRESHOLD 60000000 #define STM32_1WS_THRESHOLD 60000000
#define STM32_2WS_THRESHOLD 90000000 #define STM32_2WS_THRESHOLD 90000000
#define STM32_3WS_THRESHOLD 120000000 #define STM32_3WS_THRESHOLD 120000000
#define STM32_4WS_THRESHOLD 150000000 #define STM32_4WS_THRESHOLD 150000000
#define STM32_5WS_THRESHOLD 168000000 #define STM32_5WS_THRESHOLD 180000000
#define STM32_6WS_THRESHOLD 0 #define STM32_6WS_THRESHOLD 0
#define STM32_7WS_THRESHOLD 0 #define STM32_7WS_THRESHOLD 0
#define STM32_8WS_THRESHOLD 0
#elif (STM32_VDD >= 240) && (STM32_VDD < 270) #elif (STM32_VDD >= 240) && (STM32_VDD < 270)
#define STM32_0WS_THRESHOLD 24000000 #define STM32_0WS_THRESHOLD 24000000
#define STM32_1WS_THRESHOLD 48000000 #define STM32_1WS_THRESHOLD 48000000
@ -618,31 +685,79 @@
#define STM32_4WS_THRESHOLD 120000000 #define STM32_4WS_THRESHOLD 120000000
#define STM32_5WS_THRESHOLD 144000000 #define STM32_5WS_THRESHOLD 144000000
#define STM32_6WS_THRESHOLD 168000000 #define STM32_6WS_THRESHOLD 168000000
#define STM32_7WS_THRESHOLD 180000000
#define STM32_8WS_THRESHOLD 0
#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
#define STM32_0WS_THRESHOLD 22000000
#define STM32_1WS_THRESHOLD 44000000
#define STM32_2WS_THRESHOLD 66000000
#define STM32_3WS_THRESHOLD 88000000
#define STM32_4WS_THRESHOLD 110000000
#define STM32_5WS_THRESHOLD 132000000
#define STM32_6WS_THRESHOLD 154000000
#define STM32_7WS_THRESHOLD 176000000
#define STM32_8WS_THRESHOLD 180000000
#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
#define STM32_0WS_THRESHOLD 20000000
#define STM32_1WS_THRESHOLD 40000000
#define STM32_2WS_THRESHOLD 60000000
#define STM32_3WS_THRESHOLD 80000000
#define STM32_4WS_THRESHOLD 100000000
#define STM32_5WS_THRESHOLD 120000000
#define STM32_6WS_THRESHOLD 140000000
#define STM32_7WS_THRESHOLD 168000000
#define STM32_8WS_THRESHOLD 0
#else
#error "invalid VDD voltage specified"
#endif
#elif defined(STM32F401xx)
#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
#define STM32_0WS_THRESHOLD 30000000
#define STM32_1WS_THRESHOLD 60000000
#define STM32_2WS_THRESHOLD 84000000
#define STM32_3WS_THRESHOLD 0
#define STM32_4WS_THRESHOLD 0
#define STM32_5WS_THRESHOLD 0
#define STM32_6WS_THRESHOLD 0
#define STM32_7WS_THRESHOLD 0 #define STM32_7WS_THRESHOLD 0
#define STM32_8WS_THRESHOLD 0
#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
#define STM32_0WS_THRESHOLD 24000000
#define STM32_1WS_THRESHOLD 48000000
#define STM32_2WS_THRESHOLD 72000000
#define STM32_3WS_THRESHOLD 84000000
#define STM32_4WS_THRESHOLD 0
#define STM32_5WS_THRESHOLD 0
#define STM32_6WS_THRESHOLD 0
#define STM32_7WS_THRESHOLD 0
#define STM32_8WS_THRESHOLD 0
#elif (STM32_VDD >= 210) && (STM32_VDD < 240) #elif (STM32_VDD >= 210) && (STM32_VDD < 240)
#define STM32_0WS_THRESHOLD 18000000 #define STM32_0WS_THRESHOLD 18000000
#define STM32_1WS_THRESHOLD 36000000 #define STM32_1WS_THRESHOLD 36000000
#define STM32_2WS_THRESHOLD 54000000 #define STM32_2WS_THRESHOLD 54000000
#define STM32_3WS_THRESHOLD 72000000 #define STM32_3WS_THRESHOLD 72000000
#define STM32_4WS_THRESHOLD 90000000 #define STM32_4WS_THRESHOLD 840000000
#define STM32_5WS_THRESHOLD 108000000 #define STM32_5WS_THRESHOLD 0
#define STM32_6WS_THRESHOLD 120000000 #define STM32_6WS_THRESHOLD 0
#define STM32_7WS_THRESHOLD 138000000 #define STM32_7WS_THRESHOLD 0
#define STM32_8WS_THRESHOLD 0
#elif (STM32_VDD >= 180) && (STM32_VDD < 210) #elif (STM32_VDD >= 180) && (STM32_VDD < 210)
#define STM32_0WS_THRESHOLD 16000000 #define STM32_0WS_THRESHOLD 16000000
#define STM32_1WS_THRESHOLD 32000000 #define STM32_1WS_THRESHOLD 32000000
#define STM32_2WS_THRESHOLD 48000000 #define STM32_2WS_THRESHOLD 48000000
#define STM32_3WS_THRESHOLD 64000000 #define STM32_3WS_THRESHOLD 64000000
#define STM32_4WS_THRESHOLD 80000000 #define STM32_4WS_THRESHOLD 800000000
#define STM32_5WS_THRESHOLD 96000000 #define STM32_5WS_THRESHOLD 840000000
#define STM32_6WS_THRESHOLD 112000000 #define STM32_6WS_THRESHOLD 0
#define STM32_7WS_THRESHOLD 128000000 #define STM32_7WS_THRESHOLD 0
#define STM32_8WS_THRESHOLD 0
#else #else
#error "invalid VDD voltage specified" #error "invalid VDD voltage specified"
#endif #endif
#else /* !defined(STM32F40XX) */ #else /* STM32F2XX */
#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__) #if (STM32_VDD >= 270) && (STM32_VDD <= 360)
#define STM32_0WS_THRESHOLD 30000000 #define STM32_0WS_THRESHOLD 30000000
#define STM32_1WS_THRESHOLD 60000000 #define STM32_1WS_THRESHOLD 60000000
#define STM32_2WS_THRESHOLD 90000000 #define STM32_2WS_THRESHOLD 90000000
@ -681,7 +796,7 @@
#else #else
#error "invalid VDD voltage specified" #error "invalid VDD voltage specified"
#endif #endif
#endif /* !defined(STM32F40XX) */ #endif /* STM32F2XX */
/* /*
* HSI related checks. * HSI related checks.
@ -916,6 +1031,43 @@
#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" #error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
#endif #endif
/* Calculating VOS settings, it is different for each sub-platform.*/
#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
defined(__DOXYGEN__)
#if STM32_SYSCLK <= 120000000
#define STM32_VOS STM32_VOS_SCALE3
#define STM32_OVERDRIVE_REQUIRED FALSE
#elif STM32_SYSCLK <= 144000000
#define STM32_VOS STM32_VOS_SCALE2
#define STM32_OVERDRIVE_REQUIRED FALSE
#elif STM32_SYSCLK <= 168000000
#define STM32_VOS STM32_VOS_SCALE1
#define STM32_OVERDRIVE_REQUIRED FALSE
#else
#define STM32_VOS STM32_VOS_SCALE1
#define STM32_OVERDRIVE_REQUIRED TRUE
#endif
#elif defined(STM32F40_41xxx)
#if STM32_SYSCLK <= 144000000
#define STM32_VOS STM32_VOS_SCALE2
#else
#define STM32_VOS STM32_VOS_SCALE1
#endif
#define STM32_OVERDRIVE_REQUIRED FALSE
#elif defined(STM32F401xx)
#if STM32_SYSCLK <= 60000000
#define STM32_VOS STM32_VOS_SCALE3
#else
#define STM32_VOS STM32_VOS_SCALE2
#endif
#define STM32_OVERDRIVE_REQUIRED FALSE
#else /* STM32F2XX */
#define STM32_OVERDRIVE_REQUIRED FALSE
#endif
/** /**
* @brief AHB frequency. * @brief AHB frequency.
*/ */
@ -1189,8 +1341,10 @@
#define STM32_FLASHBITS 0x00000005 #define STM32_FLASHBITS 0x00000005
#elif STM32_HCLK <= STM32_6WS_THRESHOLD #elif STM32_HCLK <= STM32_6WS_THRESHOLD
#define STM32_FLASHBITS 0x00000006 #define STM32_FLASHBITS 0x00000006
#else #elif STM32_HCLK <= STM32_7WS_THRESHOLD
#define STM32_FLASHBITS 0x00000007 #define STM32_FLASHBITS 0x00000007
#else
#define STM32_FLASHBITS 0x00000008
#endif #endif
/* There are differences in vector names in the various sub-families, /* There are differences in vector names in the various sub-families,

4
os/hal/ports/STM32F4xx/stm32_registry.h
View File

@ -25,10 +25,6 @@
#ifndef _STM32_REGISTRY_H_ #ifndef _STM32_REGISTRY_H_
#define _STM32_REGISTRY_H_ #define _STM32_REGISTRY_H_
#if defined(STM32F40XX) || defined(STM32F427X)
#define STM32F4XX
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Platform capabilities. */ /* Platform capabilities. */
/*===========================================================================*/ /*===========================================================================*/