diff --git a/demos/rt/RT-STM32F429-DISCOVERY/.project b/demos/rt/RT-STM32F429-DISCOVERY/.project index d9fbaf68c..86c3460c5 100644 --- a/demos/rt/RT-STM32F429-DISCOVERY/.project +++ b/demos/rt/RT-STM32F429-DISCOVERY/.project @@ -76,11 +76,6 @@ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - board - 2 - CHIBIOS/boards/ST_STM32F429I_DISCOVERY - os 2 diff --git a/demos/rt/RT-STM32F429-DISCOVERY/Makefile b/demos/rt/RT-STM32F429-DISCOVERY/Makefile index b6b2312e8..376c88a3b 100644 --- a/demos/rt/RT-STM32F429-DISCOVERY/Makefile +++ b/demos/rt/RT-STM32F429-DISCOVERY/Makefile @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + # If enabled, this option allows to compile the application in THUMB mode. ifeq ($(USE_THUMB),) USE_THUMB = yes @@ -41,15 +46,21 @@ endif # Architecture or project specific options # -# Enables the use of FPU on Cortex-M4. -# Enable this if you really want to use the STM FWLib. -ifeq ($(USE_FPU),) - USE_FPU = no +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 endif -# Enable this if you really want to use the STM FWLib. -ifeq ($(USE_FWLIB),) - USE_FWLIB = no +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4. +ifeq ($(USE_FPU),) + USE_FPU = no endif # @@ -64,12 +75,13 @@ endif PROJECT = ch # Imported source files and paths -CHIBIOS = ../.. -include $(CHIBIOS)/boards/ST_STM32F429I_DISCOVERY/board.mk -include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +CHIBIOS = ../../.. include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/ports/STM32F4xx/platform.mk +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/rt/osal/osal.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk include $(CHIBIOS)/test/test.mk # Define linker script file here @@ -81,6 +93,7 @@ CSRC = $(PORTSRC) \ $(KERNSRC) \ $(TESTSRC) \ $(HALSRC) \ + $(OSALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ $(CHIBIOS)/os/various/shell.c \ @@ -115,7 +128,7 @@ TCPPSRC = ASMSRC = $(PORTASM) INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ $(CHIBIOS)/os/various/devices_lib/accel \ $(CHIBIOS)/os/various @@ -141,6 +154,7 @@ LD = $(TRGT)gcc CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp OD = $(TRGT)objdump +SZ = $(TRGT)size HEX = $(CP) -O ihex BIN = $(CP) -O binary @@ -160,29 +174,6 @@ CPPWARN = -Wall -Wextra # Compiler settings ############################################################################## -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - ############################################################################## # Start of user section # @@ -206,18 +197,5 @@ ULIBS = # End of user defines ############################################################################## -ifeq ($(USE_FPU),yes) - USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant - DDEFS += -DCORTEX_USE_FPU=TRUE -else - DDEFS += -DCORTEX_USE_FPU=FALSE -endif - -ifeq ($(USE_FWLIB),yes) - include $(CHIBIOS)/ext/stm32lib/stm32lib.mk - CSRC += $(STM32SRC) - INCDIR += $(STM32INC) - USE_OPT += -DUSE_STDPERIPH_DRIVER -endif - -include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk +RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/demos/rt/RT-STM32F429-DISCOVERY/chconf.h b/demos/rt/RT-STM32F429-DISCOVERY/chconf.h index f943ea80c..70343b6f3 100644 --- a/demos/rt/RT-STM32F429-DISCOVERY/chconf.h +++ b/demos/rt/RT-STM32F429-DISCOVERY/chconf.h @@ -30,19 +30,49 @@ /*===========================================================================*/ /** - * @name Kernel parameters and options + * @name System timers settings * @{ */ /*===========================================================================*/ +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + /** * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** + * @brief Realtime Counter frequency. + * @details Frequency of the system counter used for realtime delays and + * measurements. + */ +#define CH_CFG_RTC_FREQUENCY 168000000 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ /** * @brief Round robin interval. @@ -51,13 +81,12 @@ * disables the preemption for threads with equal priority and the * round robin becomes cooperative. Note that higher priority * threads can still preempt, the kernel is always preemptive. - * * @note Disabling the round robin preemption makes the kernel more compact * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif +#define CH_CFG_TIME_QUANTUM 0 /** * @brief Managed RAM size. @@ -68,28 +97,17 @@ * * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_MEMCORE. + * @note Requires @p CH_CFG_USE_MEMCORE. */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif +#define CH_CFG_MEMCORE_SIZE 0 /** * @brief Idle thread automatic spawn suppression. * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread automatically. The application has - * then the responsibility to do one of the following: - * - Spawn a custom idle thread at priority @p IDLEPRIO. - * - Change the main() thread priority to @p IDLEPRIO then enter - * an endless loop. In this scenario the @p main() thread acts as - * the idle thread. - * . - * @note Unless an idle thread is spawned the @p main() thread must not - * enter a sleep state. - */ -#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) -#define CH_NO_IDLE_THREAD FALSE -#endif + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. */ +#define CH_CFG_NO_IDLE_THREAD FALSE /** @} */ @@ -108,9 +126,7 @@ * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif +#define CH_CFG_OPTIMIZE_SPEED TRUE /** @} */ @@ -121,15 +137,22 @@ */ /*===========================================================================*/ +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + /** * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * * @note The default is @p TRUE. */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif +#define CH_CFG_USE_REGISTRY TRUE /** * @brief Threads synchronization APIs. @@ -138,9 +161,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif +#define CH_CFG_USE_WAITEXIT TRUE /** * @brief Semaphores APIs. @@ -148,33 +169,18 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif +#define CH_CFG_USE_SEMAPHORES TRUE /** * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE /** * @brief Mutexes APIs. @@ -182,9 +188,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif +#define CH_CFG_USE_MUTEXES TRUE /** * @brief Conditional Variables APIs. @@ -192,11 +196,9 @@ * in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note Requires @p CH_CFG_USE_MUTEXES. */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif +#define CH_CFG_USE_CONDVARS TRUE /** * @brief Conditional Variables APIs with timeout. @@ -204,11 +206,9 @@ * specification are included in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note Requires @p CH_CFG_USE_CONDVARS. */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE /** * @brief Events Flags APIs. @@ -216,9 +216,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif +#define CH_CFG_USE_EVENTS TRUE /** * @brief Events Flags APIs with timeout. @@ -226,11 +224,9 @@ * are included in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note Requires @p CH_CFG_USE_EVENTS. */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE /** * @brief Synchronous Messages APIs. @@ -239,21 +235,18 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif +#define CH_CFG_USE_MESSAGES TRUE /** * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE /** * @brief Mailboxes APIs. @@ -261,11 +254,9 @@ * included in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note Requires @p CH_CFG_USE_SEMAPHORES. */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif +#define CH_CFG_USE_MAILBOXES TRUE /** * @brief I/O Queues APIs. @@ -273,9 +264,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif +#define CH_CFG_USE_QUEUES TRUE /** * @brief Core Memory Manager APIs. @@ -284,9 +273,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif +#define CH_CFG_USE_MEMCORE TRUE /** * @brief Heap Allocator APIs. @@ -294,27 +281,11 @@ * in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif +#define CH_CFG_USE_HEAP TRUE /** * @brief Memory Pools Allocator APIs. @@ -323,9 +294,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif +#define CH_CFG_USE_MEMPOOLS TRUE /** * @brief Dynamic Threads APIs. @@ -333,12 +302,10 @@ * in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif +#define CH_CFG_USE_DYNAMIC TRUE /** @} */ @@ -349,6 +316,13 @@ */ /*===========================================================================*/ +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + /** * @brief Debug option, system state check. * @details If enabled the correct call protocol for system APIs is checked @@ -356,9 +330,7 @@ * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK FALSE -#endif +#define CH_DBG_SYSTEM_STATE_CHECK FALSE /** * @brief Debug option, parameters checks. @@ -367,9 +339,7 @@ * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif +#define CH_DBG_ENABLE_CHECKS FALSE /** * @brief Debug option, consistency checks. @@ -379,9 +349,7 @@ * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif +#define CH_DBG_ENABLE_ASSERTS FALSE /** * @brief Debug option, trace buffer. @@ -390,9 +358,7 @@ * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif +#define CH_DBG_ENABLE_TRACE FALSE /** * @brief Debug option, stack checks. @@ -404,9 +370,7 @@ * @note The default failure mode is to halt the system with the global * @p panic_msg variable set to @p NULL. */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif +#define CH_DBG_ENABLE_STACK_CHECK FALSE /** * @brief Debug option, stacks initialization. @@ -416,22 +380,18 @@ * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif +#define CH_DBG_FILL_THREADS FALSE /** * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that + * @details If enabled then a field is added to the @p thread_t structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif +#define CH_DBG_THREADS_PROFILING FALSE /** @} */ @@ -444,12 +404,10 @@ /** * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p Thread structure. + * @details User fields added to the end of the @p thread_t structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ +#define CH_CFG_THREAD_EXTRA_FIELDS \ /* Add threads custom fields here.*/ -#endif /** * @brief Threads initialization hook. @@ -458,11 +416,9 @@ * @note It is invoked from within @p chThdInit() and implicitly from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT_HOOK(tp) { \ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ /* Add threads initialization code here.*/ \ } -#endif /** * @brief Threads finalization hook. @@ -472,53 +428,61 @@ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT_HOOK(tp) { \ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ /* Add threads finalization code here.*/ \ } -#endif /** * @brief Context switch hook. * @details This hook is invoked just before switching between threads. */ -#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) -#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ /* System halt code here.*/ \ } -#endif + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ +} /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ +#define CH_CFG_IDLE_LOOP_HOOK() { \ /* Idle loop code here.*/ \ } -#endif /** * @brief System tick event hook. * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) -#define SYSTEM_TICK_EVENT_HOOK() { \ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ /* System tick event code here.*/ \ } -#endif /** * @brief System halt hook. * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) -#define SYSTEM_HALT_HOOK() { \ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ /* System halt code here.*/ \ } -#endif /** @} */ diff --git a/demos/rt/RT-STM32F429-DISCOVERY/halconf.h b/demos/rt/RT-STM32F429-DISCOVERY/halconf.h index 45f3bf130..bd5a46fba 100644 --- a/demos/rt/RT-STM32F429-DISCOVERY/halconf.h +++ b/demos/rt/RT-STM32F429-DISCOVERY/halconf.h @@ -30,13 +30,6 @@ #include "mcuconf.h" -/** - * @brief Enables the TM subsystem. - */ -#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) -#define HAL_USE_TM FALSE -#endif - /** * @brief Enables the PAL subsystem. */ diff --git a/demos/rt/RT-STM32F429-DISCOVERY/main.c b/demos/rt/RT-STM32F429-DISCOVERY/main.c index 0e96799e1..bb8e7ea2f 100644 --- a/demos/rt/RT-STM32F429-DISCOVERY/main.c +++ b/demos/rt/RT-STM32F429-DISCOVERY/main.c @@ -26,7 +26,7 @@ /* * Red LED blinker thread, times are in milliseconds. */ -static WORKING_AREA(waThread1, 128); +static THD_WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { (void)arg; @@ -42,7 +42,7 @@ static msg_t Thread1(void *arg) { /* * Green LED blinker thread, times are in milliseconds. */ -static WORKING_AREA(waThread2, 128); +static THD_WORKING_AREA(waThread2, 128); static msg_t Thread2(void *arg) { (void)arg; @@ -62,8 +62,8 @@ static msg_t Thread2(void *arg) { /* Virtual serial port over USB.*/ SerialUSBDriver SDU1; -#define SHELL_WA_SIZE THD_WA_SIZE(2048) -#define TEST_WA_SIZE THD_WA_SIZE(256) +#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048) +#define TEST_WA_SIZE THD_WORKING_AREA_SIZE(256) static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { size_t n, size; @@ -80,8 +80,8 @@ static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { } static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { - static const char *states[] = {THD_STATE_NAMES}; - Thread *tp; + static const char *states[] = {CH_STATE_NAMES}; + thread_t *tp; (void)argv; if (argc > 0) { @@ -91,23 +91,23 @@ static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { chprintf(chp, " addr stack prio refs state time\r\n"); tp = chRegFirstThread(); do { - chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s\r\n", (uint32_t)tp, (uint32_t)tp->p_ctx.r13, (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), - states[tp->p_state], (uint32_t)tp->p_time); + states[tp->p_state]); tp = chRegNextThread(tp); } while (tp != NULL); } static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { - Thread *tp; + thread_t *tp; (void)argv; if (argc > 0) { chprintf(chp, "Usage: test\r\n"); return; } - tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriorityX(), TestThread, chp); if (tp == NULL) { chprintf(chp, "out of memory\r\n"); @@ -136,7 +136,7 @@ static const ShellConfig shell_cfg1 = { * Application entry point. */ int main(void) { - Thread *shelltp = NULL; + thread_t *shelltp = NULL; /* * System initializations. @@ -190,7 +190,7 @@ int main(void) { } else { /* If the previous shell exited.*/ - if (chThdTerminated(shelltp)) { + if (chThdTerminatedX(shelltp)) { /* Recovers memory of the previous shell.*/ chThdRelease(shelltp); shelltp = NULL; diff --git a/demos/rt/RT-STM32F429-DISCOVERY/usbcfg.c b/demos/rt/RT-STM32F429-DISCOVERY/usbcfg.c index a378f3115..a644cac41 100644 --- a/demos/rt/RT-STM32F429-DISCOVERY/usbcfg.c +++ b/demos/rt/RT-STM32F429-DISCOVERY/usbcfg.c @@ -270,7 +270,7 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { case USB_EVENT_ADDRESS: return; case USB_EVENT_CONFIGURED: - chSysLockFromIsr(); + chSysLockFromISR(); /* Enables the endpoints specified into the configuration. Note, this callback is invoked from an ISR so I-Class functions @@ -281,7 +281,7 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { /* Resetting the state of the CDC subsystem.*/ sduConfigureHookI(&SDU1); - chSysUnlockFromIsr(); + chSysUnlockFromISR(); return; case USB_EVENT_SUSPEND: return; diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld new file mode 100644 index 000000000..b7d9ba349 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld @@ -0,0 +1,31 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F429xI memory setup. + */ +MEMORY +{ + flash : org = 0x08000000, len = 2M + ram : org = 0x20000000, len = 192k + ccmram : org = 0x10000000, len = 64k +} + +INCLUDE rules.ld diff --git a/os/ext/CMSIS/ST/stm32f4xx.h b/os/ext/CMSIS/ST/stm32f4xx.h index d98436814..4de8a166e 100644 --- a/os/ext/CMSIS/ST/stm32f4xx.h +++ b/os/ext/CMSIS/ST/stm32f4xx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx.h * @author MCD Application Team - * @version V1.1.0 - * @date 11-January-2013 + * @version V1.2.1 + * @date 19-September-2013 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F4xx devices. @@ -65,17 +65,38 @@ application */ -#if !defined (STM32F4XX) && !defined (STM32F40XX) && !defined (STM32F427X) - /* #define STM32F40XX */ /*!< STM32F40xx/41xx Devices */ - /* #define STM32F427X */ /*!< STM32F427x/437x Devices*/ +#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) + /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG, + STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, + STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ + + /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II, + STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */ + + /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, + STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, + STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI, + STM32F439IG and STM32F439II Devices */ + + /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ + #endif +/* Old STM32F40XX definition, maintained for legacy purpose */ +#ifdef STM32F40XX + #define STM32F40_41xxx +#endif /* STM32F40XX */ + +/* Old STM32F427X definition, maintained for legacy purpose */ +#ifdef STM32F427X + #define STM32F427_437xx +#endif /* STM32F427X */ /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. */ -#if !defined (STM32F4XX) && !defined (STM32F40XX) && !defined (STM32F427X) +#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" #endif @@ -98,6 +119,7 @@ #if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #endif /* HSE_VALUE */ /** @@ -105,7 +127,7 @@ Timeout value */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */ #endif /* HSE_STARTUP_TIMEOUT */ #if !defined (HSI_VALUE) @@ -113,10 +135,10 @@ #endif /* HSI_VALUE */ /** - * @brief STM32F4XX Standard Peripherals Library version number V1.1.0 + * @brief STM32F4XX Standard Peripherals Library version number V1.2.0 */ #define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ @@ -176,6 +198,8 @@ typedef enum IRQn DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + +#if defined (STM32F40_41xxx) CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ @@ -238,20 +262,197 @@ typedef enum IRQn DCMI_IRQn = 78, /*!< DCMI global interrupt */ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - -#ifdef STM32F40XX FPU_IRQn = 81 /*!< FPU global interrupt */ -#endif /* STM32F40XX */ +#endif /* STM32F40_41xxx */ -#ifdef STM32F427X +#if defined (STM32F427_437xx) + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ UART7_IRQn = 82, /*!< UART7 global interrupt */ UART8_IRQn = 83, /*!< UART8 global interrupt */ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - SPI6_IRQn = 86 /*!< SPI6 global Interrupt */ -#endif /* STM32F427X */ - + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ +#endif /* STM32F427_437xx */ + +#if defined (STM32F429_439xx) + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ +#endif /* STM32F429_439xx */ + +#if defined (STM32F401xx) + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ +#endif /* STM32F401xx */ + } IRQn_Type; /** @@ -501,6 +702,37 @@ typedef struct __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ } DMA_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; /** * @brief Ethernet MAC @@ -605,6 +837,7 @@ typedef struct __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ } FLASH_TypeDef; +#if defined (STM32F40_41xxx) /** * @brief Flexible Static Memory Controller */ @@ -663,6 +896,81 @@ typedef struct __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ } FSMC_Bank4_TypeDef; +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FMC_Bank4_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; +#endif /* STM32F427_437xx || STM32F429_439xx */ /** * @brief General Purpose I/O @@ -735,6 +1043,54 @@ typedef struct __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ } IWDG_TypeDef; +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + /** * @brief Power Control */ @@ -781,11 +1137,8 @@ typedef struct uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ - -#ifdef STM32F427X - uint32_t RESERVED7; /*!< Reserved, 0x88 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ -#endif /* STM32F427X */ } RCC_TypeDef; @@ -837,6 +1190,28 @@ typedef struct __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ } RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + /** * @brief SD host Interface */ @@ -1062,12 +1437,19 @@ typedef struct #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ + +#if defined (STM32F40_41xxx) #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ +#endif /* STM32F427_437xx || STM32F429_439xx */ #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ -#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */ +#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ @@ -1075,6 +1457,7 @@ typedef struct #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE + /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) @@ -1131,6 +1514,12 @@ typedef struct #define TIM11_BASE (APB2PERIPH_BASE + 0x4800) #define SPI5_BASE (APB2PERIPH_BASE + 0x5000) #define SPI6_BASE (APB2PERIPH_BASE + 0x5400) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) +#define LTDC_BASE (APB2PERIPH_BASE + 0x6800) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) /*!< AHB1 peripherals */ #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) @@ -1142,7 +1531,8 @@ typedef struct #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) - +#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400) +#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800) #define CRC_BASE (AHB1PERIPH_BASE + 0x3000) #define RCC_BASE (AHB1PERIPH_BASE + 0x3800) #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) @@ -1169,6 +1559,7 @@ typedef struct #define ETH_MMC_BASE (ETH_BASE + 0x0100) #define ETH_PTP_BASE (ETH_BASE + 0x0700) #define ETH_DMA_BASE (ETH_BASE + 0x1000) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) /*!< AHB2 peripherals */ #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) @@ -1177,12 +1568,24 @@ typedef struct #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710) #define RNG_BASE (AHB2PERIPH_BASE + 0x60800) +#if defined (STM32F40_41xxx) /*!< FSMC Bankx registers base address */ #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) +#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) +#endif /* STM32F427_437xx || STM32F429_439xx */ /* Debug MCU registers base address */ #define DBGMCU_BASE ((uint32_t )0xE0042000) @@ -1241,7 +1644,12 @@ typedef struct #define TIM11 ((TIM_TypeDef *) TIM11_BASE) #define SPI5 ((SPI_TypeDef *) SPI5_BASE) #define SPI6 ((SPI_TypeDef *) SPI6_BASE) - +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) @@ -1251,7 +1659,8 @@ typedef struct #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) - +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) @@ -1274,16 +1683,30 @@ typedef struct #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) #define ETH ((ETH_TypeDef *) ETH_BASE) +#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) #define DCMI ((DCMI_TypeDef *) DCMI_BASE) #define CRYP ((CRYP_TypeDef *) CRYP_BASE) #define HASH ((HASH_TypeDef *) HASH_BASE) #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) + +#if defined (STM32F40_41xxx) #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#endif /* STM32F427_437xx || STM32F429_439xx */ + #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) /** @@ -1308,12 +1731,12 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!MII_KS8721_ID RMII + STM32F40_41xxx diff --git a/os/hal/boards/OLIMEX_STM32_H407/board.c b/os/hal/boards/OLIMEX_STM32_H407/board.c new file mode 100644 index 000000000..8f24f8bc3 --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_H407/board.c @@ -0,0 +1,107 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + static bool_t last_status = FALSE; + + if (blkIsTransferring(sdcp)) + return last_status; + return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3); +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + return FALSE; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/os/hal/boards/OLIMEX_STM32_H407/board.h b/os/hal/boards/OLIMEX_STM32_H407/board.h new file mode 100644 index 000000000..37879aa5e --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_H407/board.h @@ -0,0 +1,1301 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Olimex STM32-H407 board. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_STM32_H407 +#define BOARD_NAME "Olimex STM32-H407" + +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID MII_KS8721_ID +#define BOARD_PHY_RMII + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768 +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 12000000 +#endif + + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 330 + +/* + * MCU type as defined in the ST header. + */ +#define STM32F40_41xxx + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON_WKUP 0 +#define GPIOA_ETH_RMII_REF_CLK 1 +#define GPIOA_ETH_RMII_MDIO 2 +#define GPIOA_ETH_RMII_MDINT 3 +#define GPIOA_PIN4 4 +#define GPIOA_PIN5 5 +#define GPIOA_PIN6 6 +#define GPIOA_ETH_RMII_CRS_DV 7 +#define GPIOA_USB_HS_BUSON 8 +#define GPIOA_OTG_FS_VBUS 9 +#define GPIOA_OTG_FS_ID 10 +#define GPIOA_OTG_FS_DM 11 +#define GPIOA_OTG_FS_DP 12 +#define GPIOA_JTAG_TMS 13 +#define GPIOA_JTAG_TCK 14 +#define GPIOA_JTAG_TDI 15 + +#define GPIOB_USB_FS_BUSON 0 +#define GPIOB_USB_HS_FAULT 1 +#define GPIOB_BOOT1 2 +#define GPIOB_JTAG_TDO 3 +#define GPIOB_JTAG_TRST 4 +#define GPIOB_PIN5 5 +#define GPIOB_PIN6 6 +#define GPIOB_PIN7 7 +#define GPIOB_I2C1_SCL 8 +#define GPIOB_I2C1_SDA 9 +#define GPIOB_SPI2_SCK 10 +#define GPIOB_PIN11 11 +#define GPIOB_OTG_HS_ID 12 +#define GPIOB_OTG_HS_VBUS 13 +#define GPIOB_OTG_HS_DM 14 +#define GPIOB_OTG_HS_DP 15 + +#define GPIOC_PIN0 0 +#define GPIOC_ETH_RMII_MDC 1 +#define GPIOC_SPI2_MISO 2 +#define GPIOC_SPI2_MOSI 3 +#define GPIOC_ETH_RMII_RXD0 4 +#define GPIOC_ETH_RMII_RXD1 5 +#define GPIOC_USART6_TX 6 +#define GPIOC_USART6_RX 7 +#define GPIOC_SD_D0 8 +#define GPIOC_SD_D1 9 +#define GPIOC_SD_D2 10 +#define GPIOC_SD_D3 11 +#define GPIOC_SD_CLK 12 +#define GPIOC_LED 13 +#define GPIOC_OSC32_IN 14 +#define GPIOC_OSC32_OUT 15 + +#define GPIOD_PIN0 0 +#define GPIOD_PIN1 1 +#define GPIOD_SD_CMD 2 +#define GPIOD_PIN3 3 +#define GPIOD_PIN4 4 +#define GPIOD_PIN5 5 +#define GPIOD_PIN6 6 +#define GPIOD_PIN7 7 +#define GPIOD_PIN8 8 +#define GPIOD_PIN9 9 +#define GPIOD_PIN10 10 +#define GPIOD_PIN11 11 +#define GPIOD_PIN12 12 +#define GPIOD_PIN13 13 +#define GPIOD_PIN14 14 +#define GPIOD_PIN15 15 + +#define GPIOE_PIN0 0 +#define GPIOE_PIN1 1 +#define GPIOE_PIN2 2 +#define GPIOE_PIN3 3 +#define GPIOE_PIN4 4 +#define GPIOE_PIN5 5 +#define GPIOE_PIN6 6 +#define GPIOE_PIN7 7 +#define GPIOE_PIN8 8 +#define GPIOE_PIN9 9 +#define GPIOE_PIN10 10 +#define GPIOE_PIN11 11 +#define GPIOE_PIN12 12 +#define GPIOE_PIN13 13 +#define GPIOE_PIN14 14 +#define GPIOE_PIN15 15 + +#define GPIOF_PIN0 0 +#define GPIOF_PIN1 1 +#define GPIOF_PIN2 2 +#define GPIOF_PIN3 3 +#define GPIOF_PIN4 4 +#define GPIOF_PIN5 5 +#define GPIOF_PIN6 6 +#define GPIOF_PIN7 7 +#define GPIOF_PIN8 8 +#define GPIOF_PIN9 9 +#define GPIOF_PIN10 10 +#define GPIOF_USB_FS_FAULT 11 +#define GPIOF_PIN12 12 +#define GPIOF_PIN13 13 +#define GPIOF_PIN14 14 +#define GPIOF_PIN15 15 + +#define GPIOG_PIN0 0 +#define GPIOG_PIN1 1 +#define GPIOG_PIN2 2 +#define GPIOG_PIN3 3 +#define GPIOG_PIN4 4 +#define GPIOG_PIN5 5 +#define GPIOG_PIN6 6 +#define GPIOG_PIN7 7 +#define GPIOG_PIN8 8 +#define GPIOG_PIN9 9 +#define GPIOG_SPI2_CS 10 +#define GPIOG_ETH_RMII_TXEN 11 +#define GPIOG_PIN12 12 +#define GPIOG_ETH_RMII_TXD0 13 +#define GPIOG_ETH_RMII_TXD1 14 +#define GPIOG_PIN15 15 + +#define GPIOH_OSC_IN 0 +#define GPIOH_OSC_OUT 1 +#define GPIOH_PIN2 2 +#define GPIOH_PIN3 3 +#define GPIOH_PIN4 4 +#define GPIOH_PIN5 5 +#define GPIOH_PIN6 6 +#define GPIOH_PIN7 7 +#define GPIOH_PIN8 8 +#define GPIOH_PIN9 9 +#define GPIOH_PIN10 10 +#define GPIOH_PIN11 11 +#define GPIOH_PIN12 12 +#define GPIOH_PIN13 13 +#define GPIOH_PIN14 14 +#define GPIOH_PIN15 15 + +#define GPIOI_PIN0 0 +#define GPIOI_PIN1 1 +#define GPIOI_PIN2 2 +#define GPIOI_PIN3 3 +#define GPIOI_PIN4 4 +#define GPIOI_PIN5 5 +#define GPIOI_PIN6 6 +#define GPIOI_PIN7 7 +#define GPIOI_PIN8 8 +#define GPIOI_PIN9 9 +#define GPIOI_PIN10 10 +#define GPIOI_PIN11 11 +#define GPIOI_PIN12 12 +#define GPIOI_PIN13 13 +#define GPIOI_PIN14 14 +#define GPIOI_PIN15 15 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON_WKUP (input floating). + * PA1 - ETH_RMII_REF_CLK (alternate 11). + * PA2 - ETH_RMII_MDIO (alternate 11). + * PA3 - ETH_RMII_MDINT (input floating). + * PA4 - PIN4 (input pullup). + * PA5 - PIN5 (input pullup). + * PA6 - PIN6 (input pullup). + * PA7 - ETH_RMII_CRS_DV (alternate 11). + * PA8 - USB_HS_BUSON (output pushpull maximum). + * PA9 - OTG_FS_VBUS (input pulldown). + * PA10 - OTG_FS_ID (alternate 10). + * PA11 - OTG_FS_DM (alternate 10). + * PA12 - OTG_FS_DP (alternate 10). + * PA13 - JTAG_TMS (alternate 0). + * PA14 - JTAG_TCK (alternate 0). + * PA15 - JTAG_TDI (alternate 0). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON_WKUP) | \ + PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_REF_CLK) |\ + PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_MDIO) |\ + PIN_MODE_INPUT(GPIOA_ETH_RMII_MDINT) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) |\ + PIN_MODE_OUTPUT(GPIOA_USB_HS_BUSON) | \ + PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) | \ + PIN_MODE_ALTERNATE(GPIOA_JTAG_TCK) | \ + PIN_MODE_ALTERNATE(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON_WKUP) |\ + PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_REF_CLK) |\ + PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDIO) |\ + PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDINT) |\ + PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_CRS_DV) |\ + PIN_OTYPE_PUSHPULL(GPIOA_USB_HS_BUSON) |\ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_VBUS) |\ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TMS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TCK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_BUTTON_WKUP) | \ + PIN_OSPEED_100M(GPIOA_ETH_RMII_REF_CLK) |\ + PIN_OSPEED_100M(GPIOA_ETH_RMII_MDIO) | \ + PIN_OSPEED_100M(GPIOA_ETH_RMII_MDINT) |\ + PIN_OSPEED_100M(GPIOA_PIN4) | \ + PIN_OSPEED_100M(GPIOA_PIN5) | \ + PIN_OSPEED_100M(GPIOA_PIN6) | \ + PIN_OSPEED_100M(GPIOA_ETH_RMII_CRS_DV) |\ + PIN_OSPEED_100M(GPIOA_USB_HS_BUSON) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_VBUS) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_100M(GPIOA_JTAG_TMS) | \ + PIN_OSPEED_100M(GPIOA_JTAG_TCK) | \ + PIN_OSPEED_100M(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON_WKUP) |\ + PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_REF_CLK) |\ + PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_MDIO) |\ + PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_MDINT) |\ + PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_CRS_DV) |\ + PIN_PUPDR_FLOATING(GPIOA_USB_HS_BUSON) |\ + PIN_PUPDR_PULLDOWN(GPIOA_OTG_FS_VBUS) |\ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_JTAG_TMS) | \ + PIN_PUPDR_PULLDOWN(GPIOA_JTAG_TCK) | \ + PIN_PUPDR_FLOATING(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON_WKUP) | \ + PIN_ODR_HIGH(GPIOA_ETH_RMII_REF_CLK) | \ + PIN_ODR_HIGH(GPIOA_ETH_RMII_MDIO) | \ + PIN_ODR_HIGH(GPIOA_ETH_RMII_MDINT) | \ + PIN_ODR_HIGH(GPIOA_PIN4) | \ + PIN_ODR_HIGH(GPIOA_PIN5) | \ + PIN_ODR_HIGH(GPIOA_PIN6) | \ + PIN_ODR_HIGH(GPIOA_ETH_RMII_CRS_DV) | \ + PIN_ODR_HIGH(GPIOA_USB_HS_BUSON) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_VBUS) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_HIGH(GPIOA_JTAG_TMS) | \ + PIN_ODR_HIGH(GPIOA_JTAG_TCK) | \ + PIN_ODR_HIGH(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON_WKUP, 0) | \ + PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11) |\ + PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11) | \ + PIN_AFIO_AF(GPIOA_ETH_RMII_MDINT, 0) | \ + PIN_AFIO_AF(GPIOA_PIN4, 0) | \ + PIN_AFIO_AF(GPIOA_PIN5, 0) | \ + PIN_AFIO_AF(GPIOA_PIN6, 0) | \ + PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_HS_BUSON, 0) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_VBUS, 0) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ + PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) | \ + PIN_AFIO_AF(GPIOA_JTAG_TCK, 0) | \ + PIN_AFIO_AF(GPIOA_JTAG_TDI, 0)) + +/* + * GPIOB setup: + * + * PB0 - USB_FS_BUSON (output pushpull maximum). + * PB1 - USB_HS_FAULT (input floating). + * PB2 - BOOT1 (input floating). + * PB3 - JTAG_TDO (alternate 0). + * PB4 - JTAG_TRST (alternate 0). + * PB5 - PIN5 (input pullup). + * PB6 - PIN6 (input pullup). + * PB7 - PIN7 (input pullup). + * PB8 - I2C1_SCL (alternate 4). + * PB9 - I2C1_SDA (alternate 4). + * PB10 - SPI2_SCK (alternate 5). + * PB11 - PIN11 (input pullup). + * PB12 - OTG_HS_ID (alternate 12). + * PB13 - OTG_HS_VBUS (input pulldown). + * PB14 - OTG_HS_DM (alternate 12). + * PB15 - OTG_HS_DP (alternate 12). + */ +#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_USB_FS_BUSON) | \ + PIN_MODE_INPUT(GPIOB_USB_HS_FAULT) | \ + PIN_MODE_INPUT(GPIOB_BOOT1) | \ + PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) | \ + PIN_MODE_ALTERNATE(GPIOB_JTAG_TRST) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) | \ + PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_USB_FS_BUSON) |\ + PIN_OTYPE_PUSHPULL(GPIOB_USB_HS_FAULT) |\ + PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TDO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TRST) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_USB_FS_BUSON) | \ + PIN_OSPEED_100M(GPIOB_USB_HS_FAULT) | \ + PIN_OSPEED_100M(GPIOB_BOOT1) | \ + PIN_OSPEED_100M(GPIOB_JTAG_TDO) | \ + PIN_OSPEED_100M(GPIOB_JTAG_TRST) | \ + PIN_OSPEED_100M(GPIOB_PIN5) | \ + PIN_OSPEED_100M(GPIOB_PIN6) | \ + PIN_OSPEED_100M(GPIOB_PIN7) | \ + PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_100M(GPIOB_SPI2_SCK) | \ + PIN_OSPEED_100M(GPIOB_PIN11) | \ + PIN_OSPEED_100M(GPIOB_OTG_HS_ID) | \ + PIN_OSPEED_100M(GPIOB_OTG_HS_VBUS) | \ + PIN_OSPEED_100M(GPIOB_OTG_HS_DM) | \ + PIN_OSPEED_100M(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_USB_FS_BUSON) |\ + PIN_PUPDR_FLOATING(GPIOB_USB_HS_FAULT) |\ + PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \ + PIN_PUPDR_FLOATING(GPIOB_JTAG_TDO) | \ + PIN_PUPDR_FLOATING(GPIOB_JTAG_TRST) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI2_SCK) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_ID) | \ + PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) | \ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_USB_FS_BUSON) | \ + PIN_ODR_HIGH(GPIOB_USB_HS_FAULT) | \ + PIN_ODR_HIGH(GPIOB_BOOT1) | \ + PIN_ODR_HIGH(GPIOB_JTAG_TDO) | \ + PIN_ODR_HIGH(GPIOB_JTAG_TRST) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_PIN6) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ + PIN_ODR_HIGH(GPIOB_SPI2_SCK) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_ID) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_DM) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_USB_FS_BUSON, 0) | \ + PIN_AFIO_AF(GPIOB_USB_HS_FAULT, 0) | \ + PIN_AFIO_AF(GPIOB_BOOT1, 0) | \ + PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) | \ + PIN_AFIO_AF(GPIOB_JTAG_TRST, 0) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0) | \ + PIN_AFIO_AF(GPIOB_PIN6, 0) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) | \ + PIN_AFIO_AF(GPIOB_SPI2_SCK, 5) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_VBUS, 0) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12)) + +/* + * GPIOC setup: + * + * PC0 - PIN0 (input pullup). + * PC1 - ETH_RMII_MDC (alternate 11). + * PC2 - SPI2_MISO (alternate 5). + * PC3 - SPI2_MOSI (alternate 5). + * PC4 - ETH_RMII_RXD0 (alternate 11). + * PC5 - ETH_RMII_RXD1 (alternate 11). + * PC6 - USART6_TX (alternate 8). + * PC7 - USART6_RX (alternate 8). + * PC8 - SD_D0 (alternate 12). + * PC9 - SD_D1 (alternate 12). + * PC10 - SD_D2 (alternate 12). + * PC11 - SD_D3 (alternate 12). + * PC12 - SD_CLK (alternate 12). + * PC13 - LED (output pushpull maximum). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_MDC) |\ + PIN_MODE_ALTERNATE(GPIOC_SPI2_MISO) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI2_MOSI) | \ + PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD0) |\ + PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD1) |\ + PIN_MODE_ALTERNATE(GPIOC_USART6_TX) | \ + PIN_MODE_ALTERNATE(GPIOC_USART6_RX) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_D0) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_D1) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_D2) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_D3) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_CLK) | \ + PIN_MODE_OUTPUT(GPIOC_LED) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_MDC) |\ + PIN_OTYPE_PUSHPULL(GPIOC_SPI2_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI2_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_RXD0) |\ + PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_RXD1) |\ + PIN_OTYPE_PUSHPULL(GPIOC_USART6_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOC_USART6_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LED) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_PIN0) | \ + PIN_OSPEED_100M(GPIOC_ETH_RMII_MDC) | \ + PIN_OSPEED_100M(GPIOC_SPI2_MISO) | \ + PIN_OSPEED_100M(GPIOC_SPI2_MOSI) | \ + PIN_OSPEED_100M(GPIOC_ETH_RMII_RXD0) | \ + PIN_OSPEED_100M(GPIOC_ETH_RMII_RXD1) | \ + PIN_OSPEED_100M(GPIOC_USART6_TX) | \ + PIN_OSPEED_100M(GPIOC_USART6_RX) | \ + PIN_OSPEED_100M(GPIOC_SD_D0) | \ + PIN_OSPEED_100M(GPIOC_SD_D1) | \ + PIN_OSPEED_100M(GPIOC_SD_D2) | \ + PIN_OSPEED_100M(GPIOC_SD_D3) | \ + PIN_OSPEED_100M(GPIOC_SD_CLK) | \ + PIN_OSPEED_100M(GPIOC_LED) | \ + PIN_OSPEED_100M(GPIOC_OSC32_IN) | \ + PIN_OSPEED_100M(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_MDC) |\ + PIN_PUPDR_FLOATING(GPIOC_SPI2_MISO) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI2_MOSI) | \ + PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_RXD0) |\ + PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_RXD1) |\ + PIN_PUPDR_FLOATING(GPIOC_USART6_TX) | \ + PIN_PUPDR_FLOATING(GPIOC_USART6_RX) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_D0) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_D1) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_D2) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_D3) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_CLK) | \ + PIN_PUPDR_FLOATING(GPIOC_LED) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ + PIN_ODR_HIGH(GPIOC_ETH_RMII_MDC) | \ + PIN_ODR_HIGH(GPIOC_SPI2_MISO) | \ + PIN_ODR_HIGH(GPIOC_SPI2_MOSI) | \ + PIN_ODR_HIGH(GPIOC_ETH_RMII_RXD0) | \ + PIN_ODR_HIGH(GPIOC_ETH_RMII_RXD1) | \ + PIN_ODR_HIGH(GPIOC_USART6_TX) | \ + PIN_ODR_HIGH(GPIOC_USART6_RX) | \ + PIN_ODR_HIGH(GPIOC_SD_D0) | \ + PIN_ODR_HIGH(GPIOC_SD_D1) | \ + PIN_ODR_HIGH(GPIOC_SD_D2) | \ + PIN_ODR_HIGH(GPIOC_SD_D3) | \ + PIN_ODR_HIGH(GPIOC_SD_CLK) | \ + PIN_ODR_HIGH(GPIOC_LED) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \ + PIN_AFIO_AF(GPIOC_ETH_RMII_MDC, 11) | \ + PIN_AFIO_AF(GPIOC_SPI2_MISO, 5) | \ + PIN_AFIO_AF(GPIOC_SPI2_MOSI, 5) | \ + PIN_AFIO_AF(GPIOC_ETH_RMII_RXD0, 11) | \ + PIN_AFIO_AF(GPIOC_ETH_RMII_RXD1, 11) | \ + PIN_AFIO_AF(GPIOC_USART6_TX, 8) | \ + PIN_AFIO_AF(GPIOC_USART6_RX, 8)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SD_D0, 12) | \ + PIN_AFIO_AF(GPIOC_SD_D1, 12) | \ + PIN_AFIO_AF(GPIOC_SD_D2, 12) | \ + PIN_AFIO_AF(GPIOC_SD_D3, 12) | \ + PIN_AFIO_AF(GPIOC_SD_CLK, 12) | \ + PIN_AFIO_AF(GPIOC_LED, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - SD_CMD (alternate 12). + * PD3 - PIN3 (input pullup). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - PIN12 (input pullup). + * PD13 - PIN13 (input pullup). + * PD14 - PIN14 (input pullup). + * PD15 - PIN15 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_ALTERNATE(GPIOD_SD_CMD) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \ + PIN_OSPEED_100M(GPIOD_PIN1) | \ + PIN_OSPEED_100M(GPIOD_SD_CMD) | \ + PIN_OSPEED_100M(GPIOD_PIN3) | \ + PIN_OSPEED_100M(GPIOD_PIN4) | \ + PIN_OSPEED_100M(GPIOD_PIN5) | \ + PIN_OSPEED_100M(GPIOD_PIN6) | \ + PIN_OSPEED_100M(GPIOD_PIN7) | \ + PIN_OSPEED_100M(GPIOD_PIN8) | \ + PIN_OSPEED_100M(GPIOD_PIN9) | \ + PIN_OSPEED_100M(GPIOD_PIN10) | \ + PIN_OSPEED_100M(GPIOD_PIN11) | \ + PIN_OSPEED_100M(GPIOD_PIN12) | \ + PIN_OSPEED_100M(GPIOD_PIN13) | \ + PIN_OSPEED_100M(GPIOD_PIN14) | \ + PIN_OSPEED_100M(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOD_SD_CMD) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_SD_CMD) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0) | \ + PIN_AFIO_AF(GPIOD_SD_CMD, 12) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0)) + +/* + * GPIOE setup: + * + * PE0 - PIN0 (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - PIN2 (input pullup). + * PE3 - PIN3 (input pullup). + * PE4 - PIN4 (input pullup). + * PE5 - PIN5 (input pullup). + * PE6 - PIN6 (input pullup). + * PE7 - PIN7 (input pullup). + * PE8 - PIN8 (input pullup). + * PE9 - PIN9 (input pullup). + * PE10 - PIN10 (input pullup). + * PE11 - PIN11 (input pullup). + * PE12 - PIN12 (input pullup). + * PE13 - PIN13 (input pullup). + * PE14 - PIN14 (input pullup). + * PE15 - PIN15 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_PIN0) | \ + PIN_OSPEED_100M(GPIOE_PIN1) | \ + PIN_OSPEED_100M(GPIOE_PIN2) | \ + PIN_OSPEED_100M(GPIOE_PIN3) | \ + PIN_OSPEED_100M(GPIOE_PIN4) | \ + PIN_OSPEED_100M(GPIOE_PIN5) | \ + PIN_OSPEED_100M(GPIOE_PIN6) | \ + PIN_OSPEED_100M(GPIOE_PIN7) | \ + PIN_OSPEED_100M(GPIOE_PIN8) | \ + PIN_OSPEED_100M(GPIOE_PIN9) | \ + PIN_OSPEED_100M(GPIOE_PIN10) | \ + PIN_OSPEED_100M(GPIOE_PIN11) | \ + PIN_OSPEED_100M(GPIOE_PIN12) | \ + PIN_OSPEED_100M(GPIOE_PIN13) | \ + PIN_OSPEED_100M(GPIOE_PIN14) | \ + PIN_OSPEED_100M(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (input pullup). + * PF1 - PIN1 (input pullup). + * PF2 - PIN2 (input pullup). + * PF3 - PIN3 (input pullup). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - PIN7 (input pullup). + * PF8 - PIN8 (input pullup). + * PF9 - PIN9 (input pullup). + * PF10 - PIN10 (input pullup). + * PF11 - USB_FS_FAULT (input floating). + * PF12 - PIN12 (input pullup). + * PF13 - PIN13 (input pullup). + * PF14 - PIN14 (input pullup). + * PF15 - PIN15 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_USB_FS_FAULT) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_USB_FS_FAULT) |\ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \ + PIN_OSPEED_100M(GPIOF_PIN1) | \ + PIN_OSPEED_100M(GPIOF_PIN2) | \ + PIN_OSPEED_100M(GPIOF_PIN3) | \ + PIN_OSPEED_100M(GPIOF_PIN4) | \ + PIN_OSPEED_100M(GPIOF_PIN5) | \ + PIN_OSPEED_100M(GPIOF_PIN6) | \ + PIN_OSPEED_100M(GPIOF_PIN7) | \ + PIN_OSPEED_100M(GPIOF_PIN8) | \ + PIN_OSPEED_100M(GPIOF_PIN9) | \ + PIN_OSPEED_100M(GPIOF_PIN10) | \ + PIN_OSPEED_100M(GPIOF_USB_FS_FAULT) | \ + PIN_OSPEED_100M(GPIOF_PIN12) | \ + PIN_OSPEED_100M(GPIOF_PIN13) | \ + PIN_OSPEED_100M(GPIOF_PIN14) | \ + PIN_OSPEED_100M(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOF_USB_FS_FAULT) |\ + PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_USB_FS_FAULT) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0) | \ + PIN_AFIO_AF(GPIOF_USB_FS_FAULT, 0) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (input pullup). + * PG1 - PIN1 (input pullup). + * PG2 - PIN2 (input pullup). + * PG3 - PIN3 (input pullup). + * PG4 - PIN4 (input pullup). + * PG5 - PIN5 (input pullup). + * PG6 - PIN6 (input pullup). + * PG7 - PIN7 (input pullup). + * PG8 - PIN8 (input pullup). + * PG9 - PIN9 (input pullup). + * PG10 - SPI2_CS (output pushpull maximum). + * PG11 - ETH_RMII_TXEN (alternate 11). + * PG12 - PIN12 (input pullup). + * PG13 - ETH_RMII_TXD0 (alternate 11). + * PG14 - ETH_RMII_TXD1 (alternate 11). + * PG15 - PIN15 (input pullup). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ + PIN_MODE_INPUT(GPIOG_PIN1) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_PIN6) | \ + PIN_MODE_INPUT(GPIOG_PIN7) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_OUTPUT(GPIOG_SPI2_CS) | \ + PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXEN) |\ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD0) |\ + PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD1) |\ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SPI2_CS) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXEN) |\ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD0) |\ + PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD1) |\ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \ + PIN_OSPEED_100M(GPIOG_PIN1) | \ + PIN_OSPEED_100M(GPIOG_PIN2) | \ + PIN_OSPEED_100M(GPIOG_PIN3) | \ + PIN_OSPEED_100M(GPIOG_PIN4) | \ + PIN_OSPEED_100M(GPIOG_PIN5) | \ + PIN_OSPEED_100M(GPIOG_PIN6) | \ + PIN_OSPEED_100M(GPIOG_PIN7) | \ + PIN_OSPEED_100M(GPIOG_PIN8) | \ + PIN_OSPEED_100M(GPIOG_PIN9) | \ + PIN_OSPEED_100M(GPIOG_SPI2_CS) | \ + PIN_OSPEED_100M(GPIOG_ETH_RMII_TXEN) | \ + PIN_OSPEED_100M(GPIOG_PIN12) | \ + PIN_OSPEED_100M(GPIOG_ETH_RMII_TXD0) | \ + PIN_OSPEED_100M(GPIOG_ETH_RMII_TXD1) | \ + PIN_OSPEED_100M(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOG_SPI2_CS) | \ + PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXEN) |\ + PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD0) |\ + PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD1) |\ + PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_SPI2_CS) | \ + PIN_ODR_HIGH(GPIOG_ETH_RMII_TXEN) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD0) | \ + PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD1) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0) | \ + PIN_AFIO_AF(GPIOG_SPI2_CS, 0) | \ + PIN_AFIO_AF(GPIOG_ETH_RMII_TXEN, 11) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0) | \ + PIN_AFIO_AF(GPIOG_ETH_RMII_TXD0, 11) | \ + PIN_AFIO_AF(GPIOG_ETH_RMII_TXD1, 11) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \ + PIN_OSPEED_100M(GPIOH_OSC_OUT) | \ + PIN_OSPEED_100M(GPIOH_PIN2) | \ + PIN_OSPEED_100M(GPIOH_PIN3) | \ + PIN_OSPEED_100M(GPIOH_PIN4) | \ + PIN_OSPEED_100M(GPIOH_PIN5) | \ + PIN_OSPEED_100M(GPIOH_PIN6) | \ + PIN_OSPEED_100M(GPIOH_PIN7) | \ + PIN_OSPEED_100M(GPIOH_PIN8) | \ + PIN_OSPEED_100M(GPIOH_PIN9) | \ + PIN_OSPEED_100M(GPIOH_PIN10) | \ + PIN_OSPEED_100M(GPIOH_PIN11) | \ + PIN_OSPEED_100M(GPIOH_PIN12) | \ + PIN_OSPEED_100M(GPIOH_PIN13) | \ + PIN_OSPEED_100M(GPIOH_PIN14) | \ + PIN_OSPEED_100M(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \ + PIN_OSPEED_100M(GPIOI_PIN1) | \ + PIN_OSPEED_100M(GPIOI_PIN2) | \ + PIN_OSPEED_100M(GPIOI_PIN3) | \ + PIN_OSPEED_100M(GPIOI_PIN4) | \ + PIN_OSPEED_100M(GPIOI_PIN5) | \ + PIN_OSPEED_100M(GPIOI_PIN6) | \ + PIN_OSPEED_100M(GPIOI_PIN7) | \ + PIN_OSPEED_100M(GPIOI_PIN8) | \ + PIN_OSPEED_100M(GPIOI_PIN9) | \ + PIN_OSPEED_100M(GPIOI_PIN10) | \ + PIN_OSPEED_100M(GPIOI_PIN11) | \ + PIN_OSPEED_100M(GPIOI_PIN12) | \ + PIN_OSPEED_100M(GPIOI_PIN13) | \ + PIN_OSPEED_100M(GPIOI_PIN14) | \ + PIN_OSPEED_100M(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/OLIMEX_STM32_H407/board.mk b/os/hal/boards/OLIMEX_STM32_H407/board.mk new file mode 100644 index 000000000..8bd37d59d --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_H407/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_H407/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_H407 diff --git a/os/hal/boards/OLIMEX_STM32_H407/cfg/board.chcfg b/os/hal/boards/OLIMEX_STM32_H407/cfg/board.chcfg new file mode 100644 index 000000000..edf298a2e --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_H407/cfg/board.chcfg @@ -0,0 +1,336 @@ + + + + + resources/gencfg/processors/boards/stm32f4xx/templates + .. + + Olimex STM32-H407 + OLIMEX_STM32_H407 + + + + + + + MII_KS8721_ID + RMII + + STM32F40_41xxx + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/os/hal/boards/OLIMEX_STM32_P407/board.h b/os/hal/boards/OLIMEX_STM32_P407/board.h index 66279a8f9..c43368dfd 100644 --- a/os/hal/boards/OLIMEX_STM32_P407/board.h +++ b/os/hal/boards/OLIMEX_STM32_P407/board.h @@ -49,9 +49,9 @@ #define STM32_VDD 330 /* - * MCU type as defined in the ST header file stm32f4xx.h. + * MCU type as defined in the ST header. */ -#define STM32F4XX +#define STM32F40_41xxx /* * IO pins assignments. diff --git a/os/hal/boards/ST_STM32F429I_DISCOVERY/board.c b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.c new file mode 100644 index 000000000..c76d97d55 --- /dev/null +++ b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.c @@ -0,0 +1,107 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief SDC card write protection detection. + */ +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/os/hal/boards/ST_STM32F429I_DISCOVERY/board.h b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.h new file mode 100644 index 000000000..b8191e6f7 --- /dev/null +++ b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.h @@ -0,0 +1,1297 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32F429I-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F429I_DISCOVERY +#define BOARD_NAME "STMicroelectronics STM32F429I-Discovery" + + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 0 +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000 +#endif + + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300 + +/* + * MCU type as defined in the ST header. + */ +#define STM32F429_439xx + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0 +#define GPIOA_MEMS_INT1 1 +#define GPIOA_MEMS_INT2 2 +#define GPIOA_LCD_B5 3 +#define GPIOA_LCD_VSYNC 4 +#define GPIOA_PIN5 5 +#define GPIOA_LCD_G2 6 +#define GPIOA_ACP_RST 7 +#define GPIOA_I2C3_SCL 8 +#define GPIOA_PIN9 9 +#define GPIOA_PIN10 10 +#define GPIOA_LCD_R4 11 +#define GPIOA_LCD_R5 12 +#define GPIOA_SWDIO 13 +#define GPIOA_SWCLK 14 +#define GPIOA_TP_INT 15 + +#define GPIOB_LCD_R3 0 +#define GPIOB_LCD_R6 1 +#define GPIOB_BOOT1 2 +#define GPIOB_SWO 3 +#define GPIOB_PIN4 4 +#define GPIOB_FMC_SDCKE1 5 +#define GPIOB_FMC_SDNE1 6 +#define GPIOB_PIN7 7 +#define GPIOB_LCD_B6 8 +#define GPIOB_LCD_B7 9 +#define GPIOB_LCD_G4 10 +#define GPIOB_LCD_G5 11 +#define GPIOB_OTG_HS_ID 12 +#define GPIOB_OTG_HS_VBUS 13 +#define GPIOB_OTG_HS_DM 14 +#define GPIOB_OTG_HS_DP 15 + +#define GPIOC_FMC_SDNWE 0 +#define GPIOC_SPI5_MEMS_CS 1 +#define GPIOC_SPI5_LCD_CS 2 +#define GPIOC_PIN3 3 +#define GPIOC_OTG_HS_PSO 4 +#define GPIOC_OTG_HS_OC 5 +#define GPIOC_LCD_HSYNC 6 +#define GPIOC_LCD_G6 7 +#define GPIOC_PIN8 8 +#define GPIOC_I2C3_SDA 9 +#define GPIOC_LCD_R2 10 +#define GPIOC_PIN11 11 +#define GPIOC_PIN12 12 +#define GPIOC_PIN13 13 +#define GPIOC_OSC32_IN 14 +#define GPIOC_OSC32_OUT 15 + +#define GPIOD_FMC_D2 0 +#define GPIOD_FMC_D3 1 +#define GPIOD_PIN2 2 +#define GPIOD_LCD_G7 3 +#define GPIOD_PIN4 4 +#define GPIOD_PIN5 5 +#define GPIOD_LCD_B2 6 +#define GPIOD_PIN7 7 +#define GPIOD_FMC_D13 8 +#define GPIOD_FMC_D14 9 +#define GPIOD_FMC_D15 10 +#define GPIOD_LCD_TE 11 +#define GPIOD_LCD_RDX 12 +#define GPIOD_LCD_WRX 13 +#define GPIOD_FMC_D0 14 +#define GPIOD_FMC_D1 15 + +#define GPIOE_FMC_NBL0 0 +#define GPIOE_FMC_NBL1 1 +#define GPIOE_PIN2 2 +#define GPIOE_PIN3 3 +#define GPIOE_PIN4 4 +#define GPIOE_PIN5 5 +#define GPIOE_PIN6 6 +#define GPIOE_FMC_D4 7 +#define GPIOE_FMC_D5 8 +#define GPIOE_FMC_D6 9 +#define GPIOE_FMC_D7 10 +#define GPIOE_FMC_D8 11 +#define GPIOE_FMC_D9 12 +#define GPIOE_FMC_D10 13 +#define GPIOE_FMC_D11 14 +#define GPIOE_FMC_D12 15 + +#define GPIOF_FMC_A0 0 +#define GPIOF_FMC_A1 1 +#define GPIOF_FMC_A2 2 +#define GPIOF_FMC_A3 3 +#define GPIOF_FMC_A4 4 +#define GPIOF_FMC_A5 5 +#define GPIOF_PIN6 6 +#define GPIOF_LCD_DCX 7 +#define GPIOF_SPI5_MISO 8 +#define GPIOF_SPI5_MOSI 9 +#define GPIOF_LCD_DE 10 +#define GPIOF_FMC_SDNRAS 11 +#define GPIOF_FMC_A6 12 +#define GPIOF_FMC_A7 13 +#define GPIOF_FMC_A8 14 +#define GPIOF_FMC_A9 15 + +#define GPIOG_FMC_A10 0 +#define GPIOG_FMC_A11 1 +#define GPIOG_PIN2 2 +#define GPIOG_PIN3 3 +#define GPIOG_FMC_BA0 4 +#define GPIOG_FMC_BA1 5 +#define GPIOG_LCD_R7 6 +#define GPIOG_LCD_CLK 7 +#define GPIOG_FMC_SDCLK 8 +#define GPIOG_PIN9 9 +#define GPIOG_LCD_G3 10 +#define GPIOG_LCD_B3 11 +#define GPIOG_LCD_B4 12 +#define GPIOG_LED3_GREEN 13 +#define GPIOG_LED4_RED 14 +#define GPIOG_FMC_SDNCAS 15 + +#define GPIOH_OSC_IN 0 +#define GPIOH_OSC_OUT 1 +#define GPIOH_PIN2 2 +#define GPIOH_PIN3 3 +#define GPIOH_PIN4 4 +#define GPIOH_PIN5 5 +#define GPIOH_PIN6 6 +#define GPIOH_PIN7 7 +#define GPIOH_PIN8 8 +#define GPIOH_PIN9 9 +#define GPIOH_PIN10 10 +#define GPIOH_PIN11 11 +#define GPIOH_PIN12 12 +#define GPIOH_PIN13 13 +#define GPIOH_PIN14 14 +#define GPIOH_PIN15 15 + +#define GPIOI_PIN0 0 +#define GPIOI_PIN1 1 +#define GPIOI_PIN2 2 +#define GPIOI_PIN3 3 +#define GPIOI_PIN4 4 +#define GPIOI_PIN5 5 +#define GPIOI_PIN6 6 +#define GPIOI_PIN7 7 +#define GPIOI_PIN8 8 +#define GPIOI_PIN9 9 +#define GPIOI_PIN10 10 +#define GPIOI_PIN11 11 +#define GPIOI_PIN12 12 +#define GPIOI_PIN13 13 +#define GPIOI_PIN14 14 +#define GPIOI_PIN15 15 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON (input floating). + * PA1 - MEMS_INT1 (input floating). + * PA2 - MEMS_INT2 (input floating). + * PA3 - LCD_B5 (alternate 14). + * PA4 - LCD_VSYNC (alternate 14). + * PA5 - PIN5 (input pullup). + * PA6 - LCD_G2 (alternate 14). + * PA7 - ACP_RST (input pullup). + * PA8 - I2C3_SCL (alternate 4). + * PA9 - PIN9 (input pullup). + * PA10 - PIN10 (input pullup). + * PA11 - LCD_R4 (alternate 14). + * PA12 - LCD_R5 (alternate 14). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - TP_INT (input floating). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(GPIOA_MEMS_INT1) | \ + PIN_MODE_INPUT(GPIOA_MEMS_INT2) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_B5) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_VSYNC) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_G2) | \ + PIN_MODE_INPUT(GPIOA_ACP_RST) | \ + PIN_MODE_ALTERNATE(GPIOA_I2C3_SCL) | \ + PIN_MODE_INPUT(GPIOA_PIN9) | \ + PIN_MODE_INPUT(GPIOA_PIN10) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_R4) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_R5) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_TP_INT)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOA_MEMS_INT1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_MEMS_INT2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_B5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_VSYNC) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_G2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ACP_RST) | \ + PIN_OTYPE_OPENDRAIN(GPIOA_I2C3_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_R4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_R5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_TP_INT)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_BUTTON) | \ + PIN_OSPEED_2M(GPIOA_MEMS_INT1) | \ + PIN_OSPEED_2M(GPIOA_MEMS_INT2) | \ + PIN_OSPEED_100M(GPIOA_LCD_B5) | \ + PIN_OSPEED_100M(GPIOA_LCD_VSYNC) | \ + PIN_OSPEED_2M(GPIOA_PIN5) | \ + PIN_OSPEED_100M(GPIOA_LCD_G2) | \ + PIN_OSPEED_2M(GPIOA_ACP_RST) | \ + PIN_OSPEED_100M(GPIOA_I2C3_SCL) | \ + PIN_OSPEED_2M(GPIOA_PIN9) | \ + PIN_OSPEED_2M(GPIOA_PIN10) | \ + PIN_OSPEED_100M(GPIOA_LCD_R4) | \ + PIN_OSPEED_100M(GPIOA_LCD_R5) | \ + PIN_OSPEED_100M(GPIOA_SWDIO) | \ + PIN_OSPEED_100M(GPIOA_SWCLK) | \ + PIN_OSPEED_2M(GPIOA_TP_INT)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ + PIN_PUPDR_FLOATING(GPIOA_MEMS_INT1) | \ + PIN_PUPDR_FLOATING(GPIOA_MEMS_INT2) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_B5) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_VSYNC) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_G2) | \ + PIN_PUPDR_PULLUP(GPIOA_ACP_RST) | \ + PIN_PUPDR_FLOATING(GPIOA_I2C3_SCL) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_R4) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_R5) | \ + PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ + PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PUPDR_FLOATING(GPIOA_TP_INT)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ + PIN_ODR_HIGH(GPIOA_MEMS_INT1) | \ + PIN_ODR_HIGH(GPIOA_MEMS_INT2) | \ + PIN_ODR_HIGH(GPIOA_LCD_B5) | \ + PIN_ODR_HIGH(GPIOA_LCD_VSYNC) | \ + PIN_ODR_HIGH(GPIOA_PIN5) | \ + PIN_ODR_HIGH(GPIOA_LCD_G2) | \ + PIN_ODR_HIGH(GPIOA_ACP_RST) | \ + PIN_ODR_HIGH(GPIOA_I2C3_SCL) | \ + PIN_ODR_HIGH(GPIOA_PIN9) | \ + PIN_ODR_HIGH(GPIOA_PIN10) | \ + PIN_ODR_HIGH(GPIOA_LCD_R4) | \ + PIN_ODR_HIGH(GPIOA_LCD_R5) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_TP_INT)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \ + PIN_AFIO_AF(GPIOA_MEMS_INT1, 0) | \ + PIN_AFIO_AF(GPIOA_MEMS_INT2, 0) | \ + PIN_AFIO_AF(GPIOA_LCD_B5, 14) | \ + PIN_AFIO_AF(GPIOA_LCD_VSYNC, 14) | \ + PIN_AFIO_AF(GPIOA_PIN5, 0) | \ + PIN_AFIO_AF(GPIOA_LCD_G2, 14) | \ + PIN_AFIO_AF(GPIOA_ACP_RST, 0)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_I2C3_SCL, 4) | \ + PIN_AFIO_AF(GPIOA_PIN9, 0) | \ + PIN_AFIO_AF(GPIOA_PIN10, 0) | \ + PIN_AFIO_AF(GPIOA_LCD_R4, 14) | \ + PIN_AFIO_AF(GPIOA_LCD_R5, 14) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0) | \ + PIN_AFIO_AF(GPIOA_TP_INT, 0)) + +/* + * GPIOB setup: + * + * PB0 - LCD_R3 (alternate 14). + * PB1 - LCD_R6 (alternate 14). + * PB2 - BOOT1 (input pullup). + * PB3 - SWO (alternate 0). + * PB4 - PIN4 (input pullup). + * PB5 - FMC_SDCKE1 (alternate 12). + * PB6 - FMC_SDNE1 (alternate 12). + * PB7 - PIN7 (input pullup). + * PB8 - LCD_B6 (alternate 14). + * PB9 - LCD_B7 (alternate 14). + * PB10 - LCD_G4 (alternate 14). + * PB11 - LCD_G5 (alternate 14). + * PB12 - OTG_HS_ID (alternate 12). + * PB13 - OTG_HS_VBUS (input pulldown). + * PB14 - OTG_HS_DM (alternate 12). + * PB15 - OTG_HS_DP (alternate 12). + */ +#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(GPIOB_LCD_R3) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_R6) | \ + PIN_MODE_INPUT(GPIOB_BOOT1) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_ALTERNATE(GPIOB_FMC_SDCKE1) | \ + PIN_MODE_ALTERNATE(GPIOB_FMC_SDNE1) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_B6) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_B7) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_G4) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_G5) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) | \ + PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_LCD_R3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_R6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_FMC_SDCKE1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_FMC_SDNE1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_B6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_B7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_G4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_G5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_LCD_R3) | \ + PIN_OSPEED_100M(GPIOB_LCD_R6) | \ + PIN_OSPEED_100M(GPIOB_BOOT1) | \ + PIN_OSPEED_100M(GPIOB_SWO) | \ + PIN_OSPEED_2M(GPIOB_PIN4) | \ + PIN_OSPEED_100M(GPIOB_FMC_SDCKE1) | \ + PIN_OSPEED_100M(GPIOB_FMC_SDNE1) | \ + PIN_OSPEED_2M(GPIOB_PIN7) | \ + PIN_OSPEED_100M(GPIOB_LCD_B6) | \ + PIN_OSPEED_100M(GPIOB_LCD_B7) | \ + PIN_OSPEED_100M(GPIOB_LCD_G4) | \ + PIN_OSPEED_100M(GPIOB_LCD_G5) | \ + PIN_OSPEED_100M(GPIOB_OTG_HS_ID) | \ + PIN_OSPEED_2M(GPIOB_OTG_HS_VBUS) | \ + PIN_OSPEED_100M(GPIOB_OTG_HS_DM) | \ + PIN_OSPEED_100M(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_LCD_R3) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_R6) | \ + PIN_PUPDR_PULLUP(GPIOB_BOOT1) | \ + PIN_PUPDR_FLOATING(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOB_FMC_SDCKE1) | \ + PIN_PUPDR_FLOATING(GPIOB_FMC_SDNE1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_B6) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_B7) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_G4) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_G5) | \ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_ID) | \ + PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) | \ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_LCD_R3) | \ + PIN_ODR_HIGH(GPIOB_LCD_R6) | \ + PIN_ODR_HIGH(GPIOB_BOOT1) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_PIN4) | \ + PIN_ODR_HIGH(GPIOB_FMC_SDCKE1) | \ + PIN_ODR_HIGH(GPIOB_FMC_SDNE1) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_LCD_B6) | \ + PIN_ODR_HIGH(GPIOB_LCD_B7) | \ + PIN_ODR_HIGH(GPIOB_LCD_G4) | \ + PIN_ODR_HIGH(GPIOB_LCD_G5) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_ID) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_DM) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_LCD_R3, 14) | \ + PIN_AFIO_AF(GPIOB_LCD_R6, 14) | \ + PIN_AFIO_AF(GPIOB_BOOT1, 0) | \ + PIN_AFIO_AF(GPIOB_SWO, 0) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0) | \ + PIN_AFIO_AF(GPIOB_FMC_SDCKE1, 12) | \ + PIN_AFIO_AF(GPIOB_FMC_SDNE1, 12) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_LCD_B6, 14) | \ + PIN_AFIO_AF(GPIOB_LCD_B7, 14) | \ + PIN_AFIO_AF(GPIOB_LCD_G4, 14) | \ + PIN_AFIO_AF(GPIOB_LCD_G5, 14) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_VBUS, 0) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12)) + +/* + * GPIOC setup: + * + * PC0 - FMC_SDNWE (alternate 12). + * PC1 - SPI5_MEMS_CS (output pushpull maximum). + * PC2 - SPI5_LCD_CS (output pushpull maximum). + * PC3 - PIN3 (input pullup). + * PC4 - OTG_HS_PSO (output pushpull maximum). + * PC5 - OTG_HS_OC (input floating). + * PC6 - LCD_HSYNC (alternate 14). + * PC7 - LCD_G6 (alternate 14). + * PC8 - PIN8 (input pullup). + * PC9 - I2C3_SDA (alternate 4). + * PC10 - LCD_R2 (alternate 14). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - PIN13 (input pullup). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_ALTERNATE(GPIOC_FMC_SDNWE) | \ + PIN_MODE_OUTPUT(GPIOC_SPI5_MEMS_CS) | \ + PIN_MODE_OUTPUT(GPIOC_SPI5_LCD_CS) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_OUTPUT(GPIOC_OTG_HS_PSO) | \ + PIN_MODE_INPUT(GPIOC_OTG_HS_OC) | \ + PIN_MODE_ALTERNATE(GPIOC_LCD_HSYNC) | \ + PIN_MODE_ALTERNATE(GPIOC_LCD_G6) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOC_I2C3_SDA) | \ + PIN_MODE_ALTERNATE(GPIOC_LCD_R2) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_FMC_SDNWE) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI5_MEMS_CS) |\ + PIN_OTYPE_PUSHPULL(GPIOC_SPI5_LCD_CS) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OTG_HS_PSO) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OTG_HS_OC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LCD_HSYNC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LCD_G6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_OPENDRAIN(GPIOC_I2C3_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LCD_R2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_FMC_SDNWE) | \ + PIN_OSPEED_100M(GPIOC_SPI5_MEMS_CS) | \ + PIN_OSPEED_100M(GPIOC_SPI5_LCD_CS) | \ + PIN_OSPEED_2M(GPIOC_PIN3) | \ + PIN_OSPEED_100M(GPIOC_OTG_HS_PSO) | \ + PIN_OSPEED_100M(GPIOC_OTG_HS_OC) | \ + PIN_OSPEED_100M(GPIOC_LCD_HSYNC) | \ + PIN_OSPEED_100M(GPIOC_LCD_G6) | \ + PIN_OSPEED_2M(GPIOC_PIN8) | \ + PIN_OSPEED_100M(GPIOC_I2C3_SDA) | \ + PIN_OSPEED_100M(GPIOC_LCD_R2) | \ + PIN_OSPEED_2M(GPIOC_PIN11) | \ + PIN_OSPEED_2M(GPIOC_PIN12) | \ + PIN_OSPEED_2M(GPIOC_PIN13) | \ + PIN_OSPEED_100M(GPIOC_OSC32_IN) | \ + PIN_OSPEED_100M(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_FMC_SDNWE) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI5_MEMS_CS) |\ + PIN_PUPDR_FLOATING(GPIOC_SPI5_LCD_CS) |\ + PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOC_OTG_HS_PSO) | \ + PIN_PUPDR_FLOATING(GPIOC_OTG_HS_OC) | \ + PIN_PUPDR_FLOATING(GPIOC_LCD_HSYNC) | \ + PIN_PUPDR_FLOATING(GPIOC_LCD_G6) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOC_I2C3_SDA) | \ + PIN_PUPDR_FLOATING(GPIOC_LCD_R2) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_FMC_SDNWE) | \ + PIN_ODR_HIGH(GPIOC_SPI5_MEMS_CS) | \ + PIN_ODR_HIGH(GPIOC_SPI5_LCD_CS) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_OTG_HS_PSO) | \ + PIN_ODR_HIGH(GPIOC_OTG_HS_OC) | \ + PIN_ODR_HIGH(GPIOC_LCD_HSYNC) | \ + PIN_ODR_HIGH(GPIOC_LCD_G6) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_I2C3_SDA) | \ + PIN_ODR_HIGH(GPIOC_LCD_R2) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_FMC_SDNWE, 12) | \ + PIN_AFIO_AF(GPIOC_SPI5_MEMS_CS, 0) | \ + PIN_AFIO_AF(GPIOC_SPI5_LCD_CS, 0) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0) | \ + PIN_AFIO_AF(GPIOC_OTG_HS_PSO, 0) | \ + PIN_AFIO_AF(GPIOC_OTG_HS_OC, 0) | \ + PIN_AFIO_AF(GPIOC_LCD_HSYNC, 14) | \ + PIN_AFIO_AF(GPIOC_LCD_G6, 14)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \ + PIN_AFIO_AF(GPIOC_I2C3_SDA, 4) | \ + PIN_AFIO_AF(GPIOC_LCD_R2, 14) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0)) + +/* + * GPIOD setup: + * + * PD0 - FMC_D2 (alternate 12). + * PD1 - FMC_D3 (alternate 12). + * PD2 - PIN2 (input pullup). + * PD3 - LCD_G7 (alternate 14). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - LCD_B2 (alternate 14). + * PD7 - PIN7 (input pullup). + * PD8 - FMC_D13 (alternate 12). + * PD9 - FMC_D14 (alternate 12). + * PD10 - FMC_D15 (alternate 12). + * PD11 - LCD_TE (input floating). + * PD12 - LCD_RDX (output pushpull maximum). + * PD13 - LCD_WRX (output pushpull maximum). + * PD14 - FMC_D0 (alternate 12). + * PD15 - FMC_D1 (alternate 12). + */ +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_FMC_D2) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D3) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOD_LCD_G7) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOD_LCD_B2) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D13) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D14) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D15) | \ + PIN_MODE_INPUT(GPIOD_LCD_TE) | \ + PIN_MODE_OUTPUT(GPIOD_LCD_RDX) | \ + PIN_MODE_OUTPUT(GPIOD_LCD_WRX) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D0) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D1)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_FMC_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_G7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_B2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D15) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_TE) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_RDX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_WRX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D1)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_FMC_D2) | \ + PIN_OSPEED_100M(GPIOD_FMC_D3) | \ + PIN_OSPEED_2M(GPIOD_PIN2) | \ + PIN_OSPEED_100M(GPIOD_LCD_G7) | \ + PIN_OSPEED_2M(GPIOD_PIN4) | \ + PIN_OSPEED_2M(GPIOD_PIN5) | \ + PIN_OSPEED_100M(GPIOD_LCD_B2) | \ + PIN_OSPEED_2M(GPIOD_PIN7) | \ + PIN_OSPEED_100M(GPIOD_FMC_D13) | \ + PIN_OSPEED_100M(GPIOD_FMC_D14) | \ + PIN_OSPEED_100M(GPIOD_FMC_D15) | \ + PIN_OSPEED_100M(GPIOD_LCD_TE) | \ + PIN_OSPEED_100M(GPIOD_LCD_RDX) | \ + PIN_OSPEED_100M(GPIOD_LCD_WRX) | \ + PIN_OSPEED_100M(GPIOD_FMC_D0) | \ + PIN_OSPEED_100M(GPIOD_FMC_D1)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_FMC_D2) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D3) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_G7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_B2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D13) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D14) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D15) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_TE) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_RDX) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_WRX) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D0) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D1)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_FMC_D2) | \ + PIN_ODR_HIGH(GPIOD_FMC_D3) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_LCD_G7) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_LCD_B2) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_FMC_D13) | \ + PIN_ODR_HIGH(GPIOD_FMC_D14) | \ + PIN_ODR_HIGH(GPIOD_FMC_D15) | \ + PIN_ODR_HIGH(GPIOD_LCD_TE) | \ + PIN_ODR_HIGH(GPIOD_LCD_RDX) | \ + PIN_ODR_HIGH(GPIOD_LCD_WRX) | \ + PIN_ODR_HIGH(GPIOD_FMC_D0) | \ + PIN_ODR_HIGH(GPIOD_FMC_D1)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_FMC_D2, 12) | \ + PIN_AFIO_AF(GPIOD_FMC_D3, 12) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0) | \ + PIN_AFIO_AF(GPIOD_LCD_G7, 14) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0) | \ + PIN_AFIO_AF(GPIOD_LCD_B2, 14) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_FMC_D13, 12) | \ + PIN_AFIO_AF(GPIOD_FMC_D14, 12) | \ + PIN_AFIO_AF(GPIOD_FMC_D15, 12) | \ + PIN_AFIO_AF(GPIOD_LCD_TE, 0) | \ + PIN_AFIO_AF(GPIOD_LCD_RDX, 0) | \ + PIN_AFIO_AF(GPIOD_LCD_WRX, 0) | \ + PIN_AFIO_AF(GPIOD_FMC_D0, 12) | \ + PIN_AFIO_AF(GPIOD_FMC_D1, 12)) + +/* + * GPIOE setup: + * + * PE0 - FMC_NBL0 (alternate 12). + * PE1 - FMC_NBL1 (alternate 12). + * PE2 - PIN2 (input pullup). + * PE3 - PIN3 (input pullup). + * PE4 - PIN4 (input pullup). + * PE5 - PIN5 (input pullup). + * PE6 - PIN6 (input pullup). + * PE7 - FMC_D4 (alternate 12). + * PE8 - FMC_D5 (alternate 12). + * PE9 - FMC_D6 (alternate 12). + * PE10 - FMC_D7 (alternate 12). + * PE11 - FMC_D8 (alternate 12). + * PE12 - FMC_D9 (alternate 12). + * PE13 - FMC_D10 (alternate 12). + * PE14 - FMC_D11 (alternate 12). + * PE15 - FMC_D12 (alternate 12). + */ +#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(GPIOE_FMC_NBL0) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_NBL1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D4) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D5) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D6) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D7) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D8) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D9) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D10) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D11) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D12)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D12)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_FMC_NBL0) | \ + PIN_OSPEED_100M(GPIOE_FMC_NBL1) | \ + PIN_OSPEED_2M(GPIOE_PIN2) | \ + PIN_OSPEED_2M(GPIOE_PIN3) | \ + PIN_OSPEED_2M(GPIOE_PIN4) | \ + PIN_OSPEED_2M(GPIOE_PIN5) | \ + PIN_OSPEED_2M(GPIOE_PIN6) | \ + PIN_OSPEED_100M(GPIOE_FMC_D4) | \ + PIN_OSPEED_100M(GPIOE_FMC_D5) | \ + PIN_OSPEED_100M(GPIOE_FMC_D6) | \ + PIN_OSPEED_100M(GPIOE_FMC_D7) | \ + PIN_OSPEED_100M(GPIOE_FMC_D8) | \ + PIN_OSPEED_100M(GPIOE_FMC_D9) | \ + PIN_OSPEED_100M(GPIOE_FMC_D10) | \ + PIN_OSPEED_100M(GPIOE_FMC_D11) | \ + PIN_OSPEED_100M(GPIOE_FMC_D12)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_FMC_NBL0) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_NBL1) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D4) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D5) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D6) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D7) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D8) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D9) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D10) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D11) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D12)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_FMC_NBL0) | \ + PIN_ODR_HIGH(GPIOE_FMC_NBL1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_FMC_D4) | \ + PIN_ODR_HIGH(GPIOE_FMC_D5) | \ + PIN_ODR_HIGH(GPIOE_FMC_D6) | \ + PIN_ODR_HIGH(GPIOE_FMC_D7) | \ + PIN_ODR_HIGH(GPIOE_FMC_D8) | \ + PIN_ODR_HIGH(GPIOE_FMC_D9) | \ + PIN_ODR_HIGH(GPIOE_FMC_D10) | \ + PIN_ODR_HIGH(GPIOE_FMC_D11) | \ + PIN_ODR_HIGH(GPIOE_FMC_D12)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_FMC_NBL0, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_NBL1, 12) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0) | \ + PIN_AFIO_AF(GPIOE_FMC_D4, 12)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_FMC_D5, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_D6, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_D7, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_D8, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_D9, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_D10, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_D11, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_D12, 12)) + +/* + * GPIOF setup: + * + * PF0 - FMC_A0 (alternate 12). + * PF1 - FMC_A1 (alternate 12). + * PF2 - FMC_A2 (alternate 12). + * PF3 - FMC_A3 (alternate 12). + * PF4 - FMC_A4 (alternate 12). + * PF5 - FMC_A5 (alternate 12). + * PF6 - PIN6 (input pullup). + * PF7 - LCD_DCX (output pushpull maximum). + * PF8 - SPI5_MISO (alternate 5). + * PF9 - SPI5_MOSI (alternate 5). + * PF10 - LCD_DE (output pushpull maximum). + * PF11 - FMC_SDNRAS (alternate 12). + * PF12 - FMC_A6 (alternate 12). + * PF13 - FMC_A7 (alternate 12). + * PF14 - FMC_A8 (alternate 12). + * PF15 - FMC_A9 (alternate 12). + */ +#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_FMC_A0) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A1) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A2) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A3) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A4) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_OUTPUT(GPIOF_LCD_DCX) | \ + PIN_MODE_ALTERNATE(GPIOF_SPI5_MISO) | \ + PIN_MODE_ALTERNATE(GPIOF_SPI5_MOSI) | \ + PIN_MODE_OUTPUT(GPIOF_LCD_DE) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_SDNRAS) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A6) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A7) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A8) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A9)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_FMC_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_LCD_DCX) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SPI5_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SPI5_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOF_LCD_DE) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_SDNRAS) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A9)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_FMC_A0) | \ + PIN_OSPEED_100M(GPIOF_FMC_A1) | \ + PIN_OSPEED_100M(GPIOF_FMC_A2) | \ + PIN_OSPEED_100M(GPIOF_FMC_A3) | \ + PIN_OSPEED_100M(GPIOF_FMC_A4) | \ + PIN_OSPEED_100M(GPIOF_FMC_A5) | \ + PIN_OSPEED_2M(GPIOF_PIN6) | \ + PIN_OSPEED_100M(GPIOF_LCD_DCX) | \ + PIN_OSPEED_100M(GPIOF_SPI5_MISO) | \ + PIN_OSPEED_100M(GPIOF_SPI5_MOSI) | \ + PIN_OSPEED_100M(GPIOF_LCD_DE) | \ + PIN_OSPEED_100M(GPIOF_FMC_SDNRAS) | \ + PIN_OSPEED_100M(GPIOF_FMC_A6) | \ + PIN_OSPEED_100M(GPIOF_FMC_A7) | \ + PIN_OSPEED_100M(GPIOF_FMC_A8) | \ + PIN_OSPEED_100M(GPIOF_FMC_A9)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_FMC_A0) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A1) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A2) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A3) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A4) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOF_LCD_DCX) | \ + PIN_PUPDR_FLOATING(GPIOF_SPI5_MISO) | \ + PIN_PUPDR_FLOATING(GPIOF_SPI5_MOSI) | \ + PIN_PUPDR_FLOATING(GPIOF_LCD_DE) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_SDNRAS) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A6) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A7) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A8) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A9)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_FMC_A0) | \ + PIN_ODR_HIGH(GPIOF_FMC_A1) | \ + PIN_ODR_HIGH(GPIOF_FMC_A2) | \ + PIN_ODR_HIGH(GPIOF_FMC_A3) | \ + PIN_ODR_HIGH(GPIOF_FMC_A4) | \ + PIN_ODR_HIGH(GPIOF_FMC_A5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_LCD_DCX) | \ + PIN_ODR_HIGH(GPIOF_SPI5_MISO) | \ + PIN_ODR_HIGH(GPIOF_SPI5_MOSI) | \ + PIN_ODR_HIGH(GPIOF_LCD_DE) | \ + PIN_ODR_HIGH(GPIOF_FMC_SDNRAS) | \ + PIN_ODR_HIGH(GPIOF_FMC_A6) | \ + PIN_ODR_HIGH(GPIOF_FMC_A7) | \ + PIN_ODR_HIGH(GPIOF_FMC_A8) | \ + PIN_ODR_HIGH(GPIOF_FMC_A9)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_FMC_A0, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A1, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A2, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A3, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A4, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A5, 12) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0) | \ + PIN_AFIO_AF(GPIOF_LCD_DCX, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_SPI5_MISO, 5) | \ + PIN_AFIO_AF(GPIOF_SPI5_MOSI, 5) | \ + PIN_AFIO_AF(GPIOF_LCD_DE, 0) | \ + PIN_AFIO_AF(GPIOF_FMC_SDNRAS, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A6, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A7, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A8, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A9, 12)) + +/* + * GPIOG setup: + * + * PG0 - FMC_A10 (alternate 12). + * PG1 - FMC_A11 (alternate 12). + * PG2 - PIN2 (input pullup). + * PG3 - PIN3 (input pullup). + * PG4 - FMC_BA0 (alternate 12). + * PG5 - FMC_BA1 (alternate 12). + * PG6 - LCD_R7 (alternate 14). + * PG7 - LCD_CLK (alternate 14). + * PG8 - FMC_SDCLK (alternate 12). + * PG9 - PIN9 (input pullup). + * PG10 - LCD_G3 (alternate 14). + * PG11 - LCD_B3 (alternate 14). + * PG12 - LCD_B4 (alternate 14). + * PG13 - LED3_GREEN (output pushpull maximum). + * PG14 - LED4_RED (output pushpull maximum). + * PG15 - FMC_SDNCAS (alternate 12). + */ +#define VAL_GPIOG_MODER (PIN_MODE_ALTERNATE(GPIOG_FMC_A10) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_A11) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_BA0) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_BA1) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_R7) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_CLK) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_SDCLK) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_G3) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_B3) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_B4) | \ + PIN_MODE_OUTPUT(GPIOG_LED3_GREEN) | \ + PIN_MODE_OUTPUT(GPIOG_LED4_RED) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_FMC_A10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_A11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_R7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_G3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_B3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_B4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LED3_GREEN) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LED4_RED) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_FMC_A10) | \ + PIN_OSPEED_100M(GPIOG_FMC_A11) | \ + PIN_OSPEED_2M(GPIOG_PIN2) | \ + PIN_OSPEED_2M(GPIOG_PIN3) | \ + PIN_OSPEED_100M(GPIOG_FMC_BA0) | \ + PIN_OSPEED_100M(GPIOG_FMC_BA1) | \ + PIN_OSPEED_100M(GPIOG_LCD_R7) | \ + PIN_OSPEED_100M(GPIOG_LCD_CLK) | \ + PIN_OSPEED_100M(GPIOG_FMC_SDCLK) | \ + PIN_OSPEED_2M(GPIOG_PIN9) | \ + PIN_OSPEED_100M(GPIOG_LCD_G3) | \ + PIN_OSPEED_100M(GPIOG_LCD_B3) | \ + PIN_OSPEED_100M(GPIOG_LCD_B4) | \ + PIN_OSPEED_100M(GPIOG_LED3_GREEN) | \ + PIN_OSPEED_100M(GPIOG_LED4_RED) | \ + PIN_OSPEED_100M(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_FMC_A10) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_A11) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_BA0) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_BA1) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_R7) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_CLK) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_SDCLK) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_G3) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_B3) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_B4) | \ + PIN_PUPDR_FLOATING(GPIOG_LED3_GREEN) | \ + PIN_PUPDR_FLOATING(GPIOG_LED4_RED) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_FMC_A10) | \ + PIN_ODR_HIGH(GPIOG_FMC_A11) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_FMC_BA0) | \ + PIN_ODR_HIGH(GPIOG_FMC_BA1) | \ + PIN_ODR_HIGH(GPIOG_LCD_R7) | \ + PIN_ODR_HIGH(GPIOG_LCD_CLK) | \ + PIN_ODR_HIGH(GPIOG_FMC_SDCLK) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_LCD_G3) | \ + PIN_ODR_HIGH(GPIOG_LCD_B3) | \ + PIN_ODR_HIGH(GPIOG_LCD_B4) | \ + PIN_ODR_LOW(GPIOG_LED3_GREEN) | \ + PIN_ODR_LOW(GPIOG_LED4_RED) | \ + PIN_ODR_HIGH(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_FMC_A10, 12) | \ + PIN_AFIO_AF(GPIOG_FMC_A11, 12) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0) | \ + PIN_AFIO_AF(GPIOG_FMC_BA0, 12) | \ + PIN_AFIO_AF(GPIOG_FMC_BA1, 12) | \ + PIN_AFIO_AF(GPIOG_LCD_R7, 14) | \ + PIN_AFIO_AF(GPIOG_LCD_CLK, 14)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_FMC_SDCLK, 12) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0) | \ + PIN_AFIO_AF(GPIOG_LCD_G3, 14) | \ + PIN_AFIO_AF(GPIOG_LCD_B3, 14) | \ + PIN_AFIO_AF(GPIOG_LCD_B4, 14) | \ + PIN_AFIO_AF(GPIOG_LED3_GREEN, 0) | \ + PIN_AFIO_AF(GPIOG_LED4_RED, 0) | \ + PIN_AFIO_AF(GPIOG_FMC_SDNCAS, 12)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \ + PIN_OSPEED_100M(GPIOH_OSC_OUT) | \ + PIN_OSPEED_2M(GPIOH_PIN2) | \ + PIN_OSPEED_2M(GPIOH_PIN3) | \ + PIN_OSPEED_2M(GPIOH_PIN4) | \ + PIN_OSPEED_2M(GPIOH_PIN5) | \ + PIN_OSPEED_2M(GPIOH_PIN6) | \ + PIN_OSPEED_2M(GPIOH_PIN7) | \ + PIN_OSPEED_2M(GPIOH_PIN8) | \ + PIN_OSPEED_2M(GPIOH_PIN9) | \ + PIN_OSPEED_2M(GPIOH_PIN10) | \ + PIN_OSPEED_2M(GPIOH_PIN11) | \ + PIN_OSPEED_2M(GPIOH_PIN12) | \ + PIN_OSPEED_2M(GPIOH_PIN13) | \ + PIN_OSPEED_2M(GPIOH_PIN14) | \ + PIN_OSPEED_2M(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_2M(GPIOI_PIN0) | \ + PIN_OSPEED_2M(GPIOI_PIN1) | \ + PIN_OSPEED_2M(GPIOI_PIN2) | \ + PIN_OSPEED_2M(GPIOI_PIN3) | \ + PIN_OSPEED_2M(GPIOI_PIN4) | \ + PIN_OSPEED_2M(GPIOI_PIN5) | \ + PIN_OSPEED_2M(GPIOI_PIN6) | \ + PIN_OSPEED_2M(GPIOI_PIN7) | \ + PIN_OSPEED_2M(GPIOI_PIN8) | \ + PIN_OSPEED_2M(GPIOI_PIN9) | \ + PIN_OSPEED_2M(GPIOI_PIN10) | \ + PIN_OSPEED_2M(GPIOI_PIN11) | \ + PIN_OSPEED_2M(GPIOI_PIN12) | \ + PIN_OSPEED_2M(GPIOI_PIN13) | \ + PIN_OSPEED_2M(GPIOI_PIN14) | \ + PIN_OSPEED_2M(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk new file mode 100644 index 000000000..f927cbb71 --- /dev/null +++ b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32F429I_DISCOVERY/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32F429I_DISCOVERY diff --git a/os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg new file mode 100644 index 000000000..a4ec62ef3 --- /dev/null +++ b/os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg @@ -0,0 +1,1192 @@ + + + + + resources/gencfg/processors/boards/stm32f4xx/templates + .. + + STMicroelectronics STM32F429I-Discovery + ST_STM32F429I_DISCOVERY + + STM32F429_439xx + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/board.h b/os/hal/boards/ST_STM32F4_DISCOVERY/board.h index 85afb6de5..c807c1611 100644 --- a/os/hal/boards/ST_STM32F4_DISCOVERY/board.h +++ b/os/hal/boards/ST_STM32F4_DISCOVERY/board.h @@ -48,9 +48,9 @@ #define STM32_VDD 300 /* - * MCU type as defined in the ST header file stm32f4xx.h. + * MCU type as defined in the ST header. */ -#define STM32F40XX +#define STM32F40_41xxx /* * IO pins assignments. diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg index e30de70e6..fd1a569c5 100644 --- a/os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg +++ b/os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg @@ -10,7 +10,13 @@ STMicroelectronics STM32F4-Discovery ST_STM32F4_DISCOVERY - + STM32F40_41xxx + otg; - halPolledDelay(32); + osalSysPolledDelayX(32); /* Core reset and delay of at least 3 PHY cycles.*/ otgp->GRSTCTL = GRSTCTL_CSRST; while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0) ; - halPolledDelay(12); + osalSysPolledDelayX(12); /* Wait AHB idle condition.*/ while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) diff --git a/os/hal/ports/STM32F0xx/hal_lld.c b/os/hal/ports/STM32F0xx/hal_lld.c index 09ab62923..9b6a85b91 100644 --- a/os/hal/ports/STM32F0xx/hal_lld.c +++ b/os/hal/ports/STM32F0xx/hal_lld.c @@ -61,10 +61,10 @@ static void hal_lld_backup_domain_init(void) { #if STM32_LSE_ENABLED #if defined(STM32_LSE_BYPASS) /* LSE Bypass.*/ - RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; + RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; #else /* No LSE Bypass.*/ - RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON; + RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON; #endif while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) ; /* Waits until LSE is stable. */ diff --git a/os/hal/ports/STM32F30x/hal_lld.c b/os/hal/ports/STM32F30x/hal_lld.c index 4521231d5..46561dc76 100644 --- a/os/hal/ports/STM32F30x/hal_lld.c +++ b/os/hal/ports/STM32F30x/hal_lld.c @@ -61,10 +61,10 @@ static void hal_lld_backup_domain_init(void) { #if STM32_LSE_ENABLED #if defined(STM32_LSE_BYPASS) /* LSE Bypass.*/ - RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; + RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; #else /* No LSE Bypass.*/ - RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON; + RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON; #endif while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) ; /* Waits until LSE is stable. */ diff --git a/os/hal/ports/STM32F37x/hal_lld.c b/os/hal/ports/STM32F37x/hal_lld.c index 6234137b0..a34b11546 100644 --- a/os/hal/ports/STM32F37x/hal_lld.c +++ b/os/hal/ports/STM32F37x/hal_lld.c @@ -61,10 +61,10 @@ static void hal_lld_backup_domain_init(void) { #if STM32_LSE_ENABLED #if defined(STM32_LSE_BYPASS) /* LSE Bypass.*/ - RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; + RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; #else /* No LSE Bypass.*/ - RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON; + RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON; #endif while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) ; /* Waits until LSE is stable. */ diff --git a/os/hal/ports/STM32F4xx/hal_lld.c b/os/hal/ports/STM32F4xx/hal_lld.c index e414043cc..7aeb67297 100644 --- a/os/hal/ports/STM32F4xx/hal_lld.c +++ b/os/hal/ports/STM32F4xx/hal_lld.c @@ -22,8 +22,6 @@ * @{ */ -/* TODO: LSEBYP like in F3.*/ - #include "hal.h" /*===========================================================================*/ @@ -60,7 +58,13 @@ static void hal_lld_backup_domain_init(void) { } #if STM32_LSE_ENABLED +#if defined(STM32_LSE_BYPASS) + /* LSE Bypass.*/ + RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; +#else + /* No LSE Bypass.*/ RCC->BDCR |= RCC_BDCR_LSEON; +#endif while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) ; /* Waits until LSE is stable. */ #endif @@ -142,17 +146,19 @@ void stm32_clock_init(void) { /* PWR initialization.*/ #if defined(STM32F4XX) || defined(__DOXYGEN__) PWR->CR = STM32_VOS; - while ((PWR->CSR & PWR_CSR_VOSRDY) == 0) - ; /* Waits until power regulator is stable. */ #else PWR->CR = 0; #endif - /* Initial clocks setup and wait for HSI stabilization, the MSI clock is - always enabled because it is the fallback clock when PLL the fails.*/ - RCC->CR |= RCC_CR_HSION; - while ((RCC->CR & RCC_CR_HSIRDY) == 0) - ; /* Waits until HSI is stable. */ + /* HSI setup, it enforces the reset situation in order to handle possible + problems with JTAG probes and re-initializations.*/ + RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ + while (!(RCC->CR & RCC_CR_HSIRDY)) + ; /* Wait until HSI is stable. */ + RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ + RCC->CFGR = 0; /* CFGR reset value. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + ; /* Waits until HSI is selected. */ #if STM32_HSE_ENABLED /* HSE activation.*/ @@ -179,21 +185,42 @@ void stm32_clock_init(void) { RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN | STM32_PLLM; RCC->CR |= RCC_CR_PLLON; + + /* Synchronization with voltage regulator stabilization.*/ +#if defined(STM32F4XX) + while ((PWR->CSR & PWR_CSR_VOSRDY) == 0) + ; /* Waits until power regulator is stable. */ + +#if STM32_OVERDRIVE_REQUIRED + /* Overdrive activation performed after activating the PLL in order to save + time as recommended in RM in "Entering Over-drive mode" paragraph.*/ + PWR->CR |= PWR_CR_ODEN; + while (!(PWR->CSR & PWR_CSR_ODRDY)) + ; + PWR->CR |= PWR_CR_ODSWEN; + while (!(PWR->CSR & PWR_CSR_ODSWRDY)) + ; +#endif /* STM32_OVERDRIVE_REQUIRED */ +#endif /* defined(STM32F4XX) */ + + /* Waiting for PLL lock.*/ while (!(RCC->CR & RCC_CR_PLLRDY)) - ; /* Waits until PLL is stable. */ -#endif + ; +#endif /* STM32_OVERDRIVE_REQUIRED */ #if STM32_ACTIVATE_PLLI2S /* PLLI2S activation.*/ RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN; RCC->CR |= RCC_CR_PLLI2SON; + + /* Waiting for PLL lock.*/ while (!(RCC->CR & RCC_CR_PLLI2SRDY)) - ; /* Waits until PLLI2S is stable. */ + ; #endif /* Other clock-related settings (dividers, MCO etc).*/ - RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | - STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; + RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | + STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; /* Flash setup.*/ #if defined(STM32_USE_REVISION_A_FIX) diff --git a/os/hal/ports/STM32F4xx/hal_lld.h b/os/hal/ports/STM32F4xx/hal_lld.h index 98bc2105c..546914742 100644 --- a/os/hal/ports/STM32F4xx/hal_lld.h +++ b/os/hal/ports/STM32F4xx/hal_lld.h @@ -20,14 +20,17 @@ * @pre This module requires the following macros to be defined in the * @p board.h file: * - STM32_LSECLK. + * - STM32_LSE_BYPASS (optionally). * - STM32_HSECLK. * - STM32_HSE_BYPASS (optionally). * - STM32_VDD (as hundredths of Volt). * . * One of the following macros must also be defined: * - STM32F2XX for High-performance STM32 F-2 devices. - * - STM32F40XX for High-performance STM32 F-4 devices. - * - STM32F42XX for High-performance STM32 F-4 devices. + * - STM32F401xx for High-performance STM32 F-4 devices. + * - STM32F40_41xxx for High-performance STM32 F-4 devices. + * - STM32F427_437xx for High-performance STM32 F-4 devices. + * - STM32F429_439xx for High-performance STM32 F-4 devices. * . * * @addtogroup HAL @@ -44,37 +47,77 @@ /*===========================================================================*/ /** - * @name Platform identification + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS TRUE + +/** + * @name Platform identification macros * @{ */ -#if defined(STM32F40XX) || defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32F40x/STM32F41x High Performance" -#elif defined(STM32F42XX) -#define PLATFORM_NAME "STM32F42x/STM32F43x High Performance" -#else /* !defined(STM32F40XX) */ +#if defined(STM32F429_439xx) || defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F429/F439 High Performance with DSP and FPU" +#define STM32F4XX +#elif defined(STM32F427_437xx) || defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F427/F437 High Performance with DSP and FPU" +#define STM32F4XX +#elif defined(STM32F40_41xxx) || defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F407/F417 High Performance with DSP and FPU" +#define STM32F4XX +#elif defined(STM32F401xx) || defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU" +#define STM32F4XX +#elif defined(STM32F2XX) || defined(__DOXYGEN__) #define PLATFORM_NAME "STM32F2xx High Performance" -#endif /* !defined(STM32F40XX) */ +#else +#error "STM32F2xx/F4xx device not specified" +#endif /** @} */ /** * @name Absolute Maximum Ratings * @{ */ -#if defined(STM32F40XX) || defined(__DOXYGEN__) +/** + * @name Absolute Maximum Ratings + * @{ + */ +#if defined(STM32F429_439xx) || defined(STM32F429_439xx) || \ + defined(__DOXYGEN__) +/** + * @brief Absolute maximum system clock. + */ +#define STM32_SYSCLK_MAX 180000000 + /** * @brief Maximum HSE clock frequency. */ #define STM32_HSECLK_MAX 26000000 +/** + * @brief Maximum HSE clock frequency using an external source. + */ +#define STM32_HSECLK_BYP_MAX 50000000 + /** * @brief Minimum HSE clock frequency. */ -#define STM32_HSECLK_MIN 1000000 +#define STM32_HSECLK_MIN 4000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_BYP_MIN 1000000 /** * @brief Maximum LSE clock frequency. */ -#define STM32_LSECLK_MAX 1000000 +#define STM32_LSECLK_MAX 32768 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_BYP_MAX 1000000 /** * @brief Minimum LSE clock frequency. @@ -84,7 +127,7 @@ /** * @brief Maximum PLLs input clock frequency. */ -#define STM32_PLLIN_MAX 2000000 +#define STM32_PLLIN_MAX 2100000 /** * @brief Minimum PLLs input clock frequency. @@ -104,7 +147,7 @@ /** * @brief Maximum PLL output clock frequency. */ -#define STM32_PLLOUT_MAX 168000000 +#define STM32_PLLOUT_MAX 180000000 /** * @brief Minimum PLL output clock frequency. @@ -114,23 +157,67 @@ /** * @brief Maximum APB1 clock frequency. */ -#define STM32_PCLK1_MAX 42000000 +#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX /4) /** * @brief Maximum APB2 clock frequency. */ -#define STM32_PCLK2_MAX 84000000 +#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2) /** * @brief Maximum SPI/I2S clock frequency. */ -#define STM32_SPII2S_MAX 37500000 +#define STM32_SPII2S_MAX 45000000 +#endif /* STM32F40_41xxx */ -#else /* !defined(STM32F40XX) */ +#if defined(STM32F40_41xxx) || defined(__DOXYGEN__) +#define STM32_SYSCLK_MAX 168000000 +#define STM32_HSECLK_MAX 26000000 +#define STM32_HSECLK_BYP_MAX 50000000 +#define STM32_HSECLK_MIN 4000000 +#define STM32_HSECLK_BYP_MIN 1000000 +#define STM32_LSECLK_MAX 32768 +#define STM32_LSECLK_BYP_MAX 1000000 +#define STM32_LSECLK_MIN 32768 +#define STM32_PLLIN_MAX 2100000 +#define STM32_PLLIN_MIN 950000 +#define STM32_PLLVCO_MAX 432000000 +#define STM32_PLLVCO_MIN 192000000 +#define STM32_PLLOUT_MAX 168000000 +#define STM32_PLLOUT_MIN 24000000 +#define STM32_PCLK1_MAX 42000000 +#define STM32_PCLK2_MAX 84000000 +#define STM32_SPII2S_MAX 42000000 +#endif /* STM32F40_41xxx */ + +#if defined(STM32F401xx) || defined(__DOXYGEN__) +#define STM32_SYSCLK_MAX 84000000 +#define STM32_HSECLK_MAX 26000000 +#define STM32_HSECLK_BYP_MAX 50000000 +#define STM32_HSECLK_MIN 4000000 +#define STM32_HSECLK_BYP_MIN 1000000 +#define STM32_LSECLK_MAX 32768 +#define STM32_LSECLK_BYP_MAX 1000000 +#define STM32_LSECLK_MIN 32768 +#define STM32_PLLIN_MAX 2100000 +#define STM32_PLLIN_MIN 950000 +#define STM32_PLLVCO_MAX 432000000 +#define STM32_PLLVCO_MIN 192000000 +#define STM32_PLLOUT_MAX 84000000 +#define STM32_PLLOUT_MIN 24000000 +#define STM32_PCLK1_MAX 42000000 +#define STM32_PCLK2_MAX 84000000 +#define STM32_SPII2S_MAX 42000000 +#endif /* STM32F40_41xxx */ + +#if defined(STM32F2XX) #define STM32_SYSCLK_MAX 120000000 #define STM32_HSECLK_MAX 26000000 +#define STM32_HSECLK_BYP_MAX 26000000 #define STM32_HSECLK_MIN 1000000 -#define STM32_LSECLK_MAX 1000000 +#define STM32_HSECLK_BYP_MIN 1000000 +#define STM32_LSECLK_MAX 32768 +#define STM32_LSECLK_BYP_MAX 1000000 #define STM32_LSECLK_MIN 32768 #define STM32_PLLIN_MAX 2000000 #define STM32_PLLIN_MIN 950000 @@ -140,8 +227,8 @@ #define STM32_PLLOUT_MIN 24000000 #define STM32_PCLK1_MAX 30000000 #define STM32_PCLK2_MAX 60000000 -#define STM32_SPII2S_MAX 37500000 -#endif /* !defined(STM32F40XX) */ +#define STM32_SPII2S_MAX 30000000 +#endif /* defined(STM32F2XX) */ /** @} */ /** @@ -156,11 +243,9 @@ * @name PWR_CR register bits definitions * @{ */ -#if defined(STM32F40XX) || defined(__DOXYGEN__) -#define STM32_VOS_MASK (1 << 14) /**< Core voltage mask. */ -#define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */ -#define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */ -#endif +#define STM32_VOS_SCALE3 (PWR_CR_VOS_0) +#define STM32_VOS_SCALE2 (PWR_CR_VOS_1) +#define STM32_VOS_SCALE1 (PWR_CR_VOS_1 | PWR_CR_VOS_0) #define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ #define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ #define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ @@ -306,6 +391,13 @@ #define STM32_PLS STM32_PLS_LEV0 #endif +/** + * @brief Enables the backup RAM regulator. + */ +#if !defined(STM32_BKPRAM_ENABLE) || defined(__DOXYGEN__) +#define STM32_BKPRAM_ENABLE FALSE +#endif + /** * @brief Enables or disables the HSI clock source. */ @@ -352,17 +444,7 @@ #define STM32_SW STM32_SW_PLL #endif -#if defined(STM32F40XX) || defined(__DOXYGEN__) -/** - * @brief Core voltage selection. - * @note This setting affects all the performance and clock related - * settings, the maximum performance is only obtainable selecting - * the maximum voltage. - */ -#if !defined(STM32_VOS) || defined(__DOXYGEN__) -#define STM32_VOS STM32_VOS_HIGH -#endif - +#if defined(STM32F4XX) || defined(__DOXYGEN__) /** * @brief Clock source for the PLLs. * @note This setting has only effect if the PLL is selected as the @@ -414,7 +496,7 @@ #define STM32_PLLQ_VALUE 7 #endif -#else /* !defined(STM32F40XX) */ +#else /* !defined(STM32F4XX) */ /** * @brief Clock source for the PLLs. * @note This setting has only effect if the PLL is selected as the @@ -465,7 +547,7 @@ #if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) #define STM32_PLLQ_VALUE 5 #endif -#endif /* !defined(STM32F40XX) */ +#endif /* !defined(STM32F4XX) */ /** * @brief AHB prescaler value. @@ -562,14 +644,7 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -/* - * MCU variant check. - */ -#if defined(STM32F42XX) -#error "unsupported STM32F4XX variant" -#endif - -#if defined(STM32F40XX) || defined(__DOXYGEN__) +#if defined(STM32F4XX) || defined(__DOXYGEN__) /* * Configuration-related checks. */ @@ -577,39 +652,31 @@ #error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined" #endif -/** - * @brief Maximum SYSCLK. - * @note It is a function of the core voltage setting. - */ -#if (STM32_VOS == STM32_VOS_HIGH) || defined(__DOXYGEN__) -#define STM32_SYSCLK_MAX 168000000 -#else -#define STM32_SYSCLK_MAX 144000000 -#endif - -#else /* !defined(STM32F40XX) */ +#else /* !defined(STM32F4XX) */ /* * Configuration-related checks. */ #if !defined(STM32F2xx_MCUCONF) #error "Using a wrong mcuconf.h file, STM32F2xx_MCUCONF not defined" #endif -#endif /* !defined(STM32F40XX) */ +#endif /* !defined(STM32F4XX) */ /** * @brief Maximum frequency thresholds and wait states for flash access. * @note The values are valid for 2.7V to 3.6V supply range. */ -#if defined(STM32F40XX) || defined(__DOXYGEN__) +#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ + defined(STM32F40_41xxx) || defined(__DOXYGEN__) #if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__) #define STM32_0WS_THRESHOLD 30000000 #define STM32_1WS_THRESHOLD 60000000 #define STM32_2WS_THRESHOLD 90000000 #define STM32_3WS_THRESHOLD 120000000 #define STM32_4WS_THRESHOLD 150000000 -#define STM32_5WS_THRESHOLD 168000000 +#define STM32_5WS_THRESHOLD 180000000 #define STM32_6WS_THRESHOLD 0 #define STM32_7WS_THRESHOLD 0 +#define STM32_8WS_THRESHOLD 0 #elif (STM32_VDD >= 240) && (STM32_VDD < 270) #define STM32_0WS_THRESHOLD 24000000 #define STM32_1WS_THRESHOLD 48000000 @@ -618,31 +685,79 @@ #define STM32_4WS_THRESHOLD 120000000 #define STM32_5WS_THRESHOLD 144000000 #define STM32_6WS_THRESHOLD 168000000 +#define STM32_7WS_THRESHOLD 180000000 +#define STM32_8WS_THRESHOLD 0 +#elif (STM32_VDD >= 210) && (STM32_VDD < 240) +#define STM32_0WS_THRESHOLD 22000000 +#define STM32_1WS_THRESHOLD 44000000 +#define STM32_2WS_THRESHOLD 66000000 +#define STM32_3WS_THRESHOLD 88000000 +#define STM32_4WS_THRESHOLD 110000000 +#define STM32_5WS_THRESHOLD 132000000 +#define STM32_6WS_THRESHOLD 154000000 +#define STM32_7WS_THRESHOLD 176000000 +#define STM32_8WS_THRESHOLD 180000000 +#elif (STM32_VDD >= 180) && (STM32_VDD < 210) +#define STM32_0WS_THRESHOLD 20000000 +#define STM32_1WS_THRESHOLD 40000000 +#define STM32_2WS_THRESHOLD 60000000 +#define STM32_3WS_THRESHOLD 80000000 +#define STM32_4WS_THRESHOLD 100000000 +#define STM32_5WS_THRESHOLD 120000000 +#define STM32_6WS_THRESHOLD 140000000 +#define STM32_7WS_THRESHOLD 168000000 +#define STM32_8WS_THRESHOLD 0 +#else +#error "invalid VDD voltage specified" +#endif + +#elif defined(STM32F401xx) +#if (STM32_VDD >= 270) && (STM32_VDD <= 360) +#define STM32_0WS_THRESHOLD 30000000 +#define STM32_1WS_THRESHOLD 60000000 +#define STM32_2WS_THRESHOLD 84000000 +#define STM32_3WS_THRESHOLD 0 +#define STM32_4WS_THRESHOLD 0 +#define STM32_5WS_THRESHOLD 0 +#define STM32_6WS_THRESHOLD 0 #define STM32_7WS_THRESHOLD 0 +#define STM32_8WS_THRESHOLD 0 +#elif (STM32_VDD >= 240) && (STM32_VDD < 270) +#define STM32_0WS_THRESHOLD 24000000 +#define STM32_1WS_THRESHOLD 48000000 +#define STM32_2WS_THRESHOLD 72000000 +#define STM32_3WS_THRESHOLD 84000000 +#define STM32_4WS_THRESHOLD 0 +#define STM32_5WS_THRESHOLD 0 +#define STM32_6WS_THRESHOLD 0 +#define STM32_7WS_THRESHOLD 0 +#define STM32_8WS_THRESHOLD 0 #elif (STM32_VDD >= 210) && (STM32_VDD < 240) #define STM32_0WS_THRESHOLD 18000000 #define STM32_1WS_THRESHOLD 36000000 #define STM32_2WS_THRESHOLD 54000000 #define STM32_3WS_THRESHOLD 72000000 -#define STM32_4WS_THRESHOLD 90000000 -#define STM32_5WS_THRESHOLD 108000000 -#define STM32_6WS_THRESHOLD 120000000 -#define STM32_7WS_THRESHOLD 138000000 +#define STM32_4WS_THRESHOLD 840000000 +#define STM32_5WS_THRESHOLD 0 +#define STM32_6WS_THRESHOLD 0 +#define STM32_7WS_THRESHOLD 0 +#define STM32_8WS_THRESHOLD 0 #elif (STM32_VDD >= 180) && (STM32_VDD < 210) #define STM32_0WS_THRESHOLD 16000000 #define STM32_1WS_THRESHOLD 32000000 #define STM32_2WS_THRESHOLD 48000000 #define STM32_3WS_THRESHOLD 64000000 -#define STM32_4WS_THRESHOLD 80000000 -#define STM32_5WS_THRESHOLD 96000000 -#define STM32_6WS_THRESHOLD 112000000 -#define STM32_7WS_THRESHOLD 128000000 +#define STM32_4WS_THRESHOLD 800000000 +#define STM32_5WS_THRESHOLD 840000000 +#define STM32_6WS_THRESHOLD 0 +#define STM32_7WS_THRESHOLD 0 +#define STM32_8WS_THRESHOLD 0 #else #error "invalid VDD voltage specified" #endif -#else /* !defined(STM32F40XX) */ -#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__) +#else /* STM32F2XX */ +#if (STM32_VDD >= 270) && (STM32_VDD <= 360) #define STM32_0WS_THRESHOLD 30000000 #define STM32_1WS_THRESHOLD 60000000 #define STM32_2WS_THRESHOLD 90000000 @@ -681,7 +796,7 @@ #else #error "invalid VDD voltage specified" #endif -#endif /* !defined(STM32F40XX) */ +#endif /* STM32F2XX */ /* * HSI related checks. @@ -916,6 +1031,43 @@ #error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" #endif +/* Calculating VOS settings, it is different for each sub-platform.*/ +#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ + defined(__DOXYGEN__) +#if STM32_SYSCLK <= 120000000 +#define STM32_VOS STM32_VOS_SCALE3 +#define STM32_OVERDRIVE_REQUIRED FALSE +#elif STM32_SYSCLK <= 144000000 +#define STM32_VOS STM32_VOS_SCALE2 +#define STM32_OVERDRIVE_REQUIRED FALSE +#elif STM32_SYSCLK <= 168000000 +#define STM32_VOS STM32_VOS_SCALE1 +#define STM32_OVERDRIVE_REQUIRED FALSE +#else +#define STM32_VOS STM32_VOS_SCALE1 +#define STM32_OVERDRIVE_REQUIRED TRUE +#endif + +#elif defined(STM32F40_41xxx) +#if STM32_SYSCLK <= 144000000 +#define STM32_VOS STM32_VOS_SCALE2 +#else +#define STM32_VOS STM32_VOS_SCALE1 +#endif +#define STM32_OVERDRIVE_REQUIRED FALSE + +#elif defined(STM32F401xx) +#if STM32_SYSCLK <= 60000000 +#define STM32_VOS STM32_VOS_SCALE3 +#else +#define STM32_VOS STM32_VOS_SCALE2 +#endif +#define STM32_OVERDRIVE_REQUIRED FALSE + +#else /* STM32F2XX */ +#define STM32_OVERDRIVE_REQUIRED FALSE +#endif + /** * @brief AHB frequency. */ @@ -1189,8 +1341,10 @@ #define STM32_FLASHBITS 0x00000005 #elif STM32_HCLK <= STM32_6WS_THRESHOLD #define STM32_FLASHBITS 0x00000006 -#else +#elif STM32_HCLK <= STM32_7WS_THRESHOLD #define STM32_FLASHBITS 0x00000007 +#else +#define STM32_FLASHBITS 0x00000008 #endif /* There are differences in vector names in the various sub-families, diff --git a/os/hal/ports/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32F4xx/stm32_registry.h index ba462175c..5edcaad15 100644 --- a/os/hal/ports/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32F4xx/stm32_registry.h @@ -25,10 +25,6 @@ #ifndef _STM32_REGISTRY_H_ #define _STM32_REGISTRY_H_ -#if defined(STM32F40XX) || defined(STM32F427X) -#define STM32F4XX -#endif - /*===========================================================================*/ /* Platform capabilities. */ /*===========================================================================*/