Files for STM32F3xx ADC driver, not complete.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4970 35acf78f-673a-0410-8e92-d51de3d6d3f4master
gdisirio
parent
efa72f03d5
commit
7273d8390d
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@ -77,7 +77,7 @@
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/**
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/**
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* @brief ADC1 driver enable switch.
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* @brief ADC1 driver enable switch.
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* @details If set to @p TRUE the support for ADC1 is included.
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* @details If set to @p TRUE the support for ADC1 is included.
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* @note The default is @p TRUE.
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* @note The default is @p FALSE.
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*/
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*/
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#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
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#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_USE_ADC1 FALSE
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@ -234,6 +234,10 @@
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#define STM32_ADC3_DMA_MSK 0x00000000
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#define STM32_ADC3_DMA_MSK 0x00000000
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#define STM32_ADC3_DMA_CHN 0x00000000
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#define STM32_ADC3_DMA_CHN 0x00000000
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#define STM32_HAS_ADC4 FALSE
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#define STM32_ADC4_DMA_MSK 0x00000000
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#define STM32_ADC4_DMA_CHN 0x00000000
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/* CAN attributes.*/
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_HAS_CAN2 FALSE
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@ -339,6 +339,7 @@
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN1 FALSE
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@ -205,6 +205,7 @@
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 TRUE
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#define STM32_HAS_CAN1 TRUE
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@ -222,6 +222,7 @@
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 TRUE
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#define STM32_HAS_CAN1 TRUE
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@ -0,0 +1,298 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32F3xx/adc_lld.c
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* @brief STM32F3xx ADC subsystem low level driver source.
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*
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* @addtogroup ADC
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief ADC1 driver identifier.*/
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#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
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ADCDriver ADCD1;
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#endif
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Stops an ongoing conversion, if any.
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*
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* @param[in] adc pointer to the ADC registers block
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*/
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static void adc_lld_stop_adc(ADC_TypeDef *adc) {
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if (adc->CR & ADC_CR_ADSTART) {
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adc->CR |= ADC_CR_ADSTP;
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while (adc->CR & ADC_CR_ADSTP)
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;
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}
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}
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/**
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* @brief ADC DMA ISR service routine.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
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/* DMA errors handling.*/
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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/* DMA, this could help only if the DMA tries to access an unmapped
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address space or violates alignment rules.*/
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_adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
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}
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else {
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/* It is possible that the conversion group has already be reset by the
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ADC error handler, in this case this interrupt is spurious.*/
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if (adcp->grpp != NULL) {
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if ((flags & STM32_DMA_ISR_HTIF) != 0) {
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/* Half transfer processing.*/
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_adc_isr_half_code(adcp);
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}
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if ((flags & STM32_DMA_ISR_TCIF) != 0) {
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/* Transfer complete processing.*/
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_adc_isr_full_code(adcp);
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}
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}
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
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/**
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* @brief ADC interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(ADC1_COMP_IRQHandler) {
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uint32_t isr;
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CH_IRQ_PROLOGUE();
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isr = ADC1->ISR;
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ADC1->ISR = isr;
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/* It could be a spurious interrupt caused by overflows after DMA disabling,
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just ignore it in this case.*/
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if (ADCD1.grpp != NULL) {
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/* Note, an overflow may occur after the conversion ended before the driver
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is able to stop the ADC, this is why the DMA channel is checked too.*/
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if ((isr & ADC_ISR_OVR) &&
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(dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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_adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
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}
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if (isr & ADC_ISR_AWD) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(&ADCD1, ADC_ERR_AWD);
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}
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}
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CH_IRQ_EPILOGUE();
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level ADC driver initialization.
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*
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* @notapi
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*/
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void adc_lld_init(void) {
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#if STM32_ADC_USE_ADC1
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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ADCD1.adc = ADC1;
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ADCD1.dmastp = STM32_DMA1_STREAM1;
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ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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#endif
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/* The shared vector is initialized on driver initialization and never
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disabled.*/
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nvicEnableVector(ADC1_COMP_IRQn,
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CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
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/* Calibration procedure.*/
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rccEnableADC1(FALSE);
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chDbgAssert(ADC1->CR == 0, "adc_lld_init(), #1", "invalid register state");
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ADC1->CR |= ADC_CR_ADCAL;
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while (ADC1->CR & ADC_CR_ADCAL)
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;
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rccDisableADC1(FALSE);
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}
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/**
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* @brief Configures and activates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start(ADCDriver *adcp) {
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/* If in stopped state then enables the ADC and DMA clocks.*/
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if (adcp->state == ADC_STOP) {
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#if STM32_ADC_USE_ADC1
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if (&ADCD1 == adcp) {
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bool_t b;
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b = dmaStreamAllocate(adcp->dmastp,
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STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
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(void *)adcp);
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chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
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dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
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rccEnableADC1(FALSE);
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#if STM32_ADCSW == STM32_ADCSW_HSI14
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/* Clock from HSI14, no need for jitter removal.*/
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ADC1->CFGR2 = 0x00001000;
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#else
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#if STM32_ADCPRE == STM32_ADCPRE_DIV2
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ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV2;
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#else
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ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV4;
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#endif
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#endif
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}
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#endif /* STM32_ADC_USE_ADC1 */
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/* ADC initial setup, starting the analog part here in order to reduce
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the latency when starting a conversion.*/
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adcp->adc->CR = ADC_CR_ADEN;
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while (!(adcp->adc->ISR & ADC_ISR_ADRDY))
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;
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}
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}
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/**
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* @brief Deactivates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop(ADCDriver *adcp) {
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/* If in ready state then disables the ADC clock and analog part.*/
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if (adcp->state == ADC_READY) {
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dmaStreamRelease(adcp->dmastp);
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/* Disabling ADC.*/
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if (adcp->adc->CR & ADC_CR_ADEN) {
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adc_lld_stop_adc(adcp->adc);
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adcp->adc->CR |= ADC_CR_ADDIS;
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while (adcp->adc->CR & ADC_CR_ADDIS)
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;
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}
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#if STM32_ADC_USE_ADC1
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if (&ADCD1 == adcp)
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rccDisableADC1(FALSE);
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#endif
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}
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}
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/**
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* @brief Starts an ADC conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start_conversion(ADCDriver *adcp) {
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uint32_t mode;
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const ADCConversionGroup *grpp = adcp->grpp;
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/* DMA setup.*/
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mode = adcp->dmamode;
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if (grpp->circular) {
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mode |= STM32_DMA_CR_CIRC;
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}
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if (adcp->depth > 1) {
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/* If the buffer depth is greater than one then the half transfer interrupt
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interrupt is enabled in order to allows streaming processing.*/
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mode |= STM32_DMA_CR_HTIE;
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}
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dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
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dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
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(uint32_t)adcp->depth);
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dmaStreamSetMode(adcp->dmastp, mode);
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dmaStreamEnable(adcp->dmastp);
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/* ADC setup, if it is defined a callback for the analog watch dog then it
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is enabled.*/
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adcp->adc->ISR = adcp->adc->ISR;
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adcp->adc->IER = ADC_IER_OVRIE | ADC_IER_AWDIE;
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adcp->adc->TR = grpp->tr;
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adcp->adc->SMPR = grpp->smpr;
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adcp->adc->CHSELR = grpp->chselr;
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/* ADC configuration and start.*/
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adcp->adc->CFGR1 = grpp->cfgr1 | ADC_CFGR1_CONT | ADC_CFGR1_DMACFG |
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ADC_CFGR1_DMAEN;
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adcp->adc->CR |= ADC_CR_ADSTART;
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}
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/**
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* @brief Stops an ongoing conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop_conversion(ADCDriver *adcp) {
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dmaStreamDisable(adcp->dmastp);
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adc_lld_stop_adc(adcp->adc);
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}
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#endif /* HAL_USE_ADC */
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/** @} */
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@ -0,0 +1,451 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||||
|
2011,2012 Giovanni Di Sirio.
|
||||||
|
|
||||||
|
This file is part of ChibiOS/RT.
|
||||||
|
|
||||||
|
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
|
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
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||||||
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/**
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* @file STM32F3xx/adc_lld.h
|
||||||
|
* @brief STM32F3xx ADC subsystem low level driver header.
|
||||||
|
*
|
||||||
|
* @addtogroup ADC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _ADC_LLD_H_
|
||||||
|
#define _ADC_LLD_H_
|
||||||
|
|
||||||
|
#if HAL_USE_ADC || defined(__DOXYGEN__)
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver constants. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name Sampling rates
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_SMPR_SMP_1P5 0 /**< @brief 14 cycles conversion time */
|
||||||
|
#define ADC_SMPR_SMP_2P5 1 /**< @brief 15 cycles conversion time. */
|
||||||
|
#define ADC_SMPR_SMP_4P5 2 /**< @brief 17 cycles conversion time. */
|
||||||
|
#define ADC_SMPR_SMP_7P5 3 /**< @brief 20 cycles conversion time. */
|
||||||
|
#define ADC_SMPR_SMP_19P5 4 /**< @brief 32 cycles conversion time. */
|
||||||
|
#define ADC_SMPR_SMP_61P5 5 /**< @brief 74 cycles conversion time. */
|
||||||
|
#define ADC_SMPR_SMP_181P5 6 /**< @brief 194 cycles conversion time. */
|
||||||
|
#define ADC_SMPR_SMP_601P5 7 /**< @brief 614 cycles conversion time. */
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name Resolution
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_CFGR1_RES_12BIT (0 << 3)
|
||||||
|
#define ADC_CFGR1_RES_10BIT (1 << 3)
|
||||||
|
#define ADC_CFGR1_RES_8BIT (2 << 3)
|
||||||
|
#define ADC_CFGR1_RES_6BIT (3 << 3)
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name Threashold register initializer
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_TR(low, high) (((uint32_t)(high) << 16) | (uint32_t)(low))
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver pre-compile time settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name Configuration options
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief ADC1 driver enable switch.
|
||||||
|
* @details If set to @p TRUE the support for ADC1 is included.
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_ADC_USE_ADC1 FALSE
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
* @brief ADC1+ADC2 driver enable switch.
|
||||||
|
* @details If set to @p TRUE the support for ADC1+ADC2 is included.
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_ADC_USE_ADC12) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_ADC_USE_ADC12 FALSE
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
* @brief ADC3 driver enable switch.
|
||||||
|
* @details If set to @p TRUE the support for ADC3 is included.
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_ADC_USE_ADC3 FALSE
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
* @brief ADC3+ADC4 driver enable switch.
|
||||||
|
* @details If set to @p TRUE the support for ADC3+ADC4 is included.
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_ADC_USE_ADC34) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_ADC_USE_ADC34 FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC1/ADC2 DMA priority (0..3|lowest..highest).
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_ADC_ADC12_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_ADC_ADC12_DMA_PRIORITY 2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC3/ADC4 DMA priority (0..3|lowest..highest).
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_ADC_ADC34_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_ADC_ADC34_DMA_PRIORITY 2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC1/ADC2 interrupt priority level setting.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_ADC_ADC12_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_ADC_ADC12_IRQ_PRIORITY 2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC3/ADC4 interrupt priority level setting.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_ADC34_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_ADC_ADC34_IRQ_PRIORITY 2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC1/ADC2 DMA interrupt priority level setting.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_ADC_ADC12_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC3/ADC4 DMA interrupt priority level setting.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_ADC_ADC34_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 2
|
||||||
|
#endif
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Derived constants and error checks. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
|
||||||
|
#error "ADC1 not present in the selected device"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC12 && (!STM32_HAS_ADC1 || !STM32_HAS_ADC2)
|
||||||
|
#error "ADC12 not present in the selected device"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
|
||||||
|
#error "ADC3 not present in the selected device"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC34 && (!STM32_HAS_ADC3 || !STM32_HAS_ADC4)
|
||||||
|
#error "ADC34 not present in the selected device"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !STM32_ADC_USE_ADC1 || !STM32_ADC_USE_ADC12 || \
|
||||||
|
!STM32_ADC_USE_ADC3 || !STM32_ADC_USE_ADC34
|
||||||
|
#error "ADC driver activated but no ADC peripheral assigned"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC1 && \
|
||||||
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
|
||||||
|
#error "Invalid IRQ priority assigned to ADC1"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC1 && \
|
||||||
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_DMA_IRQ_PRIORITY)
|
||||||
|
#error "Invalid IRQ priority assigned to ADC1 DMA"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC1 && \
|
||||||
|
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_PRIORITY)
|
||||||
|
#error "Invalid DMA priority assigned to ADC1"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC12 && \
|
||||||
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
|
||||||
|
#error "Invalid IRQ priority assigned to ADC12"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC12 && \
|
||||||
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_DMA_IRQ_PRIORITY)
|
||||||
|
#error "Invalid IRQ priority assigned to ADC12 DMA"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC12 && \
|
||||||
|
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_PRIORITY)
|
||||||
|
#error "Invalid DMA priority assigned to ADC12"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC3 && \
|
||||||
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)
|
||||||
|
#error "Invalid IRQ priority assigned to ADC3"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC3 && \
|
||||||
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_DMA_IRQ_PRIORITY)
|
||||||
|
#error "Invalid IRQ priority assigned to ADC3 DMA"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC3 && \
|
||||||
|
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC34_DMA_PRIORITY)
|
||||||
|
#error "Invalid DMA priority assigned to ADC3"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC34 && \
|
||||||
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)
|
||||||
|
#error "Invalid IRQ priority assigned to ADC34"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC34 && \
|
||||||
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_DMA_IRQ_PRIORITY)
|
||||||
|
#error "Invalid IRQ priority assigned to ADC34 DMA"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC34 && \
|
||||||
|
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC34_DMA_PRIORITY)
|
||||||
|
#error "Invalid DMA priority assigned to ADC34"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(STM32_DMA_REQUIRED)
|
||||||
|
#define STM32_DMA_REQUIRED
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver data structures and types. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC sample data type.
|
||||||
|
*/
|
||||||
|
typedef uint16_t adcsample_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Channels number in a conversion group.
|
||||||
|
*/
|
||||||
|
typedef uint16_t adc_channels_num_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Possible ADC failure causes.
|
||||||
|
* @note Error codes are architecture dependent and should not relied
|
||||||
|
* upon.
|
||||||
|
*/
|
||||||
|
typedef enum {
|
||||||
|
ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
|
||||||
|
ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
|
||||||
|
ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */
|
||||||
|
} adcerror_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Type of a structure representing an ADC driver.
|
||||||
|
*/
|
||||||
|
typedef struct ADCDriver ADCDriver;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC notification callback type.
|
||||||
|
*
|
||||||
|
* @param[in] adcp pointer to the @p ADCDriver object triggering the
|
||||||
|
* callback
|
||||||
|
* @param[in] buffer pointer to the most recent samples data
|
||||||
|
* @param[in] n number of buffer rows available starting from @p buffer
|
||||||
|
*/
|
||||||
|
typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC error callback type.
|
||||||
|
*
|
||||||
|
* @param[in] adcp pointer to the @p ADCDriver object triggering the
|
||||||
|
* callback
|
||||||
|
* @param[in] err ADC error code
|
||||||
|
*/
|
||||||
|
typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Conversion group configuration structure.
|
||||||
|
* @details This implementation-dependent structure describes a conversion
|
||||||
|
* operation.
|
||||||
|
* @note The use of this configuration structure requires knowledge of
|
||||||
|
* STM32 ADC cell registers interface, please refer to the STM32
|
||||||
|
* reference manual for details.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
/**
|
||||||
|
* @brief Enables the circular buffer mode for the group.
|
||||||
|
*/
|
||||||
|
bool_t circular;
|
||||||
|
/**
|
||||||
|
* @brief Number of the analog channels belonging to the conversion group.
|
||||||
|
*/
|
||||||
|
adc_channels_num_t num_channels;
|
||||||
|
/**
|
||||||
|
* @brief Callback function associated to the group or @p NULL.
|
||||||
|
*/
|
||||||
|
adccallback_t end_cb;
|
||||||
|
/**
|
||||||
|
* @brief Error callback or @p NULL.
|
||||||
|
*/
|
||||||
|
adcerrorcallback_t error_cb;
|
||||||
|
/* End of the mandatory fields.*/
|
||||||
|
/**
|
||||||
|
* @brief ADC CFGR1 register initialization data.
|
||||||
|
*/
|
||||||
|
uint32_t cfgr1;
|
||||||
|
/**
|
||||||
|
* @brief ADC TR register initialization data.
|
||||||
|
*/
|
||||||
|
uint32_t tr;
|
||||||
|
/**
|
||||||
|
* @brief ADC SMPR register initialization data.
|
||||||
|
*/
|
||||||
|
uint32_t smpr;
|
||||||
|
/**
|
||||||
|
* @brief ADC CHSELR register initialization data.
|
||||||
|
* @details The number of bits at logic level one in this register must
|
||||||
|
* be equal to the number in the @p num_channels field.
|
||||||
|
*/
|
||||||
|
uint32_t chselr;
|
||||||
|
} ADCConversionGroup;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Driver configuration structure.
|
||||||
|
* @note It could be empty on some architectures.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t dummy;
|
||||||
|
} ADCConfig;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Structure representing an ADC driver.
|
||||||
|
*/
|
||||||
|
struct ADCDriver {
|
||||||
|
/**
|
||||||
|
* @brief Driver state.
|
||||||
|
*/
|
||||||
|
adcstate_t state;
|
||||||
|
/**
|
||||||
|
* @brief Current configuration data.
|
||||||
|
*/
|
||||||
|
const ADCConfig *config;
|
||||||
|
/**
|
||||||
|
* @brief Current samples buffer pointer or @p NULL.
|
||||||
|
*/
|
||||||
|
adcsample_t *samples;
|
||||||
|
/**
|
||||||
|
* @brief Current samples buffer depth or @p 0.
|
||||||
|
*/
|
||||||
|
size_t depth;
|
||||||
|
/**
|
||||||
|
* @brief Current conversion group pointer or @p NULL.
|
||||||
|
*/
|
||||||
|
const ADCConversionGroup *grpp;
|
||||||
|
#if ADC_USE_WAIT || defined(__DOXYGEN__)
|
||||||
|
/**
|
||||||
|
* @brief Waiting thread.
|
||||||
|
*/
|
||||||
|
Thread *thread;
|
||||||
|
#endif
|
||||||
|
#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
|
||||||
|
#if CH_USE_MUTEXES || defined(__DOXYGEN__)
|
||||||
|
/**
|
||||||
|
* @brief Mutex protecting the peripheral.
|
||||||
|
*/
|
||||||
|
Mutex mutex;
|
||||||
|
#elif CH_USE_SEMAPHORES
|
||||||
|
Semaphore semaphore;
|
||||||
|
#endif
|
||||||
|
#endif /* ADC_USE_MUTUAL_EXCLUSION */
|
||||||
|
#if defined(ADC_DRIVER_EXT_FIELDS)
|
||||||
|
ADC_DRIVER_EXT_FIELDS
|
||||||
|
#endif
|
||||||
|
/* End of the mandatory fields.*/
|
||||||
|
/**
|
||||||
|
* @brief Pointer to the ADCx registers block.
|
||||||
|
*/
|
||||||
|
ADC_TypeDef *adc;
|
||||||
|
/**
|
||||||
|
* @brief Pointer to associated SMA channel.
|
||||||
|
*/
|
||||||
|
const stm32_dma_stream_t *dmastp;
|
||||||
|
/**
|
||||||
|
* @brief DMA mode bit mask.
|
||||||
|
*/
|
||||||
|
uint32_t dmamode;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver macros. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Changes the value of the ADC CCR registers.
|
||||||
|
* @details Use this function in order to enable or disable the internal
|
||||||
|
* analog sources. See the documentation in the STM32F3xx Reference
|
||||||
|
* Manual.
|
||||||
|
*/
|
||||||
|
#define adcSTM32SetCCR(adc, ccr) ((adc)->CCR = (ccr))
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* External declarations. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
|
||||||
|
extern ADCDriver ADCD1;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC12 && !defined(__DOXYGEN__)
|
||||||
|
extern ADCDriver ADCD12;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
|
||||||
|
extern ADCDriver ADCD3;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_ADC_USE_ADC34 && !defined(__DOXYGEN__)
|
||||||
|
extern ADCDriver ADCD34;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
void adc_lld_init(void);
|
||||||
|
void adc_lld_start(ADCDriver *adcp);
|
||||||
|
void adc_lld_stop(ADCDriver *adcp);
|
||||||
|
void adc_lld_start_conversion(ADCDriver *adcp);
|
||||||
|
void adc_lld_stop_conversion(ADCDriver *adcp);
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* HAL_USE_ADC */
|
||||||
|
|
||||||
|
#endif /* _ADC_LLD_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -307,6 +307,10 @@
|
||||||
STM32_DMA_STREAM_ID_MSK(2, 1))
|
STM32_DMA_STREAM_ID_MSK(2, 1))
|
||||||
#define STM32_ADC3_DMA_CHN 0x00000022
|
#define STM32_ADC3_DMA_CHN 0x00000022
|
||||||
|
|
||||||
|
#define STM32_HAS_ADC4 FALSE
|
||||||
|
#define STM32_ADC4_DMA_MSK 0x00000000
|
||||||
|
#define STM32_ADC4_DMA_CHN 0x00000000
|
||||||
|
|
||||||
/* CAN attributes.*/
|
/* CAN attributes.*/
|
||||||
#define STM32_HAS_CAN1 TRUE
|
#define STM32_HAS_CAN1 TRUE
|
||||||
#define STM32_HAS_CAN2 TRUE
|
#define STM32_HAS_CAN2 TRUE
|
||||||
|
|
|
||||||
|
|
@ -182,6 +182,7 @@
|
||||||
#define STM32_HAS_ADC1 TRUE
|
#define STM32_HAS_ADC1 TRUE
|
||||||
#define STM32_HAS_ADC2 FALSE
|
#define STM32_HAS_ADC2 FALSE
|
||||||
#define STM32_HAS_ADC3 FALSE
|
#define STM32_HAS_ADC3 FALSE
|
||||||
|
#define STM32_HAS_ADC4 FALSE
|
||||||
|
|
||||||
/* CAN attributes.*/
|
/* CAN attributes.*/
|
||||||
#define STM32_HAS_CAN1 FALSE
|
#define STM32_HAS_CAN1 FALSE
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue