PAL support for MSP430, various other fixes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1037 35acf78f-673a-0410-8e92-d51de3d6d3f4master
gdisirio
parent
03aef59589
commit
6ab7ea31f1
|
|
@ -18,6 +18,8 @@
|
|||
*/
|
||||
|
||||
#include <ch.h>
|
||||
#include <pal.h>
|
||||
|
||||
#include <signal.h>
|
||||
|
||||
#include "board.h"
|
||||
|
|
@ -45,31 +47,27 @@ void hwinit(void) {
|
|||
BCSCTL2 = VAL_BCSCTL2;
|
||||
|
||||
/*
|
||||
* I/O ports initialization.
|
||||
* I/O ports initialization. PxSEL registers are assumed to be cleared after
|
||||
* the reset.
|
||||
*/
|
||||
P1OUT = VAL_P1OUT;
|
||||
P1DIR = VAL_P1DIR;
|
||||
P1SEL = VAL_P1SEL;
|
||||
palInit();
|
||||
palWritePort(IOPORT_A, VAL_P1OUT);
|
||||
pal_lld_msp430_set_direction(IOPORT_A, VAL_P1DIR);
|
||||
|
||||
P2OUT = VAL_P2OUT;
|
||||
P2DIR = VAL_P2DIR;
|
||||
P2SEL = VAL_P2SEL;
|
||||
palWritePort(IOPORT_B, VAL_P2OUT);
|
||||
pal_lld_msp430_set_direction(IOPORT_B, VAL_P2DIR);
|
||||
|
||||
P3OUT = VAL_P3OUT;
|
||||
P3DIR = VAL_P3DIR;
|
||||
P3SEL = VAL_P3SEL;
|
||||
palWritePort(IOPORT_C, VAL_P3OUT);
|
||||
pal_lld_msp430_set_direction(IOPORT_C, VAL_P3DIR);
|
||||
|
||||
P4OUT = VAL_P4OUT;
|
||||
P4DIR = VAL_P4DIR;
|
||||
P4SEL = VAL_P4SEL;
|
||||
palWritePort(IOPORT_D, VAL_P4OUT);
|
||||
pal_lld_msp430_set_direction(IOPORT_D, VAL_P4DIR);
|
||||
|
||||
P5OUT = VAL_P5OUT;
|
||||
P5DIR = VAL_P5DIR;
|
||||
P5SEL = VAL_P5SEL;
|
||||
palWritePort(IOPORT_E, VAL_P5OUT);
|
||||
pal_lld_msp430_set_direction(IOPORT_E, VAL_P5DIR);
|
||||
|
||||
P6OUT = VAL_P6OUT;
|
||||
P6DIR = VAL_P6DIR;
|
||||
P6SEL = VAL_P6SEL;
|
||||
palWritePort(IOPORT_F, VAL_P6OUT);
|
||||
pal_lld_msp430_set_direction(IOPORT_F, VAL_P6DIR);
|
||||
|
||||
/*
|
||||
* Timer 0 setup, uses SMCLK as source.
|
||||
|
|
|
|||
|
|
@ -58,40 +58,44 @@
|
|||
#endif
|
||||
|
||||
/*
|
||||
* Pin definitionsfor the Olimex MSP430-P1611 board.
|
||||
* Pin definitions for the Olimex MSP430-P1611 board.
|
||||
*/
|
||||
#define P3_O_TXD0 (1 << 4)
|
||||
#define P3_I_RXD0 (1 << 5)
|
||||
#define P6_O_LED (1 << 0)
|
||||
#define P6_I_BUTTON (1 << 1)
|
||||
#define P3_O_TXD0 4
|
||||
#define P3_O_TXD0_MASK (1 << P3_O_TXD0)
|
||||
#define P3_I_RXD0 5
|
||||
#define P3_I_RXD0_MASK (1 << P3_I_RXD0)
|
||||
#define P6_O_LED 0
|
||||
#define P6_O_LED_MASK (1 << P6_O_LED)
|
||||
#define P6_I_BUTTON 1
|
||||
#define P6_I_BUTTON_MASK (1 << P6_I_BUTTON)
|
||||
|
||||
/*
|
||||
* Initial I/O ports settings.
|
||||
*/
|
||||
#define VAL_P1OUT 0x00
|
||||
#define VAL_P1DIR 0xFF
|
||||
#define VAL_P1SEL 0x00
|
||||
|
||||
#define VAL_P2OUT 0x00
|
||||
#define VAL_P2DIR 0xFF
|
||||
#define VAL_P2SEL 0x00
|
||||
|
||||
#define VAL_P3OUT P3_O_TXD0
|
||||
#define VAL_P3DIR ~P3_I_RXD0
|
||||
#define VAL_P3SEL 0x00
|
||||
#define VAL_P3OUT P3_O_TXD0_MASK
|
||||
#define VAL_P3DIR ~P3_I_RXD0_MASK
|
||||
|
||||
#define VAL_P4OUT 0x00
|
||||
#define VAL_P4DIR 0xFF
|
||||
#define VAL_P4SEL 0x00
|
||||
|
||||
#define VAL_P5OUT 0x00
|
||||
#define VAL_P5DIR 0xFF
|
||||
#define VAL_P5SEL 0x00
|
||||
|
||||
#define VAL_P6OUT P6_O_LED
|
||||
#define VAL_P6DIR ~P6_I_BUTTON
|
||||
#define VAL_P6SEL 0x00
|
||||
#define VAL_P6OUT P6_O_LED_MASK
|
||||
#define VAL_P6DIR ~P6_I_BUTTON_MASK
|
||||
|
||||
void hwinit(void);
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void hwinit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _BOARD_H_ */
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
*/
|
||||
|
||||
#include <ch.h>
|
||||
#include <pal.h>
|
||||
#include <test.h>
|
||||
|
||||
#include "board.h"
|
||||
|
|
@ -30,9 +31,9 @@ static WORKING_AREA(waThread1, 64);
|
|||
static msg_t Thread1(void *arg) {
|
||||
|
||||
while (TRUE) {
|
||||
P6OUT |= P6_O_LED;
|
||||
palSetPad(IOPORT_F, P6_O_LED);
|
||||
chThdSleepMilliseconds(500);
|
||||
P6OUT &= ~P6_O_LED;
|
||||
palClearPad(IOPORT_F, P6_O_LED);
|
||||
chThdSleepMilliseconds(500);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -64,7 +65,7 @@ int main(int argc, char **argv) {
|
|||
* sleeping in a loop.
|
||||
*/
|
||||
while (TRUE) {
|
||||
if (!(P6IN & P6_I_BUTTON))
|
||||
if (!palReadPad(IOPORT_F, P6_I_BUTTON))
|
||||
TestThread(&COM1);
|
||||
chThdSleepMilliseconds(500);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@
|
|||
|
||||
/**
|
||||
* @defgroup AT91SAM7X AT91SAM7X Support
|
||||
* @{
|
||||
* @brief AT91SAM7X specific support.
|
||||
* @details The AT91SAM7X support includes:
|
||||
* - Buffered, interrupt driven, serial driver.
|
||||
|
|
@ -29,23 +28,33 @@
|
|||
*
|
||||
* @ingroup ARM7
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup AT91SAM7X_PAL I/O Ports Support
|
||||
* @brief I/O Ports peripherals support.
|
||||
* @details This module supports the AT91SAM7X PIO controller. The controller
|
||||
* supports the following features (see @ref PAL):
|
||||
* - 32 bits wide ports.
|
||||
* - Atomic set/reset functions.
|
||||
* - Output latched regardless of the pad setting.
|
||||
* - Direct read of input pads regardless of the pad setting.
|
||||
* .
|
||||
* The only non atomic operations are bit toggling and bus/group writing.
|
||||
*
|
||||
* @ingroup AT91SAM7X
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup AT91SAM7X_SERIAL USART Support
|
||||
* @{
|
||||
* @brief USART peripherals support.
|
||||
* @details The serial driver supports the AT91SAM7X USART peripherals.
|
||||
*
|
||||
* @ingroup AT91SAM7X
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup AT91SAM7X_EMAC EMAC Support
|
||||
* @{
|
||||
* @brief EMAC peripheral support.
|
||||
*
|
||||
* @ingroup AT91SAM7X
|
||||
*/
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -177,8 +177,7 @@ typedef FIO * ioportid_t;
|
|||
|
||||
/**
|
||||
* @brief FIO port setup.
|
||||
* @details This function initializes a FIO port, note that this functionality
|
||||
* is LPC214x specific and non portable.
|
||||
* @details This function programs the pins direction within a port.
|
||||
*/
|
||||
#define pal_lld_lpc214x_set_direction(port, dir) { \
|
||||
(port)->FIO_DIR = (dir); \
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@
|
|||
|
||||
/**
|
||||
* @defgroup LPC214x LPC214x Support
|
||||
* @{
|
||||
* @brief LPC214x specific support.
|
||||
* @details The LPC214x support includes:
|
||||
* - VIC support code.
|
||||
|
|
@ -34,16 +33,13 @@
|
|||
*
|
||||
* @ingroup ARM7
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup LPC214x_VIC VIC Support
|
||||
* @{
|
||||
* @brief VIC peripheral support.
|
||||
*
|
||||
* @ingroup LPC214x
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup LPC214x_PAL I/O Ports Support
|
||||
|
|
@ -52,7 +48,6 @@
|
|||
* supports the following features (see @ref PAL):
|
||||
* - 32 bits wide ports.
|
||||
* - Atomic set/reset functions.
|
||||
* - Atomic set+reset function (atomic bus operations).
|
||||
* - Output latched regardless of the pad setting.
|
||||
* - Direct read of input pads regardless of the pad setting.
|
||||
* .
|
||||
|
|
@ -63,20 +58,16 @@
|
|||
|
||||
/**
|
||||
* @defgroup LPC214x_SERIAL UART Support
|
||||
* @{
|
||||
* @brief UART peripherals support.
|
||||
* @details The serial driver supports the LPC214x UART peripherals.
|
||||
*
|
||||
* @ingroup LPC214x
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup LPC214x_SSP SSP Support
|
||||
* @{
|
||||
* @brief SSP peripheral support.
|
||||
* @details This SPI driver supports the LPC214x SSP peripheral.
|
||||
*
|
||||
* @ingroup LPC214x
|
||||
*/
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@
|
|||
|
||||
/**
|
||||
* @defgroup ARM7 ARM7TDMI
|
||||
* @{
|
||||
* @details The ARM7 architecture is quite complex for a microcontroller and
|
||||
* some explanations are required about the port choices.
|
||||
*
|
||||
|
|
@ -121,11 +120,9 @@
|
|||
*
|
||||
* @ingroup Ports
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup ARM7_CONF Configuration Options
|
||||
* @{
|
||||
* @brief ARM7 specific configuration options.
|
||||
* @details The ARM7 port allows some architecture-specific configurations
|
||||
* settings that can be specified externally, as example on the compiler
|
||||
|
|
@ -144,11 +141,9 @@
|
|||
*
|
||||
* @ingroup ARM7
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup ARM7_CORE Core Port Implementation
|
||||
* @{
|
||||
* @brief ARM7 specific port code, structures and macros.
|
||||
*
|
||||
* @ingroup ARM7
|
||||
|
|
@ -156,11 +151,9 @@
|
|||
* @file ports/ARM7/chcore.h Port related structures and macros.
|
||||
* @file ports/ARM7/chcore.c Port related code.
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup ARM7_STARTUP Startup Support
|
||||
* @{
|
||||
* @brief ARM7 startup code support.
|
||||
* @details ChibiOS/RT provides its own generic startup file for the ARM7 port.
|
||||
* Of course it is not mandatory to use it but care should be taken about the
|
||||
|
|
@ -205,4 +198,3 @@
|
|||
* @ingroup ARM7
|
||||
* @file ports/ARM7/crt0.s Startup code.
|
||||
*/
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@
|
|||
|
||||
/**
|
||||
* @defgroup ARMCM3 ARM Cortex-M3
|
||||
* @{
|
||||
* @details The ARM Cortex-M3 architecture is quite complex for a
|
||||
* microcontroller and some explanations are required about the port choices.
|
||||
*
|
||||
|
|
@ -82,11 +81,9 @@
|
|||
*
|
||||
* @ingroup Ports
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup ARMCM3_CONF Configuration Options
|
||||
* @{
|
||||
* @brief ARM Cortex-M3 Configuration Options.
|
||||
* @details The ARMCM3 port allows some architecture-specific configurations
|
||||
* settings that can be specified externally, as example on the compiler
|
||||
|
|
@ -113,20 +110,16 @@
|
|||
*
|
||||
* @ingroup ARMCM3
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup ARMCM3_CORE Core Port Implementation
|
||||
* @{
|
||||
* @brief ARM Cortex-M3 specific port code, structures and macros.
|
||||
*
|
||||
* @ingroup ARMCM3
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup ARMCM3_STARTUP Startup Support
|
||||
* @{
|
||||
* @brief ARM Cortex-M3 startup code support.
|
||||
* @details ChibiOS/RT provides its own generic startup file for the ARM
|
||||
* Cortex-M3 port.
|
||||
|
|
@ -168,13 +161,10 @@
|
|||
* @ingroup ARMCM3
|
||||
* @file ports/ARMCM3/crt0.s Startup code.
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup ARMCM3_NVIC NVIC Support
|
||||
* @{
|
||||
* @brief ARM Cortex-M3 NVIC support.
|
||||
*
|
||||
* @ingroup ARMCM3
|
||||
*/
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,192 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file ports/MSP430/pal_lld.h
|
||||
* @brief MSP430 Digital I/O low level driver
|
||||
* @addtogroup MSP430_PAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _PAL_LLD_H_
|
||||
#define _PAL_LLD_H_
|
||||
|
||||
#include <msp430x16x.h>
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I/O Ports Types and constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Generic MSP430 I/O port.
|
||||
*/
|
||||
union __ioport {
|
||||
struct {
|
||||
ioregister_t in;
|
||||
ioregister_t out;
|
||||
ioregister_t dir;
|
||||
} iop_common;
|
||||
struct port_simple_t iop_simple;
|
||||
struct port_full_t iop_full;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Width, in bits, of an I/O port.
|
||||
*/
|
||||
#define PAL_IOPORTS_WIDTH 8
|
||||
|
||||
/**
|
||||
* @brief Digital I/O port sized unsigned type.
|
||||
*/
|
||||
typedef uint8_t ioportmask_t;
|
||||
|
||||
/**
|
||||
* @brief Port Identifier.
|
||||
* @details This type can be a scalar or some kind of pointer, do not make
|
||||
* any assumption about it, use the provided macros when populating
|
||||
* variables of this type.
|
||||
*/
|
||||
typedef union __ioport * ioportid_t;
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I/O Ports Identifiers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief I/O port A identifier.
|
||||
* @details This port identifier is mapped on the MSP430 port 1 (P1).
|
||||
*/
|
||||
#if defined(__MSP430_HAS_PORT1__) || \
|
||||
defined(__MSP430_HAS_PORT1_R__) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define IOPORT_A ((ioportid_t)0x0020)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief I/O port B identifier.
|
||||
* @details This port identifier is mapped on the MSP430 port 2 (P2).
|
||||
*/
|
||||
#if defined(__MSP430_HAS_PORT2__) || \
|
||||
defined(__MSP430_HAS_PORT2_R__) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define IOPORT_B ((ioportid_t)0x0028)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief I/O port C identifier.
|
||||
* @details This port identifier is mapped on the MSP430 port 3 (P3).
|
||||
*/
|
||||
#if defined(__MSP430_HAS_PORT3__) || \
|
||||
defined(__MSP430_HAS_PORT3_R__) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define IOPORT_C ((ioportid_t)0x0018)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief I/O port D identifier.
|
||||
* @details This port identifier is mapped on the MSP430 port 4 (P4).
|
||||
*/
|
||||
#if defined(__MSP430_HAS_PORT4__) || \
|
||||
defined(__MSP430_HAS_PORT4_R__) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define IOPORT_D ((ioportid_t)0x001c)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief I/O port E identifier.
|
||||
* @details This port identifier is mapped on the MSP430 port 5 (P5).
|
||||
*/
|
||||
#if defined(__MSP430_HAS_PORT5__) || \
|
||||
defined(__MSP430_HAS_PORT5_R__) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define IOPORT_E ((ioportid_t)0x0030)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief I/O port F identifier.
|
||||
* @details This port identifier is mapped on the MSP430 port 6 (P6).
|
||||
*/
|
||||
#if defined(__MSP430_HAS_PORT6__) || \
|
||||
defined(__MSP430_HAS_PORT6_R__) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define IOPORT_F ((ioportid_t)0x0034)
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Implementation, some of the following macros could be implemented as */
|
||||
/* functions, if so please put them in a file named pal_lld.c. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Low level PAL subsystem initialization.
|
||||
*/
|
||||
#define pal_lld_init()
|
||||
|
||||
/**
|
||||
* @brief Reads the physical I/O port states.
|
||||
* @details This function is implemented by reading the PxIN register, the
|
||||
* implementation has no side effects.
|
||||
*
|
||||
* @param[in] port the port identifier
|
||||
* @return The port bits.
|
||||
*
|
||||
* @note This function is not meant to be invoked directly by the application
|
||||
* code.
|
||||
*/
|
||||
#define pal_lld_readport(port) ((port)->iop_common.in.reg_p)
|
||||
|
||||
/**
|
||||
* @brief Reads the output latch.
|
||||
* @details This function is implemented by reading the PxOUT register, the
|
||||
* implementation has no side effects.
|
||||
*
|
||||
* @param[in] port the port identifier
|
||||
* @return The latched logical states.
|
||||
*
|
||||
* @note This function is not meant to be invoked directly by the application
|
||||
* code.
|
||||
*/
|
||||
#define pal_lld_readlatch(port) ((port)->iop_common.out.reg_p)
|
||||
|
||||
/**
|
||||
* @brief Writes a bits mask on a I/O port.
|
||||
* @details This function is implemented by writing the PxOUT register, the
|
||||
* implementation has no side effects.
|
||||
*
|
||||
* @param[in] port the port identifier
|
||||
* @param[in] bits the bits to be written on the specified port
|
||||
*
|
||||
* @note This function is not meant to be invoked directly by the application
|
||||
* code.
|
||||
*/
|
||||
#define pal_lld_writeport(port, bits) { \
|
||||
(port)->iop_common.out.reg_p = (bits); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set pins direction.
|
||||
* @details This function programs the pins direction within a port.
|
||||
*/
|
||||
#define pal_lld_msp430_set_direction(port, dirmask) { \
|
||||
(port)->iop_common.dir.reg_p = (dirmask); \
|
||||
}
|
||||
|
||||
#endif /* _PAL_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -19,7 +19,6 @@
|
|||
|
||||
/**
|
||||
* @defgroup MSP430 MSP430
|
||||
* @{
|
||||
* @details MSP430 port details. This section how the ChibiOS/RT features are
|
||||
* implemented on this architecture.
|
||||
*
|
||||
|
|
@ -59,11 +58,9 @@
|
|||
*
|
||||
* @ingroup Ports
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup MSP430_CONF Configuration Options
|
||||
* @{
|
||||
* @brief MSP430 Configuration Options.
|
||||
* @details The MSP430 port allows some architecture-specific configurations
|
||||
* settings that can be specified externally, as example on the compiler
|
||||
|
|
@ -76,33 +73,41 @@
|
|||
*
|
||||
* @ingroup MSP430
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup MSP430_CORE Core Port Implementation
|
||||
* @{
|
||||
* @brief MSP430 specific port code, structures and macros.
|
||||
*
|
||||
* @ingroup MSP430
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup MSP430_DRIVERS MSP430 Drivers
|
||||
* @{
|
||||
* @brief Device drivers included in the MSP430 support.
|
||||
*
|
||||
* @ingroup MSP430
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup MSP430_PAL I/O Ports Support
|
||||
* @brief I/O Ports peripherals support.
|
||||
* @details This module supports the MSP430 Digital I/O controller. The
|
||||
* controller supports the following features (see @ref PAL):
|
||||
* - 8 bits wide ports.
|
||||
* - Atomic set/reset/toggle functions because special MSP430 instruction set.
|
||||
* - Output latched regardless of the pad setting.
|
||||
* - Direct read of input pads regardless of the pad setting.
|
||||
* .
|
||||
* The only non atomic operations are bus/group writing.
|
||||
*
|
||||
* @ingroup MSP430_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MSP430_SERIAL USART Support
|
||||
* @{
|
||||
* @brief USART support.
|
||||
* @details The serial driver supports both the MSP430 USARTs in asynchronous
|
||||
* mode.
|
||||
*
|
||||
* @ingroup MSP430_DRIVERS
|
||||
*/
|
||||
/** @} */
|
||||
|
|
|
|||
Loading…
Reference in New Issue