git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6098 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-08-07 13:37:27 +00:00
parent 636f02da90
commit 68ea680d84
4 changed files with 110 additions and 7 deletions

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@ -1,5 +1,6 @@
# List of all the STM32F30x platform files.
PLATFORMSRC = ${CHIBIOS}/os/halnew/platforms/STM32F30x/stm32_dma.c \
PLATFORMSRC = ${CHIBIOS}/os/halnew/platforms/common/ARMCMx/nvic.c \
${CHIBIOS}/os/halnew/platforms/STM32F30x/stm32_dma.c \
${CHIBIOS}/os/halnew/platforms/STM32F30x/hal_lld.c \
${CHIBIOS}/os/halnew/platforms/STM32F30x/adc_lld.c \
${CHIBIOS}/os/halnew/platforms/STM32F30x/ext_lld_isr.c \
@ -18,7 +19,8 @@ PLATFORMSRC = ${CHIBIOS}/os/halnew/platforms/STM32F30x/stm32_dma.c \
${CHIBIOS}/os/halnew/platforms/STM32/USBv1/usb_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/halnew/platforms/STM32F30x \
PLATFORMINC = ${CHIBIOS}/os/halnew/platforms/common/ARMCMx \
${CHIBIOS}/os/halnew/platforms/STM32F30x \
${CHIBIOS}/os/halnew/platforms/STM32 \
${CHIBIOS}/os/halnew/platforms/STM32/GPIOv2 \
${CHIBIOS}/os/halnew/platforms/STM32/I2Cv2 \

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@ -0,0 +1,57 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file common/ARMCMx/nvic.c
* @brief Cortex-Mx NVIC support code.
*
* @addtogroup COMMON_ARMCMx_NVIC
* @{
*/
#include "hal.h"
/**
* @brief Sets the priority of an interrupt handler and enables it.
* @note The parameters are not tested for correctness.
*
* @param[in] n the interrupt number
* @param[in] prio the interrupt priority mask
*/
void nvicEnableVector(uint32_t n, uint32_t prio) {
NVIC->IP[n] = prio << (8 - __NVIC_PRIO_BITS);
NVIC->ICPR[n >> 5] = 1 << (n & 0x1F);
NVIC->ISER[n >> 5] = 1 << (n & 0x1F);
}
/**
* @brief Disables an interrupt handler.
* @note The parameters are not tested for correctness.
*
* @param[in] n the interrupt number
*/
void nvicDisableVector(uint32_t n) {
NVIC->ICER[n >> 5] = 1 << (n & 0x1F);
NVIC->IP[n] = 0;
}
/** @} */

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@ -0,0 +1,43 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file common/ARMCMx/nvic.h
* @brief Cortex-Mx NVIC support macros and structures.
*
* @addtogroup COMMON_ARMCMx_NVIC
* @{
*/
#ifndef _NVIC_H_
#define _NVIC_H_
#ifdef __cplusplus
extern "C" {
#endif
void nvicEnableVector(uint32_t n, uint32_t prio);
void nvicDisableVector(uint32_t n);
#ifdef __cplusplus
}
#endif
#endif /* _NVIC_H_ */
/** @} */

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@ -31,11 +31,11 @@
#include "chcore.h"
#if !defined(FALSE) || defined(__DOXYGEN__)
#define FALSE 0
#define FALSE 0
#endif
#if !defined(TRUE) || defined(__DOXYGEN__)
#define TRUE 1
#define TRUE 1
#endif
#if !defined(__DOXYGEN__)
@ -56,7 +56,7 @@
* Performs a context switch between two threads.
*--------------------------------------------------------------------------*/
.thumb_func
.globl _port_switch
.globl _port_switch
_port_switch:
push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
#if CORTEX_USE_FPU
@ -78,7 +78,7 @@ _port_switch:
* called on thread function return.
*--------------------------------------------------------------------------*/
.thumb_func
.globl _port_thread_start
.globl _port_thread_start
_port_thread_start:
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
@ -98,7 +98,7 @@ _port_thread_start:
* Exception handlers return here for context switching.
*--------------------------------------------------------------------------*/
.thumb_func
.globl _port_switch_from_isr
.globl _port_switch_from_isr
_port_switch_from_isr:
#if CH_DBG_STATISTICS
bl _stats_start_measure_crit_thd
@ -113,6 +113,7 @@ _port_switch_from_isr:
#if CH_DBG_STATISTICS
bl _stats_stop_measure_crit_thd
#endif
.globl _port_exit_from_isr
_port_exit_from_isr:
#if CORTEX_SIMPLIFIED_PRIORITY
mov r3, #SCB_ICSR :AND: 0xFFFF