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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5422 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-03-13 12:55:10 +00:00
parent 1a9fd1ee48
commit 68c2e740e8
10 changed files with 6875 additions and 3 deletions
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9
os/hal/platforms/SPC563Mxx/hal_lld.h
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@ -27,7 +27,7 @@
#ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
#include "mpc563m.h"
#include "xpc563m.h"
#include "spc563m_registry.h"
/*===========================================================================*/
@ -42,12 +42,17 @@
/**
* @brief Platform name.
*/
#define PLATFORM_NAME "SPC563M64"
#define PLATFORM_NAME "SPC563Mxx Powertrain"
/**
* @name ESYNCR2 register definitions
* @{
*/
#define SPC5_RFD_DIV2 0 /**< Divide VCO frequency by 2. */
#define SPC5_RFD_DIV4 1 /**< Divide VCO frequency by 4. */
#define SPC5_RFD_DIV8 2 /**< Divide VCO frequency by 8. */
#define SPC5_RFD_DIV16 3 /**< Divide VCO frequency by 16.*/
/** @} */
/**
* @name BIUCR register definitions

2
os/hal/platforms/SPC563Mxx/platform.mk
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@ -1,4 +1,4 @@
# List of all the SPC56x platform files.
# List of all the SPC563Mxx platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC563Mxx/hal_lld.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c \

2
os/hal/platforms/SPC563Mxx/spc563m_registry.h
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@ -48,6 +48,8 @@
#define SPC5_ESCIB_HANDLER vector149
#define SPC5_ESCIB_NUMBER 149
#define SPC5_HAS_ESCIC FALSE
/* SIU attributes.*/
#define SPC5_HAS_SIU TRUE
#define SPC5_SIU_SUPPORTS_PORTS FALSE

0
os/hal/platforms/SPC563Mxx/mpc563m.h → os/hal/platforms/SPC563Mxx/xpc563m.h
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124
os/hal/platforms/SPC564Axx/hal_lld.c Normal file
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@ -0,0 +1,124 @@
/*
* Licensed under ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file SPC564Axx/hal_lld.c
* @brief SPC564Axx HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
*/
#include "ch.h"
#include "hal.h"
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
extern void _vectors(void);
uint32_t n;
/* FLASH wait states and prefetching setup.*/
CFLASH0.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
CFLASH0.BIUCR2.R = 0;
CFLASH0.PFCR3.R = 0;
/* Optimal crossbar settings. The DMA priority is placed above the CPU
priority in order to not starve I/O activities while the CPU is
executing tight loops (FLASH and SRAM slave ports only).
The SRAM is parked on the load/store port, for some unknown reason it
is defaulted on the instructions port and this kills performance.*/
XBAR.SGPCR3.B.PARK = 4; /* RAM slave on load/store port.*/
XBAR.MPR0.R = 0x00030201; /* Flash slave port priorities:
eDMA (1): 0 (highest)
Core Instructions (0): 1
Undocumented (2): 2
Core Data (4): 3 */
XBAR.MPR3.R = 0x00030201; /* SRAM slave port priorities:
eDMA (1): 0 (highest)
Core Instructions (0): 1
Undocumented (2): 2
Core Data (4): 3 */
/* Downcounter timer initialized for system tick use, TB enabled for debug
and measurements.*/
n = SPC5_SYSCLK / CH_FREQUENCY;
asm volatile ("li %%r3, 0 \t\n"
"mtspr 284, %%r3 \t\n" /* Clear TBL register. */
"mtspr 285, %%r3 \t\n" /* Clear TBU register. */
"mtspr 22, %[n] \t\n" /* Init. DEC register. */
"mtspr 54, %[n] \t\n" /* Init. DECAR register.*/
"li %%r3, 0x4000 \t\n" /* TBEN bit. */
"mtspr 1008, %%r3 \t\n" /* HID0 register. */
"lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */
"mtspr 340, %%r3" /* TCR register. */
: : [n] "r" (n) : "r3");
/* INTC initialization, software vector mode, 4 bytes vectors, starting
at priority 0.*/
INTC.MCR.R = 0;
INTC.CPR.R = 0;
INTC.IACKR.R = (uint32_t)_vectors;
}
/**
* @brief SPC563 clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h and
* @p hal_lld.h
* @note This function must be invoked only after the system reset.
*
* @special
*/
void spc_clock_init(void) {
#if !SPC5_NO_INIT
/* PLL activation.*/
FMPLL.ESYNCR1.B.EMODE = 1; /* Enhanced mode on. */
FMPLL.ESYNCR1.B.CLKCFG &= 1; /* Bypass mode, PLL off.*/
#if !SPC5_CLK_BYPASS
FMPLL.ESYNCR1.B.CLKCFG |= 2; /* PLL on. */
FMPLL.ESYNCR1.B.EPREDIV = SPC5_CLK_PREDIV;
FMPLL.ESYNCR1.B.EMFD = SPC5_CLK_MFD;
FMPLL.ESYNCR2.B.ERFD = SPC5_CLK_RFD;
while (!FMPLL.SYNSR.B.LOCK)
;
FMPLL.ESYNCR1.B.CLKCFG |= 4; /* Clock from the PLL. */
#endif /* !SPC5_CLK_BYPASS */
#endif /* !SPC5_NO_INIT */
}
/** @} */

264
os/hal/platforms/SPC564Axx/hal_lld.h Normal file
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@ -0,0 +1,264 @@
/*
* Licensed under ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file SPC564Axx/hal_lld.h
* @brief SPC564Axx HAL subsystem low level driver header.
* @pre This module requires the following macros to be defined in the
* @p board.h file:
* - SPC5_XOSC_CLK.
* .
*
* @addtogroup HAL
* @{
*/
#ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
#include "xpc564a.h"
#include "spc564a_registry.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief Defines the support for realtime counters in the HAL.
*/
#define HAL_IMPLEMENTS_COUNTERS FALSE
/**
* @brief Platform name.
*/
#define PLATFORM_NAME "SPC564Axx Powertrain"
/**
* @name ESYNCR2 register definitions
* @{
*/
#define SPC5_RFD_DIV2 0 /**< Divide VCO frequency by 2. */
#define SPC5_RFD_DIV4 1 /**< Divide VCO frequency by 4. */
#define SPC5_RFD_DIV8 2 /**< Divide VCO frequency by 8. */
#define SPC5_RFD_DIV16 3 /**< Divide VCO frequency by 16.*/
/** @} */
/**
* @name BIUCR register definitions
* @{
*/
#define BIUCR_BANK1_TOO 0x01000000 /**< Use settings for bank1 too.*/
#define BIUCR_MASTER7_PREFETCH 0x00800000 /**< Enable master 7 prefetch. */
#define BIUCR_MASTER6_PREFETCH 0x00400000 /**< Enable master 6 prefetch. */
#define BIUCR_MASTER5_PREFETCH 0x00200000 /**< Enable master 5 prefetch. */
#define BIUCR_MASTER4_PREFETCH 0x00100000 /**< Enable master 4 prefetch. */
#define BIUCR_MASTER3_PREFETCH 0x00080000 /**< Enable master 3 prefetch. */
#define BIUCR_MASTER2_PREFETCH 0x00040000 /**< Enable master 2 prefetch. */
#define BIUCR_MASTER1_PREFETCH 0x00020000 /**< Enable master 1 prefetch. */
#define BIUCR_MASTER0_PREFETCH 0x00010000 /**< Enable master 0 prefetch. */
#define BIUCR_APC_MASK 0x0000E000 /**< APC field mask. */
#define BIUCR_APC_0 (0 << 13) /**< No additional hold cycles. */
#define BIUCR_APC_1 (1 << 13) /**< 1 additional hold cycle. */
#define BIUCR_APC_2 (2 << 13) /**< 2 additional hold cycles. */
#define BIUCR_APC_3 (3 << 13) /**< 3 additional hold cycles. */
#define BIUCR_APC_4 (4 << 13) /**< 4 additional hold cycles. */
#define BIUCR_APC_5 (5 << 13) /**< 5 additional hold cycles. */
#define BIUCR_APC_6 (6 << 13) /**< 6 additional hold cycles. */
#define BIUCR_WWSC_MASK 0x00001800 /**< WWSC field mask. */
#define BIUCR_WWSC_0 (0 << 11) /**< No write wait states. */
#define BIUCR_WWSC_1 (1 << 11) /**< 1 write wait state. */
#define BIUCR_WWSC_2 (2 << 11) /**< 2 write wait states. */
#define BIUCR_WWSC_3 (3 << 11) /**< 3 write wait states. */
#define BIUCR_RWSC_MASK 0x00001800 /**< RWSC field mask. */
#define BIUCR_RWSC_0 (0 << 8) /**< No read wait states. */
#define BIUCR_RWSC_1 (1 << 8) /**< 1 read wait state. */
#define BIUCR_RWSC_2 (2 << 8) /**< 2 read wait states. */
#define BIUCR_RWSC_3 (3 << 8) /**< 3 read wait states. */
#define BIUCR_RWSC_4 (4 << 8) /**< 4 read wait states. */
#define BIUCR_RWSC_5 (5 << 8) /**< 5 read wait states. */
#define BIUCR_RWSC_6 (6 << 8) /**< 6 read wait states. */
#define BIUCR_RWSC_7 (7 << 8) /**< 7 read wait states. */
#define BIUCR_DPFEN 0x00000040 /**< Data prefetch enable. */
#define BIUCR_IPFEN 0x00000010 /**< Instr. prefetch enable. */
#define BIUCR_PFLIM_MASK 0x00000060 /**< PFLIM field mask. */
#define BIUCR_PFLIM_NO (0 << 1) /**< No prefetching. */
#define BIUCR_PFLIM_ON_MISS (1 << 1) /**< Prefetch on miss. */
#define BIUCR_PFLIM_ON_HITMISS (2 << 1) /**< Prefetch on hit and miss. */
#define BIUCR_BFEN 0x00000001 /**< Flash buffering enable. */
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @brief Disables the clocks initialization in the HAL.
*/
#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
#define SPC5_NO_INIT FALSE
#endif
/**
* @brief Clock bypass.
* @note If set to @p TRUE then the PLL is not started and initialized, the
* external clock is used as-is and the other clock-related settings
* are ignored.
*/
#if !defined(SPC5_CLK_BYPASS) || defined(__DOXYGEN__)
#define SPC5_CLK_BYPASS FALSE
#endif
/**
* @brief Disables the overclock checks.
*/
#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
#define SPC5_ALLOW_OVERCLOCK FALSE
#endif
/**
* @brief External clock pre-divider.
* @note Must be in range 1...15.
* @note The effective divider factor is this value.
*/
#if !defined(SPC5_CLK_PREDIV) || defined(__DOXYGEN__)
#define SPC5_CLK_PREDIV_VALUE 2
#endif
/**
* @brief Multiplication factor divider.
* @note Must be in range 32...96.
*/
#if !defined(SPC5_CLK_MFD_VALUE) || defined(__DOXYGEN__)
#define SPC5_CLK_MFD_VALUE 80
#endif
/**
* @brief Reduced frequency divider.
*/
#if !defined(SPC5_CLK_RFD) || defined(__DOXYGEN__)
#define SPC5_CLK_RFD RFD_DIV4
#endif
/**
* @brief Flash buffer and prefetching settings.
* @note Please refer to the SPC563M64 reference manual about the meaning
* of the following bits, if in doubt DO NOT MODIFY IT.
* @note Do not specify the APC, WWSC, RWSC bits in this value because
* those are calculated from the system clock and ORed with this
* value.
*/
#if !defined(SPC5_FLASH_BIUCR) || defined(__DOXYGEN__)
#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \
BIUCR_MASTER4_PREFETCH | \
BIUCR_MASTER0_PREFETCH | \
BIUCR_DPFEN | \
BIUCR_IPFEN | \
BIUCR_PFLIM_ON_MISS | \
BIUCR_BFEN)
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*
* Configuration-related checks.
*/
#if !defined(SPC564Axx_MCUCONF)
#error "Using a wrong mcuconf.h file, SPC564Axx_MCUCONF not defined"
#endif
#if (SPC5_CLK_PREDIV_VALUE < 1) || (SPC5_CLK_PREDIV_VALUE > 15)
#error "invalid SPC5_CLK_PREDIV_VALUE value specified"
#endif
#if (SPC5_CLK_MFD_VALUE < 32) || (SPC5_CLK_MFD_VALUE > 96)
#error "invalid SPC5_CLK_MFD_VALUE value specified"
#endif
#if (SPC5_CLK_RFD != SPC5_RFD_DIV2) && (SPC5_CLK_RFD != SPC5_RFD_DIV4) && \
(SPC5_CLK_RFD != SPC5_RFD_DIV8) && (SPC5_CLK_RFD != SPC5_RFD_DIV16)
#error "invalid SPC5_CLK_RFD value specified"
#endif
/**
* @brief PLL input divider.
*/
#define SPC5_CLK_PREDIV (SPC5_CLK_PREDIV_VALUE - 1)
/**
* @brief PLL multiplier.
*/
#define SPC5_CLK_MFD (SPC5_CLK_MFD_VALUE)
/**
* @brief PLL output clock.
*/
#define SPC5_PLLCLK ((SPC5_XOSC_CLK / SPC5_CLK_PREDIV_VALUE) * \
SPC5_CLK_MFD_VALUE)
#if (SPC5_PLLCLK < 256000000) || (SPC5_PLLCLK > 512000000)
#error "VCO frequency out of the acceptable range (256...512)"
#endif
/**
* @brief PLL output clock.
*/
#if !SPC5_CLK_BYPASS || defined(__DOXYGEN__)
#define SPC5_SYSCLK (SPC5_PLLCLK / (1 << (SPC5_CLK_RFD + 1)))
#else
#define SPC5_SYSCLK SPC5_XOSC_CLK
#endif
#if (SPC5_SYSCLK > 150000000) && !SPC5_ALLOW_OVERCLOCK
#error "System clock above maximum rated frequency (150MHz)"
#endif
/**
* @brief Flash wait states are a function of the system clock.
*/
#if (SPC5_SYSCLK <= 30000000) || defined(__DOXYGEN__)
#define SPC5_FLASH_WS (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_1)
#elif SPC5_SYSCLK <= 60000000
#define SPC5_FLASH_WS (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_1)
#else
#define SPC5_FLASH_WS (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_1)
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#include "spc5_edma.h"
#ifdef __cplusplus
extern "C" {
#endif
void hal_lld_init(void);
void spc_clock_init(void);
#ifdef __cplusplus
}
#endif
#endif /* _HAL_LLD_H_ */
/** @} */

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os/hal/platforms/SPC564Axx/platform.mk Normal file
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@ -0,0 +1,13 @@
# List of all the SPC564Axx platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC564Axx/hal_lld.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC564Axx \
${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \
${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1 \
${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1 \
${CHIBIOS}/os/hal/platforms/SPC5xx/SIU_v1

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os/hal/platforms/SPC564Axx/spc564a_registry.h Normal file
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/*
* Licensed under ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file SPC564Axx/spc564a_registry.h
* @brief SPC564Axx capabilities registry.
*
* @addtogroup HAL
* @{
*/
#ifndef _SPC563M_REGISTRY_H_
#define _SPC563M_REGISTRY_H_
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
/**
* @name SPC564Axx capabilities
* @{
*/
/* eDMA attributes.*/
#define SPC5_HAS_EDMAA TRUE
#define SPC5_EDMA_NCHANNELS 64
#define SPC5_EDMA_HAS_MUX FALSE
/* eQADC attributes.*/
#define SPC5_HAS_EQADC TRUE
/* eSCI attributes.*/
#define SPC5_HAS_ESCIA TRUE
#define SPC5_ESCIA_HANDLER vector146
#define SPC5_ESCIA_NUMBER 146
#define SPC5_HAS_ESCIB TRUE
#define SPC5_ESCIB_HANDLER vector149
#define SPC5_ESCIB_NUMBER 149
#define SPC5_HAS_ESCIC TRUE
#define SPC5_ESCIB_HANDLER vector473
#define SPC5_ESCIB_NUMBER 473
/* SIU attributes.*/
#define SPC5_HAS_SIU TRUE
#define SPC5_SIU_SUPPORTS_PORTS FALSE
/** @} */
#endif /* _SPC563M_REGISTRY_H_ */
/** @} */

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os/hal/platforms/SPC564Axx/typedefs.h Normal file
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/*
* Licensed under ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file SPC564Axx/typedefs.h
* @brief Dummy typedefs file.
*/
#ifndef _TYPEDEFS_H_
#define _TYPEDEFS_H_
#include "chtypes.h"
#endif /* _TYPEDEFS_H_ */

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os/hal/platforms/SPC564Axx/xpc564a.h Normal file
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