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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6097 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-08-07 13:03:34 +00:00
parent e0e31ea715
commit 636f02da90
2 changed files with 32 additions and 50 deletions
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20
os/kernel/ports/ARMCMx/devices/STM32F30x/stm32f30x.h
View File

@ -177,7 +177,7 @@ typedef enum IRQn
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the lines 17, 19 & 20 */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
@ -247,7 +247,8 @@ typedef enum IRQn
*/
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_stm32f30x.h" /* STM32F30x System Header */
/* CHIBIOS FIX */
/*#include "system_stm32f30x.h"*/ /* STM32F30x System Header */
#include <stdint.h>
/** @addtogroup Exported_types
@ -553,7 +554,8 @@ typedef struct
/**
* @brief General Purpose I/O
*/
/* CHIBIOS FIX */
#if 0
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
@ -571,6 +573,7 @@ typedef struct
__IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
uint16_t RESERVED3; /*!< Reserved, 0x2A */
}GPIO_TypeDef;
#endif
/**
* @brief Operational Amplifier (OPAMP)
@ -1028,7 +1031,9 @@ typedef struct
/* */
/******************************************************************************/
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
/* CHIBIOS FIX */
//#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
#define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
@ -4749,8 +4754,11 @@ typedef struct
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
#define RCC_APB1ENR_UART3EN ((uint32_t)0x00080000) /*!< UART 3 clock enable */
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00100000) /*!< UART 4 clock enable */
/* CHIBIOS FIX */
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 3 clock enable */
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 4 clock enable */
//#define RCC_APB1ENR_UART3EN ((uint32_t)0x00080000) /*!< UART 3 clock enable */
//#define RCC_APB1ENR_UART4EN ((uint32_t)0x00100000) /*!< UART 4 clock enable */
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */

62
os/kernel/ports/ARMCMx/devices/STM32F30x/systick.h
View File

@ -45,36 +45,10 @@
/* Module data structures and types. */
/*===========================================================================*/
typedef struct {
volatile uint32_t CR1;
volatile uint32_t CR2;
volatile uint32_t SMCR;
volatile uint32_t DIER;
volatile uint32_t SR;
volatile uint32_t EGR;
volatile uint32_t CCMR1;
volatile uint32_t CCMR2;
volatile uint32_t CCER;
volatile uint32_t CNT;
volatile uint32_t PSC;
volatile uint32_t ARR;
volatile uint32_t RCR;
volatile uint32_t CCR[4];
volatile uint32_t BDTR;
volatile uint32_t DCR;
volatile uint32_t DMAR;
volatile uint32_t OR;
volatile uint32_t CCMR3;
volatile uint32_t CCR5;
volatile uint32_t CCR6;
} local_stm32_tim_t;
/*===========================================================================*/
/* Module macros. */
/*===========================================================================*/
#define STM32F3_TIM2 ((local_stm32_tim_t *)0x40000000)
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
@ -90,13 +64,13 @@ typedef struct {
*/
static inline void port_timer_init(void) {
STM32F3_TIM2->ARR = 0xFFFFFFFF;
STM32F3_TIM2->CCMR1 = 0;
STM32F3_TIM2->CCR[0] = 0;
STM32F3_TIM2->DIER = 0;
STM32F3_TIM2->CR2 = 0;
STM32F3_TIM2->EGR = 1; /* UG, CNT initialized. */
STM32F3_TIM2->CR1 = 1; /* CEN */
TIM2->ARR = 0xFFFFFFFF;
TIM2->CCMR1 = 0;
TIM2->CCR1 = 0;
TIM2->DIER = 0;
TIM2->CR2 = 0;
TIM2->EGR = TIM_EGR_UG;
TIM2->CR1 = TIM_CR1_CEN;
}
/**
@ -108,7 +82,7 @@ static inline void port_timer_init(void) {
*/
static inline systime_t port_timer_get_time(void) {
return STM32F3_TIM2->CNT;
return TIM2->CNT;
}
/**
@ -122,13 +96,13 @@ static inline systime_t port_timer_get_time(void) {
*/
static inline void port_timer_start_alarm(systime_t time) {
chDbgAssert((STM32F3_TIM2->DIER & 2) == 0,
chDbgAssert((TIM2->DIER & 2) == 0,
"port_timer_start_alarm(), #1",
"already started");
STM32F3_TIM2->CCR[0] = time;
STM32F3_TIM2->SR = 0;
STM32F3_TIM2->DIER = 2; /* CC1IE */
TIM2->CCR1 = time;
TIM2->SR = 0;
TIM2->DIER = 2; /* CC1IE */
}
/**
@ -138,11 +112,11 @@ static inline void port_timer_start_alarm(systime_t time) {
*/
static inline void port_timer_stop_alarm(void) {
chDbgAssert((STM32F3_TIM2->DIER & 2) != 0,
chDbgAssert((TIM2->DIER & 2) != 0,
"port_timer_stop_alarm(), #1",
"not started");
STM32F3_TIM2->DIER = 0;
TIM2->DIER = 0;
}
/**
@ -154,11 +128,11 @@ static inline void port_timer_stop_alarm(void) {
*/
static inline void port_timer_set_alarm(systime_t time) {
chDbgAssert((STM32F3_TIM2->DIER & 2) != 0,
chDbgAssert((TIM2->DIER & 2) != 0,
"port_timer_set_alarm(), #1",
"not started");
STM32F3_TIM2->CCR[0] = time;
TIM2->CCR1 = time;
}
/**
@ -170,11 +144,11 @@ static inline void port_timer_set_alarm(systime_t time) {
*/
static inline systime_t port_timer_get_alarm(void) {
chDbgAssert((STM32F3_TIM2->DIER & 2) != 0,
chDbgAssert((TIM2->DIER & 2) != 0,
"port_timer_get_alarm(), #1",
"not started");
return STM32F3_TIM2->CCR[0];
return TIM2->CCR1;
}
#endif /* _CHTIMER_H_ */