From 633098ebcd87d2a654deede6feff0d93fdabaebc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 6 Dec 2012 10:53:16 +0000 Subject: [PATCH] STM32F3 SPI working, STM32F0 support update. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4879 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/ST_STM32F0_DISCOVERY/board.h | 3 +- boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg | 6 +- demos/ARMCM0-STM32F051-DISCOVERY/mcuconf.h | 2 +- os/hal/platforms/STM32/GPIOv2/pal_lld.h | 5 +- os/hal/platforms/STM32F0xx/hal_lld.c | 20 +- os/hal/platforms/STM32F0xx/hal_lld.h | 40 +- readme.txt | 2 +- testhal/STM32F0xx/ADC/mcuconf.h | 2 +- testhal/STM32F0xx/EXT/mcuconf.h | 2 +- testhal/STM32F0xx/IRQ_STORM/mcuconf.h | 2 +- testhal/STM32F0xx/PWM-ICU/mcuconf.h | 2 +- testhal/STM32F0xx/SPI/.cproject | 51 ++ testhal/STM32F0xx/SPI/.project | 38 ++ testhal/STM32F0xx/SPI/Makefile | 207 +++++++ testhal/STM32F0xx/SPI/chconf.h | 535 ++++++++++++++++++ testhal/STM32F0xx/SPI/halconf.h | 342 +++++++++++ testhal/STM32F0xx/SPI/main.c | 166 ++++++ testhal/STM32F0xx/SPI/mcuconf.h | 144 +++++ testhal/STM32F0xx/SPI/readme.txt | 30 + testhal/STM32F0xx/UART/mcuconf.h | 2 +- testhal/STM32F3xx/SPI/.cproject | 51 ++ testhal/STM32F3xx/SPI/.project | 38 ++ testhal/STM32F3xx/SPI/Makefile | 221 ++++++++ testhal/STM32F3xx/SPI/chconf.h | 535 ++++++++++++++++++ testhal/STM32F3xx/SPI/halconf.h | 342 +++++++++++ testhal/STM32F3xx/SPI/main.c | 166 ++++++ testhal/STM32F3xx/SPI/mcuconf.h | 96 ++++ testhal/STM32F3xx/SPI/readme.txt | 30 + .../config_wizard/META-INF/MANIFEST.MF | 2 +- .../boards/stm32f0xx/templates/board.h.ftl | 10 +- .../gencfg/schema/boards/stm32f0xx_board.xsd | 13 + ...rg.chibios.tools.eclipse.config_1.2.1.jar} | Bin 1875314 -> 1875433 bytes 32 files changed, 3062 insertions(+), 43 deletions(-) create mode 100644 testhal/STM32F0xx/SPI/.cproject create mode 100644 testhal/STM32F0xx/SPI/.project create mode 100644 testhal/STM32F0xx/SPI/Makefile create mode 100644 testhal/STM32F0xx/SPI/chconf.h create mode 100644 testhal/STM32F0xx/SPI/halconf.h create mode 100644 testhal/STM32F0xx/SPI/main.c create mode 100644 testhal/STM32F0xx/SPI/mcuconf.h create mode 100644 testhal/STM32F0xx/SPI/readme.txt create mode 100644 testhal/STM32F3xx/SPI/.cproject create mode 100644 testhal/STM32F3xx/SPI/.project create mode 100644 testhal/STM32F3xx/SPI/Makefile create mode 100644 testhal/STM32F3xx/SPI/chconf.h create mode 100644 testhal/STM32F3xx/SPI/halconf.h create mode 100644 testhal/STM32F3xx/SPI/main.c create mode 100644 testhal/STM32F3xx/SPI/mcuconf.h create mode 100644 testhal/STM32F3xx/SPI/readme.txt rename tools/eclipse/plugins/{org.chibios.tools.eclipse.config_1.2.0.jar => org.chibios.tools.eclipse.config_1.2.1.jar} (99%) diff --git a/boards/ST_STM32F0_DISCOVERY/board.h b/boards/ST_STM32F0_DISCOVERY/board.h index 65e5595aa..24c5899d6 100644 --- a/boards/ST_STM32F0_DISCOVERY/board.h +++ b/boards/ST_STM32F0_DISCOVERY/board.h @@ -31,7 +31,6 @@ #define BOARD_ST_STM32F0_DISCOVERY #define BOARD_NAME "ST STM32F0-Discovery" - /* * Board oscillators-related settings. * NOTE: LSE not fitted. @@ -41,6 +40,8 @@ #define STM32_LSECLK 0 #endif +#define STM32_LSEDRV (3 << 3) + #if !defined(STM32_HSECLK) #define STM32_HSECLK 0 #endif diff --git a/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg b/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg index f69d6ca66..3773f03d1 100644 --- a/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg +++ b/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg @@ -10,10 +10,8 @@ ST STM32F0-Discovery ST_STM32F0_DISCOVERY - + BDCR |= RCC_BDCR_LSEON; +#if defined(STM32_LSE_BYPASS) + /* LSE Bypass.*/ + RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; +#else + /* No LSE Bypass.*/ + RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON; +#endif while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) ; /* Waits until LSE is stable. */ #endif @@ -172,10 +174,10 @@ void stm32_clock_init(void) { #endif /* Clock settings.*/ - RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE | - STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE | - STM32_HPRE; - RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW | + RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC | + STM32_ADCPRE | STM32_PPRE | STM32_HPRE; + RCC->CFGR2 = STM32_PREDIV; + RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW | STM32_USART1SW; #if STM32_ACTIVATE_PLL diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h index d38248ce5..775892391 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.h +++ b/os/hal/platforms/STM32F0xx/hal_lld.h @@ -24,6 +24,8 @@ * @pre This module requires the following macros to be defined in the * @p board.h file: * - STM32_LSECLK. + * - STM32_LSEDRV. + * - STM32_LSE_BYPASS (optionally). * - STM32_HSECLK. * - STM32_HSE_BYPASS (optionally). * . @@ -170,9 +172,6 @@ #define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ #define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ -#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */ -#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */ - #define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ #define STM32_MCOSEL_HSI14 (3 << 24) /**< HSI14 clock on MCO pin. */ #define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ @@ -506,11 +505,11 @@ * @brief Crystal PLL pre-divider. * @note This setting has only effect if the PLL is selected as the * system clock source. - * @note The default value is calculated for a 48MHz system clock from + * @note The default value is calculated for a 72MHz system clock from * a 8MHz crystal using the PLL. */ -#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__) -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__) +#define STM32_PREDIV_VALUE 1 #endif /** @@ -704,6 +703,18 @@ #error "LSE frequency not defined" #endif +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#if !defined(STM32_LSEDRV) +#error "STM32_LSEDRV not defined" +#endif + +#if (STM32_LSEDRV >> 3) > 3 +#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))" +#endif + #if STM32_CECSW == STM32_CECSW_LSE #error "LSE not enabled, required by STM32_CECSW" #endif @@ -712,10 +723,6 @@ #error "LSE not enabled, required by STM32_USART1SW" #endif -#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) -#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" -#endif - #else /* !STM32_LSE_ENABLED */ #if STM32_RTCSEL == STM32_RTCSEL_LSE @@ -737,9 +744,10 @@ #endif /* HSE prescaler setting check.*/ -#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \ - (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2) -#error "invalid STM32_PLLXTPRE value specified" +#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16)) +#define STM32_PREDIV ((STM32_PREDIV_VALUE - 1) << 0) +#else +#error "invalid STM32_PREDIV value specified" #endif /** @@ -756,11 +764,7 @@ * @brief PLL input clock frequency. */ #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1 -#define STM32_PLLCLKIN (STM32_HSECLK / 1) -#else -#define STM32_PLLCLKIN (STM32_HSECLK / 2) -#endif +#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PREDIV_VALUE) #elif STM32_PLLSRC == STM32_PLLSRC_HSI #define STM32_PLLCLKIN (STM32_HSICLK / 2) #else diff --git a/readme.txt b/readme.txt index 48043cd65..c5ec1bf0a 100644 --- a/readme.txt +++ b/readme.txt @@ -145,7 +145,7 @@ (backported to 2.4.3). - FIX: Fixed STM8L, cosmic compiler: c_lreg not saved (bug 3566342)(backported to 2.2.10 and 2.4.3). -- NEW: Initial support for STM32F30x. +- NEW: Initial support for STM32F30x (HAL, PAL, Serial, SPI). - NEW: AT91SAM7A3 I2C support. - NEW: AT91SAM7A3 basic support. - NEW: Unified the STM32F4xx and STM32F2xx platform code. The STM32F2xx now is diff --git a/testhal/STM32F0xx/ADC/mcuconf.h b/testhal/STM32F0xx/ADC/mcuconf.h index 4cda58614..a78a09471 100644 --- a/testhal/STM32F0xx/ADC/mcuconf.h +++ b/testhal/STM32F0xx/ADC/mcuconf.h @@ -47,7 +47,7 @@ #define STM32_LSE_ENABLED FALSE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSI -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PREDIV_VALUE 1 #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 diff --git a/testhal/STM32F0xx/EXT/mcuconf.h b/testhal/STM32F0xx/EXT/mcuconf.h index e635e00b3..f3b8dc629 100644 --- a/testhal/STM32F0xx/EXT/mcuconf.h +++ b/testhal/STM32F0xx/EXT/mcuconf.h @@ -47,7 +47,7 @@ #define STM32_LSE_ENABLED FALSE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSI -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PREDIV_VALUE 1 #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 diff --git a/testhal/STM32F0xx/IRQ_STORM/mcuconf.h b/testhal/STM32F0xx/IRQ_STORM/mcuconf.h index f1e7ab918..e08f91123 100644 --- a/testhal/STM32F0xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32F0xx/IRQ_STORM/mcuconf.h @@ -47,7 +47,7 @@ #define STM32_LSE_ENABLED FALSE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSI -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PREDIV_VALUE 1 #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 diff --git a/testhal/STM32F0xx/PWM-ICU/mcuconf.h b/testhal/STM32F0xx/PWM-ICU/mcuconf.h index fc02500bd..7bae2ccf1 100644 --- a/testhal/STM32F0xx/PWM-ICU/mcuconf.h +++ b/testhal/STM32F0xx/PWM-ICU/mcuconf.h @@ -47,7 +47,7 @@ #define STM32_LSE_ENABLED FALSE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSI -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PREDIV_VALUE 1 #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 diff --git a/testhal/STM32F0xx/SPI/.cproject b/testhal/STM32F0xx/SPI/.cproject new file mode 100644 index 000000000..d5cace391 --- /dev/null +++ b/testhal/STM32F0xx/SPI/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F0xx/SPI/.project b/testhal/STM32F0xx/SPI/.project new file mode 100644 index 000000000..be544ce50 --- /dev/null +++ b/testhal/STM32F0xx/SPI/.project @@ -0,0 +1,38 @@ + + + STM32F0xx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F0_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F0xx/SPI/Makefile b/testhal/STM32F0xx/SPI/Makefile new file mode 100644 index 000000000..0b2d556fb --- /dev/null +++ b/testhal/STM32F0xx/SPI/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F0_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F0xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F0xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F051x8.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F0xx/SPI/chconf.h b/testhal/STM32F0xx/SPI/chconf.h new file mode 100644 index 000000000..290044421 --- /dev/null +++ b/testhal/STM32F0xx/SPI/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F0xx/SPI/halconf.h b/testhal/STM32F0xx/SPI/halconf.h new file mode 100644 index 000000000..f70fd1b9d --- /dev/null +++ b/testhal/STM32F0xx/SPI/halconf.h @@ -0,0 +1,342 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F0xx/SPI/main.c b/testhal/STM32F0xx/SPI/main.c new file mode 100644 index 000000000..a6ef95214 --- /dev/null +++ b/testhal/STM32F0xx/SPI/main.c @@ -0,0 +1,166 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig hs_spicfg = { + NULL, + GPIOB, + 12, + 0, + SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0 +}; + +/* + * Low speed SPI configuration (140.625kHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig ls_spicfg = { + NULL, + GPIOB, + 12, + SPI_CR1_BR_2 | SPI_CR1_BR_1, + SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0 +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palSetPad(GPIOC, GPIOC_LED4); /* LED ON. */ + spiStart(&SPID2, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palClearPad(GPIOC, GPIOC_LED4); /* LED OFF. */ + spiStart(&SPID2, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} +/* + * This is a periodic thread that does absolutely nothing except flashing + * a LED. + */ +static WORKING_AREA(blinker_wa, 128); +static msg_t blinker(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOC, GPIOC_LED3); + chThdSleepMilliseconds(500); + palClearPad(GPIOC, GPIOC_LED3); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * SPI2 I/O pins setup. + */ + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(0) | + PAL_STM32_OSPEED_HIGHEST); /* New SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(0) | + PAL_STM32_OSPEED_HIGHEST); /* New MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(0) | + PAL_STM32_OSPEED_HIGHEST); /* New MOSI. */ + palSetPad(GPIOB, 12); + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); /* New CS. */ + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Starting the blinker thread. + */ + chThdCreateStatic(blinker_wa, sizeof(blinker_wa), + NORMALPRIO-1, blinker, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F0xx/SPI/mcuconf.h b/testhal/STM32F0xx/SPI/mcuconf.h new file mode 100644 index 000000000..65d04e7f7 --- /dev/null +++ b/testhal/STM32F0xx/SPI/mcuconf.h @@ -0,0 +1,144 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32F0xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F0xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_HSI14_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 12 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE STM32_PPRE_DIV1 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_CECSW STM32_CECSW_HSI +#define STM32_I2C1SW STM32_I2C1SW_HSI +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 2 +#define STM32_GPT_TIM2_IRQ_PRIORITY 2 +#define STM32_GPT_TIM3_IRQ_PRIORITY 2 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 3 +#define STM32_ICU_TIM2_IRQ_PRIORITY 3 +#define STM32_ICU_TIM3_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 3 +#define STM32_PWM_TIM2_IRQ_PRIORITY 3 +#define STM32_PWM_TIM3_IRQ_PRIORITY 3 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USART1_PRIORITY 3 +#define STM32_SERIAL_USART2_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 2 +#define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() diff --git a/testhal/STM32F0xx/SPI/readme.txt b/testhal/STM32F0xx/SPI/readme.txt new file mode 100644 index 000000000..636a7c248 --- /dev/null +++ b/testhal/STM32F0xx/SPI/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for STM32F0xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F0-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F0xx SPI driver. + +** Board Setup ** + +- Connect PB14 and PB15 together for SPI loop-back. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F0xx/UART/mcuconf.h b/testhal/STM32F0xx/UART/mcuconf.h index e148ed6bb..09ddbd969 100644 --- a/testhal/STM32F0xx/UART/mcuconf.h +++ b/testhal/STM32F0xx/UART/mcuconf.h @@ -47,7 +47,7 @@ #define STM32_LSE_ENABLED FALSE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSI -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PREDIV_VALUE 1 #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 diff --git a/testhal/STM32F3xx/SPI/.cproject b/testhal/STM32F3xx/SPI/.cproject new file mode 100644 index 000000000..bd3a84398 --- /dev/null +++ b/testhal/STM32F3xx/SPI/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F3xx/SPI/.project b/testhal/STM32F3xx/SPI/.project new file mode 100644 index 000000000..9e4e53e90 --- /dev/null +++ b/testhal/STM32F3xx/SPI/.project @@ -0,0 +1,38 @@ + + + STM32F3xx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F3_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F3xx/SPI/Makefile b/testhal/STM32F3xx/SPI/Makefile new file mode 100644 index 000000000..a2cf0e690 --- /dev/null +++ b/testhal/STM32F3xx/SPI/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F3_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F3xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F303xc.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F3xx/SPI/chconf.h b/testhal/STM32F3xx/SPI/chconf.h new file mode 100644 index 000000000..290044421 --- /dev/null +++ b/testhal/STM32F3xx/SPI/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F3xx/SPI/halconf.h b/testhal/STM32F3xx/SPI/halconf.h new file mode 100644 index 000000000..d176ad1a7 --- /dev/null +++ b/testhal/STM32F3xx/SPI/halconf.h @@ -0,0 +1,342 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F3xx/SPI/main.c b/testhal/STM32F3xx/SPI/main.c new file mode 100644 index 000000000..27085cd24 --- /dev/null +++ b/testhal/STM32F3xx/SPI/main.c @@ -0,0 +1,166 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig hs_spicfg = { + NULL, + GPIOB, + 12, + 0, + SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0 +}; + +/* + * Low speed SPI configuration (140.625kHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig ls_spicfg = { + NULL, + GPIOB, + 12, + SPI_CR1_BR_2 | SPI_CR1_BR_1, + SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0 +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palSetPad(GPIOE, GPIOE_LED10_RED); /* LED ON. */ + spiStart(&SPID2, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palClearPad(GPIOE, GPIOE_LED10_RED);/* LED OFF. */ + spiStart(&SPID2, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} +/* + * This is a periodic thread that does absolutely nothing except flashing + * a LED. + */ +static WORKING_AREA(blinker_wa, 128); +static msg_t blinker(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOE, GPIOE_LED3_RED); + chThdSleepMilliseconds(500); + palClearPad(GPIOE, GPIOE_LED3_RED); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * SPI2 I/O pins setup. + */ + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* New SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* New MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* New MOSI. */ + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); /* New CS. */ + palSetPad(GPIOB, 12); + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Starting the blinker thread. + */ + chThdCreateStatic(blinker_wa, sizeof(blinker_wa), + NORMALPRIO-1, blinker, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F3xx/SPI/mcuconf.h b/testhal/STM32F3xx/SPI/mcuconf.h new file mode 100644 index 000000000..910bdd009 --- /dev/null +++ b/testhal/STM32F3xx/SPI/mcuconf.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F30x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADC12PRES STM32_ADC12PRES_DIV1 +#define STM32_ADC34PRES STM32_ADC34PRES_DIV1 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_UART4SW STM32_UART4SW_PCLK +#define STM32_UART5SW STM32_UART5SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_TIM1SW STM32_TIM1SW_PCLK2 +#define STM32_TIM8SW STM32_TIM8SW_PCLK2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() diff --git a/testhal/STM32F3xx/SPI/readme.txt b/testhal/STM32F3xx/SPI/readme.txt new file mode 100644 index 000000000..285d9c724 --- /dev/null +++ b/testhal/STM32F3xx/SPI/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for STM32F3xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F3-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F3xx SPI driver. + +** Board Setup ** + +- Connect PB14 and PB15 together for SPI loop-back. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/tools/eclipse/config_wizard/META-INF/MANIFEST.MF b/tools/eclipse/config_wizard/META-INF/MANIFEST.MF index 30e998e6f..37f4f5b08 100644 --- a/tools/eclipse/config_wizard/META-INF/MANIFEST.MF +++ b/tools/eclipse/config_wizard/META-INF/MANIFEST.MF @@ -2,7 +2,7 @@ Manifest-Version: 1.0 Bundle-ManifestVersion: 2 Bundle-Name: ChibiOS-RT_Configuration_Support Bundle-SymbolicName: org.chibios.tools.eclipse.config;singleton:=true -Bundle-Version: 1.2.0 +Bundle-Version: 1.2.1 Bundle-Activator: config_wizard.Activator Require-Bundle: org.eclipse.core.resources;bundle-version="3.7.101", org.eclipse.core.runtime;bundle-version="3.7.0", diff --git a/tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f0xx/templates/board.h.ftl b/tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f0xx/templates/board.h.ftl index 30fda47df..6eb360b6c 100644 --- a/tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f0xx/templates/board.h.ftl +++ b/tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f0xx/templates/board.h.ftl @@ -47,8 +47,8 @@ [#if doc1.board.ethernet_phy.bus_type[0]?string == "RMII"] #define BOARD_PHY_RMII [/#if] -[/#if] +[/#if] /* * Board oscillators-related settings. [#if doc1.board.clocks.@LSEFrequency[0]?number == 0] @@ -62,14 +62,20 @@ #define STM32_LSECLK ${doc1.board.clocks.@LSEFrequency[0]} #endif +[#if doc1.board.clocks.@LSEBypass[0]?string == "true"] +#define STM32_LSE_BYPASS + +[/#if] +#define STM32_LSEDRV (${doc1.board.clocks.@LSEDrive[0]?word_list[0]?number} << 3) + #if !defined(STM32_HSECLK) #define STM32_HSECLK ${doc1.board.clocks.@HSEFrequency[0]} #endif [#if doc1.board.clocks.@HSEBypass[0]?string == "true"] #define STM32_HSE_BYPASS -[/#if] +[/#if] /* * MCU type as defined in the ST header file stm32f0xx.h. */ diff --git a/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f0xx_board.xsd b/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f0xx_board.xsd index 59b6e3d68..fb41cf6ea 100644 --- a/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f0xx_board.xsd +++ b/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f0xx_board.xsd @@ -41,6 +41,19 @@ + + + + + + + + + + + + diff --git a/tools/eclipse/plugins/org.chibios.tools.eclipse.config_1.2.0.jar b/tools/eclipse/plugins/org.chibios.tools.eclipse.config_1.2.1.jar similarity index 99% rename from tools/eclipse/plugins/org.chibios.tools.eclipse.config_1.2.0.jar rename to tools/eclipse/plugins/org.chibios.tools.eclipse.config_1.2.1.jar index dfe509154d5b93cd7167ead2dc7a9b05a1c2abff..e29e8a94627590ef2687d821d0a59c5a12b4be2f 100644 GIT binary patch delta 8723 zcmaJ`2Rv2p|G)O$+c`Fok@YP^WE3f@g{;V4*UTtx_TJ+tlroDl!ZkxELW+d4i=vE- zM5+I|=lZJK_xJkW*XwybVDBq|_)BB?{GM9+^TX zM%8K_sUGpfFC`>JRRD9+fLNCCQQ8XMp`7t&8dq)UC`8Op8InAan0Ke(T&(?6Z4qIG z?y)&0`@~Fn^3o$Ghi7aD+D6u?y7JBkq*exFz2BuLC+lxIl2R}=ykmRc?Vmt4(LXr) z&ZcaL**LLoqqlQxsAeB9zovK2F~&|}u-e8h*}1*!^?;0+$ZK*FOucu#T*-OnGPF|F zd;T|I0aziKS$;B(4try@;GjvoNzWR>3Wb$er< zKap%vQFd!XKh$9L%v^dWbuimT*!#F;nX0D#TOBKm$9pDS`>$qpZK@iD&RFf&wf5_7 z@oYB8yHzOwfP)ebzG0}frVXj{F8L-~Ry~3OZwYO*jof-)+u#3d?S-aEs@_eVN8?)l zzkF?0=?iJfVw{t!?;Ragsh_30WiSw*%U2e|+-NtloMpgTS^55nibvyfmdk>bib3oR zx)cIOuFO?SNKxg@tj{6k)1;DlPFt#jz@hDfxKdV)k_w=V}BjRPsu zEJ&%50cTPXq_&_0((aRTBJD0xge;Xz66qRJ2}0M%K~jLgMRn94KM?vN0P>|Jk>N>m z$W#%{aWWmG79&56)IsF3NyM0PZeBXjn9?^S2xgVM`1}O*^aoP*Y z!w5`Abrh)$sbp~V!!W9JVx+-MD~2@kkI~}?bQsHs5M+}n9~lYDWsS;ZC4vhvTu89F ztfXxuIEg50PExp#!G#X^Qe>9PW32$n^CC>v)-tmq0z9@!Akz&xrUi zKMTZ=AuZoez%RTveoFuuzJ*x>vsMCmhmX|7f?WspqAtyC!QsM29zhG z!-XMR-gGzy-u#516nRhvnr8$7XiOet#I#<%oYwOW9KB{F#jo3HZ(#}PMiLe2>l{Av zW29qpr$JjtxTD>F*suOV)V(gpqRGLQrOd~j&lSB6SUsv68J)yz5wCb3o;4o(c&=CV zbNk&7lVn%r67qa5M7BF`6d!47y4_>e@PkB}VyHRXdphhBMRfqB!&qaj1*DmvnM8pZ zJ7e`ohjaT3@8c|G+LdxN1(W}~oS#Y-&xLI$Im2E6+6tFjC)#s4+Fx82xG2PXoTw#M zD4io@F;UzSC6DfS>K6l=CyX=E@ZXS&Hj$w@AuyifOYZT+oPC7e=bc0p!|l$fUOKK3 zNACOKXAXr*?2qy1w$(OxLqx}L>@Cyg7-q9oaf!mCFO+e4T5L%0*is0Gu#N6zt*;bQ zTOFpy^OsvI^Wy{bXyuHxTP*~xE^K{##VT?qTVc#|Dpnn=^8DPjrtbBvY%}{w9>awX zpsGvJUEl2w%PA^10_%Dnm!At z^z!!3*B>+42tCnxq9Z&5b5GbAb4zBedlNHcG_`dc-12;tr}cnR()yc9uYKWa_q1_W zT#6`~(V2QStt2>ITleEjSHQ}LYzdERbC zN9$YT$3yM08ZXDEFNJq-ma%BcyPO|-F8e#KgX%PbeNQv}_6Tal9>1eE(LDY1V2Fz~GwjG(EhxGqFlM%}Yhp?-5UAgnS$( zG;6ls)ji(VYhoy{`G=F#%U8WtvEEimiRrb5 zLH_oq^7@%VV9HxTt6tz%oxGMuR+YtPjA8UzqR|P4Aq!dMDdT5`bt5NCI%CC7tQcKY zyWGsgLi4n8`C%*fo2oIEG)6t!)1aSpnq_A9yCrkbPvJz5tR3xwXme)g4rlp8P>DAy zc~-_R)I$E4a2Zo3r<{Yd@LH*KVeb~-(Mr~)0lh5~+UuF(1Rf>!fW)`#v7m1pzZx9V3s z8D&=CTb=1yTe9dVlx-w`Kl4k#%gP+|l6YiM@M}r00!u0R_5McRQss{a8^g{^eCWSG z7uxpmwerC;gUa5C8{C28fz9?jwKRv0c&Mf>=3SV&GIdq>?I)4izK|vQ2G089JukK~ zfgfCzXn|2NuP}GZNs{CCt_R~TovKD&AY=O@Y+48oU|d!ABrCzm`INN%@o?K}fy++cJ#9I|s;A%7w-mLj}G zcgK?d3B^MF+@WCY@t(ODcFCCS?)8RK;h1ymVPWTtm~X5Gi+FyNFMF9*?Mm?p z8@J}Fd#{it?mZ{e!34_taNH_LpRIVomCvcZNwOi_^xW;amaM34fM<8wXy&R`-avN8 z(~Z;*k6ibw&^)=*TQe3rHzTyFW%?ZT*{AA?16AOc3+JSb^eRt&XxuV-)4R!JEy&`H z$^9u>eMU^_?2ef=D0xE~d8gL(ML@x0DJ{|V7hkiChMc6``ezqm0}oVnOFtYo-%A z)ZBKyW_wx5tPMfwF6Z>2#8168fKRxz zKkusxv&<<+d+{^(3-r@#G3aHN7^O~K$JX~aeECeo*~iDnH@PNvPHK4$bGs;Jz9s|1 z8(0=J5Sx7DYw(&4zx=N&vR$zu{!MI{sUOuVaE(fJNRq|W4tw%*({CNL)L5q5*$X}h?mE4 zPyVDz==((@oWcGh;7nw>6^#ppTITSSaQh3PHZ1YQtzRWlKbBgZvyQ(V2y`ozyxf6K zDZ9PgA+U30D|GyHfggPCGPzU>&gXA;Ey$WAee?f!uXh$jHSRw7<2p)hF$_>#mWkTdC18S zf;A3f;jsc@D%-oL!tDTAWt>$0MsfEvO(D(NQI?60Q%!kM^WtW=VLk9)@xMKIm;Uu*pI#qqGtp!{Na6wcj9PWLwPw`i?2 zm3dnGGKmQ1`z^~Os7rNj^-8DuVm>E7Nq3M7{(8eg-9pi==-_Pi^;(@M!%_V+{(ek} zG&c_?8E*?R+cqBq-y04!4>Ol;Hq_WYa_P%yv?w^U{H^SZod11A9%VCM=VlBzc9FWI zDtjq-ds748aa6w7MPJvhxBj-34obb0-yl{yGZXxJQoWJGoTvHMfNxO{dOopD#Pq>6 zCz26{DyUzY@AfQH-4mh{cfwLvgd8Ku`r_SG6YWs7D;L#l0TJP*R#i|l-LEMEY*@hw_QkP6@8v<8Xs>Be&jq{g?z?Z7Yi z7Ox{XgO?+51>H!faBn$0QHG!g6o3ZRG1CJyrOe_F+zyGc6%0%yXLCkpc9?!<-Cq76 ze3V3UP&}hrTh3tQsplib=^O?%trp8I-oQIdex?_voa;lG=v?RO+QwQL&bPd39qt=s z+3~&`zVCH~<)>j|iS;g>_xy3&x3x)+6`qz8UQ{`vuA|SjQp)B>*Tg8;G*CV3Won6e z-6MI!rAD{#-VR8=?`!CG!FzJ^KobTmirFpIciGuh%h3NR=hhz`;DXuSyosJdq6_$-njs=*_ z?}Jk>Ubw$kHBzD-Z&)MKHTxK+=^*^I!#KV=UI0#O58HQh6JX8j1mQXI3_TKohb|X? z3{>CLRQev&%duJcVU{>8`SjCPO$Cpgk$$o#>5b+UVoJ}}cpsZP9=%oKFctpKu(EBU zN(5JzS!9CRN(0Isd`A_!FbfV?c`%1CX6J9^1zmE!heV(LXyIf`GA-TP#xo)v`sl4gI zte(=)T6%+py`(YzZHIQ#*_@_R@zUyB)wntjdh`h$= zmSvc5M3;74h}oc*u8_(Py8d&e>7uh)QSV}toL{;eM7VxE*dnRmnV~ z5fCzTP^6=i`itYh-Ql9SahJMDhekK61o_pM?PhMKJY+{6zSo~fZG4tW(@vIo>e?)` zUH7w8Y~8ce3=y4;b*E_Kn3&R|?#3BBufopEzjW6W5?oby0M6Op7Fs)zexY9vlhH=1Ua?EG*#ql5rV zeCDm3z*4!@ugZYj&g}$X^(`MkHmfHS|9Hzsib5TBK%uY)y}{G?`?H5Byr3MoLcD2!8^k%pkU$o|3Vpf?(jueV zxY1r@6qNkSIDx|g1P+su;CO@>{?dR_f?zsLJO}|^02TBmXxGv_4vO1_+=2kg|0o{~ zh9w4eC9Va7%!r3LJt7XMG8j}u`k!Gb9!q#WyzIQuzFwE?{u{LZFjyrLI*I|2>r@DN z$R^UX+oaqFF8v)Sf~RC6c*=FsG*2>?|M>X@1N$jNhQp8>REfW$K)?tRFrJ4DuYnTC za|B<5S(0%qybz-xNCCB8+l^E|4tcqU&_Ns_AaaogiHE=lNdB)59qz)59=aCtr=sT` z%mlst7eN%8_7DI%8v3UW6UA>zDD+Qb=6@i|QXqY1*q?fpdnj$DK1c?c{fi>@eh{Dx zQ0u=aGCxL;Y&Zz~zp>*Zh+Py;;Q-&?nM5emfv`eL*>FJf!gqZwhYb-EQ6Up{)DdL; z-!rO(2uS<8x&E<4kaN2_HfdVP9L}>yc-isnIfX(Mg!n<$5g>Be3nfRutBxKjivW3% z3GT!7m7w_ukRR#OM#6m+NGuW*K>DX}{ZEi%B#3+jfMVhP;S^SUs@r%w9&ony`n|I7 zjyQ_;QYT?ZQ3cOPQM3e(oP#D|eS~-iM@$cKMeQ0o5(NVh>1@#LbT$^qJ!&^9LGUo< zR2vtvwV=Jw|I1z}R^8?ED-(DkyN*Z?h{f{jTA3$0z?fMH0D3mC?pD7cVsR$!brH80vcXuGZ zSeW@z8UaiNRipv*(AC)8V8-EOw$kxF!JlIIpoLhF1?O019E^}>?ICi=3YMHQU!8-u zc}s2->KK6^XP}fg@GKG&BL11;Q6dy-1%CZHNg$L{w8zH_wZy}zw^IaA{IRZ)r-iKJ zVcQcWgtExjAm|Ma;wbwAQcM8Zkw_XPz>sz09z+TKd#W1BoCr z;`Z+k2q=^xf!pW136=PvlkxZ{L2ZdJX+h85`2M6_TrCO49s2*q;SUcK(1WDiS!l)y z)x9JX5``p_cX8!p821?>#QC5*$sn^bZV_tM$k^M$uh&9?C=@(7d%uE^@mT=n;p*$) zQHg$rZ_3kl$i(XX4&tivn5 zPZWjXClK;p0id=mfD3w_0jNJgK#FXQo+s<$QD9Gsh}J}xUkx@T>%Sygsln_ z2-W}CC0zOe&_V&JAT6Tc8(HIL3!g*`*ik4E0)^6Fy9!gk06M4_RzPO{Z7RHzoF)hH z-Z7_vY{;;98a(Vq141o~pehsqflLVf-p85!D3k^PeLf>1s|hVZyUaTfOcBquOJSO| zn|fE$am*kxEDquBMi6?$>L(mVBKRjZ51U3Xgl=8@H^vQFW$l{k&4BfWq;@g*PmK!- z{?`qaOc*Pc|BbOigq(#cyBK_}@&_jm&izO=1lte)6|((yGXV#I$Nqo_89(UlLBMY( z-Lqh=E<*(3f$nC3+(>E-aK*EQz*F2zgF?v?gmm2q;?IU%!hKMMNUwvu$h!G`d4od9 z5y*Ey>eoSagcJ>kG2y-?0`TdFP)NvRkCgjATj@;7d+9z{O$z>FAXGCm+f$>1_TK=x z5HrDQL?%tJyd}K-63Y8q?#a_a(KkSD#COAksl`}0iH6`zlp*jv9BR7(sv$!4&x}o* zVIkb57$Ip4#Fq`KBSJS(*37uXsDmvNreh|A$p#N1?s3wga}wZJylYb;P+R z0O>ozUl$p3c9#)f4!oD3U7@5LkOz`>1*svbT#y#AhrF-DRN3&(PMBAdP+|`F41R97J~M*~Wd zkPOLK^d@Ea&N){~@Av(m?|+|XKYRGC^;>HXYwvyc`Bd#Y|InAw_y8pp9R`ELU=mED zQyE3^@utxlri^B^5vghd#DhlI9faES&;0TQ1MRxTl}%Bs(%VHTMl$_Ll!*cTr{0z~ z+#)&OE+mY2_Al=6zVF?@A^rHxSDv;@=9b;g`2kbU#RLTMr@L_91i#iFXiMwj^$X3r zR(Y*?{|(`C@Z?lZ!h;*)2j#mz=I-oeP0%TJYmVRA6Ki?%>M`T}WegQWhmSjVm6)@Z z@dr6R(YUL$zfYwt=%_{6gPsiG^N&AlA>~me?5*A%r4UEuw#{v4sFAQem5z#dJ;OrF zJ+Ih-ynp&QrUD+ietaylB<0ucfEUru-?}uek|;U1AhKf_S2QNpANhiHX;4Jpcv(VQ zU|M>KxqK1-m13%La7XQE{4L_%QKqXHWpmn3yQc!LFDf14FI&;}8ea}qXFjNsT^77mlT6XD*mQtPWQYz=l(SqJkHN)!Z`AggNr`s#$vW?hpr;fH5Jg{-at3cUy zH8`8%+LVG?pSLzr_)DW-Cr_V0;%pY9Wg(mASDBQ(eM_BIg3|!5|7O4x6Wj0Uf#)TC zib9MM$+@rsXs&|gM{}F?oQM@c>({YTXx@k2jpi(rd(hmNQX9>)DfglI5T)jNeJ6CO z8o;I7QqiFe?o`5PZi@rb%c;20@)N4vl<*o!r=XTZ>n3 z^_UWoh;!hkf)h2IXy8Oka^S|@C!z?Djf(@a@o=Jp6Fr<5;KT?gCO9#}i2x@SII+Ts zjRa(~`!A!KX&D@GX&Ibw;(`-5DJ_Gi2^~+8e7ggvCtGff&f^{VL+1Gl;44|CxeIteW{m6sTnMNSlViX+YP1wE z1+0<137iF}$)$+TfDE1m>Ca-`hsl?4f7tOD%(nEC)a;N2#@_v)J%<_KrDI8AfdCg)- zYfVC;^y!w=kbmZz$DXgQc5p>pd?{8pZhotKrco^~cr~nE76%5|7;yP@;qJfY>Ca|AI=>VI0;!Dn)Z34ufHtSR?1PoW$gI5s(+~Cs~a8DC8X_M#h1K@w2$%=ZuYwd^^LV=#*uf2w}_IY}~E?H0`rW z7-jd1RKVx)oH(AO5!l5SUGgc;jeTiOJhQ+5XqceG0R46jqCzBIg4lyULA>ZYo<28K zRKIXjaek!4Fw#2pLG2a^6 z%01UrTbuK18-14?vyh8t_x`#ht=xU-Co&ee>-g2ry!Ol?76;tZXM3yhl- zeT-Ha!Els%IJ~~(L!#{0BHXapr+8jQ8}IMQ#%r&pdnzVZ#ob^Q>V#E^*C*x|*0-F9JU>G%FOPfo{!x0!5WZ0}WuL~=d5xV%TGSp)aMupTe?Fei z2=jZIO_F;iBpup{4Wm-R&$AQk)#>r^pD{;@^J;q%$nM8%}Ai`3sbO~%r)g?6Qi zDN2{8*`^Gi+z~h8z-E;s=Gdv8(EQbQj6}R z0tL#+ir>0Y#8-*7-7;|n+zWbOn^N33fm6p&8HnL4S90XF#l~8*8Z{?jN7nQe<0c$~ zesrGXSyHffYIb!$XmUV@aPjxsvBu_|1O#ANLX~{i~>nNBfUkeN5<1lD}i=YE$hN zX1hz$HP@oKQ}zX*o%E{IId)b1n#*aLS{>I;kMU_s35}f=`Bp#6+_PttT7&VmhBpIT z`0vvxtNN^nF2)Te21iNLPOIy$*lum1?S3%I8Lr#cG5LhE?Cg&x zUr7ehW}Nv^W+p5FJuCVjI$bS_IGmHc%+r*lUwcO`*z2FTLZnX^oq(DMpqxRZk>J}q zM<)_lbh=mesp4<><;#hV$4W9od-^=iiEPOn6p}C3E$F`^95|k+{q)|u3j&{6{0gOX zF#*awwUwCK(3?|7M2p{CT^Lvv^&J11eQYPIU;ZlBJ;xnR!z}M64+IuJK&mqu796mt=!|8hVL4eD}xP-a_@Y**c5J( zcEKV%uH@hoUeJjJ`p|{)h4OAwE&KK88O6f%`>z3|& ztL9=Nj=8@i8CkCIkrG@^RI!l1LM5(mcQ4d4uxS3`{qUa$Lx`d!OOprMj}**3yE-P` z__lDXZjI{^4tbJo21GDsXdS-GRy{jTC2sKAC}(do&vJ-JDqS|eUd92zC2)Q^ZQ`~Y zo3J?Ro&`>>P|g>8dPPekBc#O|1Jjq)D|Tny>;pZ8(A4PS=>ETP)Wb@dJgllr%>q;Rim7TF_6ZPN?5w_ zGh+CaTmLMl^*Sp&J*chl$wkbQ(hU$5o_$d z6>~4@Vu$;@P{(C&gGU_rthMB~4RcJ>!M!K?bZ$9AV@b?%~^37v+! zzo)HaW8Sxn6ph9y7r!?-=hZQHL~D;z=o7n=Y0d2xEA1kr%vGQLv&+D*t1}LRTx%9I zmsKLL5KaP=LvAAM_f^3Z@+~G91k=fP7lI%-OTGqDNPvS_^cLgY@odqT8iP5=g4|-X zNV3vkBw6~d9QYHJhG1!BXjX2W6bIk1HLjizT7ZZkxC@dp1UVpBicdCQ5*uFVVMxBO3TABjqru+3lntN5#&QI>I~3O4#-3t zJ7VJfR+bQctBH7aSq=NuS+leBuH%h;J^FXM2gMy3?q$8XKC}1xVr71IlbBxqsmaDH z+AD8P4-JGZo_uH^U8zVHkWJq(!OrlLl3*YI=0fKT`ySQjb)nP{S8b)<_7-gIdu|%V zh8@Me&jUlF6lBkjvey*L3Ib<(FP-M3q9dlopWI&jUc221jQzRts7`%O?h&JI)MMG@ zAd&^I?4?Wh;$lVEwLkIF24z!g8DGfzu|l}5=(5XN?$wJXUaH}ky7ZJUOQLIGgWIEL zbY9>`y18)W(W8VXA335zZGt(x#P_ofPk%{yAJM>V^mzWuZ0Ih2r#?9B=zT6HZdq_A z>Rc_9Re#~_Q*7wZc7}tUZoKsDQQh0$uyw_yCRKZGs?qG2JDkcH&;3JqFQIXo?{dbC zafTk?@>suHiNY!QoUvGAeM9r>cm0>kD#LSOvhA8+YVMW3jL7vX*8bqFy(4Cw_aYG;?FTnSo1uz5>i?Er2CB- zDc8DwX?C>Q`curIXS=R1Cva8Xe$bJX8(AG>HkU_bIGXQg-&0>@BKILOSTs(>zQ&{#^ua0lNOJdW${$*=kn_)_q4UogLZMKvv`K`m*a8UHc#yFmM?Y2}G?)D7bW@l!p#I#1;u zIET=4sB=f@)7z1Zj51zi(p}&!a&h$GY@JAbS+7as7Zw-GU?%=4rEK9V)nzArBkSe{ z^DjFYRwOjdZ4F?2cn@0!V+3wSjA2Fzq zHIO!Sx^1Li^@wlBf?Jgbt-)te*_^EjPI}|?A87Zu;rY(i8SW$AZxwg)z7Xog7Zc7t zu4)#;p3B3%L~Hrzj+~4o6d=4JxeW>ywSQHZ%ye|<{H{E0jzipbii7vx4xDr?eCB_X z=sH1JtKP?OP%|cSp-t{EUDsffUGTgayaWzh>USd&Duzt%D8CT*>bb*gSY7=>jYG59 zZxR>V<>P8!c`~Sr*gm^>ZTRwKD|_|ZPTUXgaUICG*U6Re%xyH!)Qc$DRy|&Y z#UE9bURQSX-|*zceYz0;<-p6pZ|Qw=+iuq+gVzYzKN2m)`T7cGbi4#)k2P=#Fn1S$ zA0Nv^$4;M95;xSNuifS)e66!~l#?r1#jp)46C`VD-EZAOLt-M*lPKs(c=|;K&RHeN zck~ujP=(LY3ZJ^i4L7wU-0LT;wpbjyF=uvvPUoYGOJeb@;o>j-KHf@e(8@F+WUdvs z;~qM;C1G`$P+Lr#&OEZeD?`q6R^L;a@w7~}f2(8Bst)th`r%zGt%0E-w(6fo7Ac4` zb6@S#atzKVuc%}a9i*DA;!mBcI#hPmV(v4xf9G516Y~rD;`?Lm@1(^2jKuxis_N%y zD(+H9x<}~o9y)uKa6mvhlgq*;UDLXpkbJGy#j$v(Huh)O{r+z~iX!~#H9c89CY^o< zW;vuR)3dC3r7N7UlFF;y}#RlBV1 zgD5TDVzPGE3o(i{A*P^q`m%C8fh^6MM#Lq}cQSNe_R^jFzg?1y35?@1@a%{QtO#Fe z9Y4i6rQjtrw2Ijj@ER%D<$iuD3`W_NRO$zsQjyQUK(G*vT&Oq%RQ&yL3VjR#mH3ep z9rMSJX`@WQ%xDZi>Y?BkIGt;ZTrG^>12+U#u8}_9RT}?dvMzc-+mw&HG;tK|8`g0Go?V-%82O{Fk%P zNd)UaFc2yY0~yc`K0q2NDd9$8=w}#6xAkxP;+yPiB9hx6&=e%ITr=cKr7+v?w}l;R8V~fAR+Nr2R6+ZJO}GPWLRtplduQE);65OW86~S;Z&i`_ugD0rhz~OVyMsqjQ0c$$tpe2$hn_`&Ea>>6zWrQpg)g+s zn=B!dg-k5g7>7<)dISy+5u-smR5vjiMq)P*TJ$X%YLABJ6H!Fr#&uX0zj+9e6MbVg z;DYc*1zA@ZJlUKqo)hwjSvQBQ53Cj$fv(4_4{i;zY674)F`%S15<|JFGzF{h>#7kP zvCJE!7|fMOMmVI&+lk|GXGeEwS2vg6lS=-#!2n}jBzp;!?8L;+F6!M>+JTjJpR60%T~ z;kt?`Hx;^rxp?~cNS`?7`?rrRxSdqG%M2L%-AsR(XM|GX*3Ex-v-cq+NrkD7r20!J z8tVKdbaL?8NyB~&W@Z(Gq2J`=0f=yR-6yHDu#XLp-r04Z-Qha+-AU-!IS}2C_@VZ* z>jB({KzaUT=$$_R{t>a{@qLt^VNeSX8y~!B8*j2G4cVUq?a-~O7Y}OvgokYpEe4~y zNyw5&=7#q!cIYM%z(IWR>$auhVcWN&HgMiQf`V)t*divO4BH-tliDU)hx83KW@s!P zll=D#$Rq{c7xrcXe9)6bkb&&>#s`JJ<*BnbeyE|e3Drqp71DpIC zDA`bwMyX6-Z7gTmMk_DGlM1q;UiWw=6;;42U*TRFY+|vmM&xxMiKO)-18r60Wi zhk@`{lTD(*kI14|lR#F~;KL-?pxG0o^#BBa1Np=4N$ZdfGkA7I;ZF>kmq1YmS^iQo z$cA1V&<`b0eGW8g?1alH1hBw*-S%%j8oQE5~+Ro-3q)3mp}SR(Q!aMmQIC3@7)-H@$oq2>gFXK=;`ry;I*~YUwH%%l{4)5_DyWZrvPXT z-X@`osUZ4Y5PAsHQJ$Cu()UtxLbIvsw;HB2xYhSF0Hu5e1fYXy>oaYQG+$Xln|UDk ziw!+g@C&<%U{%ZO*xWL}0Db<2tsz+H+Bznm4)UN=IwN>c{T&=&bc`5`z$QOUXrS8= z$cBCyg3hIb9B9`sr^A!wL61P<&?f@??C}`_Sx~Cq--0k0%}rE=gbjJ#KaLDE)S$== zn9+`BLxKb9%wAt_->p)U<>9r~1W(Im#=Rg}URmN#5Bx1l-lf6=ZY}n={A+ciT; z0;BLm<-qg*`v!@eez_1u4yc4Gspi1b(`tga#s;70>*sbz4#5%Cr z9rQVi7o}WAC`*t01*>0x4-w=lV0{6GKUn<*U;G8vAn=;aCYTqR$${eo(FSv2nEn_U zhA$G3RW2M*2oj7S1jpYR9#(<*_b zG&Gf3UQ5CI%U