git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8278 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
parent
8892a90de8
commit
6274f1e25f
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@ -18,8 +18,13 @@
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*/
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/*
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* ST32F746xG memory setup.
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* Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
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* ST32F746xG generic setup.
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*
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* RAM0 - Data, Heap.
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* RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
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*
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* Notes:
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* BSS is placed in DTCM RAM in order to simplify DMA buffers management.
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*/
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MEMORY
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{
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@ -47,7 +52,7 @@ REGION_ALIAS("PROCESS_STACK_RAM", ram3);
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REGION_ALIAS("DATA_RAM", ram0);
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/* RAM region to be used for BSS segment.*/
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REGION_ALIAS("BSS_RAM", ram0);
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REGION_ALIAS("BSS_RAM", ram3);
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/* RAM region to be used for the default heap.*/
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REGION_ALIAS("HEAP_RAM", ram0);
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@ -18,8 +18,14 @@
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*/
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/*
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* ST32F746xG memory setup.
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* Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
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* ST32F746xG Ethernet setup.
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*
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* RAM1 - Data, Heap.
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* RAM2 - ETH.
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* RAM3 - Main Stack, Process Stack, BSS, NOCACHE.
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*
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* Notes:
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* BSS is placed in DTCM RAM in order to simplify DMA buffers management.
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*/
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MEMORY
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{
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@ -46,7 +52,7 @@ REGION_ALIAS("PROCESS_STACK_RAM", ram3);
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REGION_ALIAS("DATA_RAM", ram1);
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/* RAM region to be used for BSS segment.*/
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REGION_ALIAS("BSS_RAM", ram1);
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REGION_ALIAS("BSS_RAM", ram3);
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/* RAM region to be used for the default heap.*/
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REGION_ALIAS("HEAP_RAM", ram1);
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@ -0,0 +1,68 @@
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
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This file is part of ChibiOS.
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ChibiOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* ST32F746xG maximum RAM setup.
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*
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* RAM0 - Data, BSS, Heap.
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* RAM3 - Main Stack, Process Stack, NOCACHE, ETH.
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*
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* Notes:
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* BSS is placed in cached RAM, DMA buffers management is delegated to the
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* application code. This setup maximizes the linear RAM available to BSS and
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* Heap.
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*/
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MEMORY
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{
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flash : org = 0x08000000, len = 1M
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flash_itcm : org = 0x00200000, len = 1M
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ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
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ram1 : org = 0x20010000, len = 240k /* SRAM1 */
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ram2 : org = 0x2004C000, len = 16k /* SRAM2 */
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ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */
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ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
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ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
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ram6 : org = 0x00000000, len = 0
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ram7 : org = 0x00000000, len = 0
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}
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/* RAM region to be used for Main stack. This stack accommodates the processing
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of all exceptions and interrupts*/
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REGION_ALIAS("MAIN_STACK_RAM", ram3);
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/* RAM region to be used for the process stack. This is the stack used by
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the main() function.*/
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REGION_ALIAS("PROCESS_STACK_RAM", ram3);
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/* RAM region to be used for data segment.*/
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REGION_ALIAS("DATA_RAM", ram0);
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/* RAM region to be used for BSS segment.*/
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REGION_ALIAS("BSS_RAM", ram0);
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/* RAM region to be used for the default heap.*/
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REGION_ALIAS("HEAP_RAM", ram0);
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/* RAM region to be used for nocache segment.*/
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REGION_ALIAS("NOCACHE_RAM", ram3);
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/* RAM region to be used for eth segment.*/
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REGION_ALIAS("ETH_RAM", ram3);
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INCLUDE ld/rules_STM32F7xx.ld
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@ -52,10 +52,15 @@ static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
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size_t nx = 0, ny = 0;
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static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
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#if 0
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/* DMA buffer invalidation because data cache, only invalidating the
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half buffer just filled.*/
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half buffer just filled.
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Only required if the ADC buffer is placed in a cache-able area.*/
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dmaBufferInvalidate(buffer,
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n * adcp->grpp->num_channels * sizeof (adcsample_t));
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#else
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(void)adcp;
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#endif
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/* Updating counters.*/
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if (samples1 == buffer) {
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@ -88,6 +88,7 @@
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#define STM32_CECSEL STM32_CECSEL_LSE
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#define STM32_CK48MSEL STM32_CK48MSEL_PLL
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#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
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#define STM32_SRAM2_NOCACHE FALSE
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/*
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* ADC driver system settings.
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@ -88,6 +88,7 @@
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#define STM32_CECSEL STM32_CECSEL_LSE
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#define STM32_CK48MSEL STM32_CK48MSEL_PLL
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#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
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#define STM32_SRAM2_NOCACHE FALSE
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/*
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* ADC driver system settings.
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@ -55,14 +55,7 @@ static const SPIConfig ls_spicfg = {
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*/
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#define SPI_BUFFERS_SIZE 128U
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#if defined(__GNUC__)
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__attribute__((aligned (32)))
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#endif
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static uint8_t txbuf[SPI_BUFFERS_SIZE];
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#if defined(__GNUC__)
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__attribute__((aligned (32)))
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#endif
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static uint8_t rxbuf[SPI_BUFFERS_SIZE];
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/*===========================================================================*/
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@ -87,7 +80,6 @@ static THD_FUNCTION(spi_thread_1, p) {
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/* Preparing data buffer and flushing cache.*/
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for (i = 0; i < SPI_BUFFERS_SIZE; i++)
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txbuf[i] = (uint8_t)i;
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dmaBufferFlush(txbuf, SPI_BUFFERS_SIZE);
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/* Slave selection and data exchange.*/
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spiSelect(&SPID2);
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@ -95,9 +87,6 @@ static THD_FUNCTION(spi_thread_1, p) {
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spiUnselect(&SPID2);
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#if defined(SPI_LOOPBACK)
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/* Invalidating cache over the buffer then checking the
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loopback result.*/
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dmaBufferInvalidate(rxbuf, SPI_BUFFERS_SIZE);
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if (memcmp(txbuf, rxbuf, SPI_BUFFERS_SIZE) != 0)
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chSysHalt("loopback failure");
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#endif
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@ -125,7 +114,6 @@ static THD_FUNCTION(spi_thread_2, p) {
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/* Preparing data buffer and flushing cache.*/
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for (i = 0; i < SPI_BUFFERS_SIZE; i++)
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txbuf[i] = (uint8_t)(128U + i);
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dmaBufferFlush(txbuf, SPI_BUFFERS_SIZE);
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/* Slave selection and data exchange.*/
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spiSelect(&SPID2);
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spiUnselect(&SPID2);
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#if defined(SPI_LOOPBACK)
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/* Invalidating cache over the buffer then checking the
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loopback result.*/
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dmaBufferInvalidate(rxbuf, SPI_BUFFERS_SIZE);
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if (memcmp(txbuf, rxbuf, SPI_BUFFERS_SIZE) != 0)
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chSysHalt("loopback failure");
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#endif
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@ -88,6 +88,7 @@
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#define STM32_CECSEL STM32_CECSEL_LSE
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#define STM32_CK48MSEL STM32_CK48MSEL_PLL
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#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
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#define STM32_SRAM2_NOCACHE FALSE
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/*
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* ADC driver system settings.
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@ -88,6 +88,7 @@
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#define STM32_CECSEL STM32_CECSEL_LSE
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#define STM32_CK48MSEL STM32_CK48MSEL_PLL
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#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
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#define STM32_SRAM2_NOCACHE FALSE
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/*
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* ADC driver system settings.
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