git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4233 35acf78f-673a-0410-8e92-d51de3d6d3f4
parent
7a6a1679a4
commit
5a7b2c4fba
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@ -98,17 +98,13 @@ static const SerialConfig default_config =
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static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
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static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
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USART_TypeDef *u = sdp->usart;
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USART_TypeDef *u = sdp->usart;
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/*
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/* Baud rate setting.*/
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* Baud rate setting.
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*/
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if (sdp->usart == USART1)
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if (sdp->usart == USART1)
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u->BRR = STM32_USART1CLK / config->sc_speed;
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u->BRR = STM32_USART1CLK / config->sc_speed;
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else
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else
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u->BRR = STM32_PCLK / config->sc_speed;
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u->BRR = STM32_PCLK / config->sc_speed;
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/*
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/* Note that some bits are enforced.*/
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* Note that some bits are enforced.
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*/
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u->CR1 = config->sc_cr1 | USART_CR1_UE | USART_CR1_PEIE |
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u->CR1 = config->sc_cr1 | USART_CR1_UE | USART_CR1_PEIE |
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USART_CR1_RXNEIE | USART_CR1_TE |
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USART_CR1_RXNEIE | USART_CR1_TE |
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USART_CR1_RE;
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USART_CR1_RE;
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@ -215,9 +211,7 @@ static void serve_interrupt(SerialDriver *sdp) {
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static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
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static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
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USART_TypeDef *u = sdp->usart;
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USART_TypeDef *u = sdp->usart;
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/*
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/* Baud rate setting.*/
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* Baud rate setting.
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*/
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#if STM32_HAS_USART6
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#if STM32_HAS_USART6
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if ((sdp->usart == USART1) || (sdp->usart == USART6))
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if ((sdp->usart == USART1) || (sdp->usart == USART6))
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#else
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#else
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@ -227,9 +221,7 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
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else
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else
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u->BRR = STM32_PCLK1 / config->sc_speed;
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u->BRR = STM32_PCLK1 / config->sc_speed;
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/*
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/* Note that some bits are enforced.*/
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* Note that some bits are enforced.
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*/
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u->CR1 = config->sc_cr1 | USART_CR1_UE | USART_CR1_PEIE |
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u->CR1 = config->sc_cr1 | USART_CR1_UE | USART_CR1_PEIE |
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USART_CR1_RXNEIE | USART_CR1_TE |
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USART_CR1_RXNEIE | USART_CR1_TE |
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USART_CR1_RE;
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USART_CR1_RE;
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@ -223,18 +223,15 @@
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*/
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*/
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/* ADC attributes.*/
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_DEFAULT STM32_DMA_STREAM_ID(1, 0)
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \
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STM32_DMA_STREAM_ID_MSK(1, 1))
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STM32_DMA_STREAM_ID_MSK(1, 1))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC2 FALSE
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#define STM32_ADC2_DMA_DEFAULT 0
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#define STM32_ADC2_DMA_MSK 0x00000000
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#define STM32_ADC2_DMA_MSK 0x00000000
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#define STM32_ADC2_DMA_CHN 0x00000000
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#define STM32_ADC2_DMA_CHN 0x00000000
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_ADC3_DMA_DEFAULT 0
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#define STM32_ADC3_DMA_MSK 0x00000000
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#define STM32_ADC3_DMA_MSK 0x00000000
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#define STM32_ADC3_DMA_CHN 0x00000000
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#define STM32_ADC3_DMA_CHN 0x00000000
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