From 59bb7ed0c624a773630c20cb3cfc85f4d65d5e78 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 19 Nov 2012 11:55:16 +0000
Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4830
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 demos/PPC-SPC560B-GCC/mcuconf.h       |  7 +++++++
 os/hal/platforms/SPC560BCxx/hal_lld.c |  1 +
 os/hal/platforms/SPC560BCxx/hal_lld.h | 13 +++++++++++++
 3 files changed, 21 insertions(+)

diff --git a/demos/PPC-SPC560B-GCC/mcuconf.h b/demos/PPC-SPC560B-GCC/mcuconf.h
index 2de1ffee3..8948bd35b 100644
--- a/demos/PPC-SPC560B-GCC/mcuconf.h
+++ b/demos/PPC-SPC560B-GCC/mcuconf.h
@@ -104,6 +104,13 @@
                                              SPC5_ME_MC_CFLAON_NORMAL |     \
                                              SPC5_ME_MC_DFLAON_NORMAL |     \
                                              SPC5_ME_MC_MVRON)
+#define SPC5_ME_STANDBY0_MC_BITS            (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
+                                             SPC5_ME_MC_IRCON |             \
+                                             SPC5_ME_MC_XOSC0ON |           \
+                                             SPC5_ME_MC_PLL0ON |            \
+                                             SPC5_ME_MC_CFLAON_NORMAL |     \
+                                             SPC5_ME_MC_DFLAON_NORMAL |     \
+                                             SPC5_ME_MC_MVRON)
 #define SPC5_ME_RUN_PC0_BITS                0
 #define SPC5_ME_RUN_PC1_BITS                (SPC5_ME_RUN_PC_TEST |          \
                                              SPC5_ME_RUN_PC_SAFE |          \
diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.c b/os/hal/platforms/SPC560BCxx/hal_lld.c
index 31fc21cf8..4f7ef3db7 100644
--- a/os/hal/platforms/SPC560BCxx/hal_lld.c
+++ b/os/hal/platforms/SPC560BCxx/hal_lld.c
@@ -141,6 +141,7 @@ void spc_clock_init(void) {
   ME.RUN[3].R       = SPC5_ME_RUN3_MC_BITS;     /* RUN0 run mode.           */
   ME.HALT0.R        = SPC5_ME_HALT0_MC_BITS;    /* HALT0 run mode.          */
   ME.STOP0.R        = SPC5_ME_STOP0_MC_BITS;    /* STOP0 run mode.          */
+  ME.STANDBY0.R     = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode.       */
 
   /* Peripherals run and low power modes initialization.*/
   ME.RUNPC[0].R     = SPC5_ME_RUN_PC0_BITS;
diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.h b/os/hal/platforms/SPC560BCxx/hal_lld.h
index 78e4c3dfc..2fb5a3247 100644
--- a/os/hal/platforms/SPC560BCxx/hal_lld.h
+++ b/os/hal/platforms/SPC560BCxx/hal_lld.h
@@ -407,6 +407,19 @@
                                              SPC5_ME_MC_MVRON)
 #endif
 
+/**
+ * @brief   STANDBY0 mode settings.
+ */
+#if !defined(SPC5_ME_STANDBY0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_STANDBY0_MC_BITS            (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
+                                             SPC5_ME_MC_IRCON |             \
+                                             SPC5_ME_MC_XOSC0ON |           \
+                                             SPC5_ME_MC_PLL0ON |            \
+                                             SPC5_ME_MC_CFLAON_NORMAL |     \
+                                             SPC5_ME_MC_DFLAON_NORMAL |     \
+                                             SPC5_ME_MC_MVRON)
+#endif
+
 /**
  * @brief   Peripheral mode 0 (run mode).
  * @note    Do not change this setting, it is expected to be the "never run"