zcy
/
tinySA
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6213 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-08-23 12:14:39 +00:00
parent 4377d247ae
commit 590c03982f
29 changed files with 540 additions and 370 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
demos/ARMCM4-STM32F407-DISCOVERY-MEMS/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

10
demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

18
os/hal/platforms/STM32/SPIv1/spi_lld.c
View File

@ -216,49 +216,49 @@ void spi_lld_start(SPIDriver *spip) {
if (spip->state == SPI_STOP) { if (spip->state == SPI_STOP) {
#if STM32_SPI_USE_SPI1 #if STM32_SPI_USE_SPI1
if (&SPID1 == spip) { if (&SPID1 == spip) {
bool_t b; bool b;
b = dmaStreamAllocate(spip->dmarx, b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI1_IRQ_PRIORITY, STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip); (void *)spip);
chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx, b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI1_IRQ_PRIORITY, STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip); (void *)spip);
chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
rccEnableSPI1(FALSE); rccEnableSPI1(FALSE);
} }
#endif #endif
#if STM32_SPI_USE_SPI2 #if STM32_SPI_USE_SPI2
if (&SPID2 == spip) { if (&SPID2 == spip) {
bool_t b; bool b;
b = dmaStreamAllocate(spip->dmarx, b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI2_IRQ_PRIORITY, STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip); (void *)spip);
chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx, b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI2_IRQ_PRIORITY, STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip); (void *)spip);
chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
rccEnableSPI2(FALSE); rccEnableSPI2(FALSE);
} }
#endif #endif
#if STM32_SPI_USE_SPI3 #if STM32_SPI_USE_SPI3
if (&SPID3 == spip) { if (&SPID3 == spip) {
bool_t b; bool b;
b = dmaStreamAllocate(spip->dmarx, b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI3_IRQ_PRIORITY, STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip); (void *)spip);
chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx, b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI3_IRQ_PRIORITY, STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip); (void *)spip);
chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
rccEnableSPI3(FALSE); rccEnableSPI3(FALSE);
} }
#endif #endif

8
os/hal/platforms/STM32/SPIv1/spi_lld.h
View File

@ -328,17 +328,13 @@ struct SPIDriver{
/** /**
* @brief Waiting thread. * @brief Waiting thread.
*/ */
Thread *thread; thread_reference_t thread;
#endif /* SPI_USE_WAIT */ #endif /* SPI_USE_WAIT */
#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) #if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
#if CH_USE_MUTEXES || defined(__DOXYGEN__)
/** /**
* @brief Mutex protecting the bus. * @brief Mutex protecting the bus.
*/ */
Mutex mutex; mutex_t mutex;
#elif CH_USE_SEMAPHORES
Semaphore semaphore;
#endif
#endif /* SPI_USE_MUTUAL_EXCLUSION */ #endif /* SPI_USE_MUTUAL_EXCLUSION */
#if defined(SPI_DRIVER_EXT_FIELDS) #if defined(SPI_DRIVER_EXT_FIELDS)
SPI_DRIVER_EXT_FIELDS SPI_DRIVER_EXT_FIELDS

100
os/hal/platforms/STM32/USARTv1/uart_lld.c
View File

@ -59,16 +59,16 @@
STM32_DMA_GETCHANNEL(STM32_UART_UART4_RX_DMA_STREAM, \ STM32_DMA_GETCHANNEL(STM32_UART_UART4_RX_DMA_STREAM, \
STM32_UART4_RX_DMA_CHN) STM32_UART4_RX_DMA_CHN)
#define UART4_TX_DMA_CHANNEL \ #define UART4_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_UART4_TX_DMA_STREAM, \ STM32_DMA_GETCHANNEL(STM32_UART_UART4_TX_DMA_STREAM, \
STM32_UART4_TX_DMA_CHN) STM32_UART4_TX_DMA_CHN)
#define UART5_RX_DMA_CHANNEL \ #define UART5_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_UART5_RX_DMA_STREAM, \ STM32_DMA_GETCHANNEL(STM32_UART_UART5_RX_DMA_STREAM, \
STM32_UART5_RX_DMA_CHN) STM32_UART5_RX_DMA_CHN)
#define UART5_TX_DMA_CHANNEL \ #define UART5_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_UART5_TX_DMA_STREAM, \ STM32_DMA_GETCHANNEL(STM32_UART_UART5_TX_DMA_STREAM, \
STM32_UART5_TX_DMA_CHN) STM32_UART5_TX_DMA_CHN)
#define USART6_RX_DMA_CHANNEL \ #define USART6_RX_DMA_CHANNEL \
@ -79,14 +79,6 @@
STM32_DMA_GETCHANNEL(STM32_UART_USART6_TX_DMA_STREAM, \ STM32_DMA_GETCHANNEL(STM32_UART_USART6_TX_DMA_STREAM, \
STM32_USART6_TX_DMA_CHN) STM32_USART6_TX_DMA_CHN)
#if (STM32_UART_USE_UART4 || STM32_UART_USE_UART5)
#define STM32_UART45_CR2_CHECK_MASK (USART_CR2_STOP_0 | USART_CR2_CLKEN | \
USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL)
#define STM32_UART45_CR3_CHECK_MASK (USART_CR3_CTSIE | USART_CR3_CTSE | \
USART_CR3_RTSE | USART_CR3_SCEN | USART_CR3_NACK)
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Driver exported variables. */ /* Driver exported variables. */
/*===========================================================================*/ /*===========================================================================*/
@ -507,28 +499,6 @@ void uart_lld_init(void) {
#endif #endif
} }
/**
* @brief Check CR2 and CR3 values for compatibility with UART4, UART5.
*
* @param[in] uartp pointer to the @p UARTDriver object
*
* @notapi
*/
#if (STM32_UART_USE_UART4 || STM32_UART_USE_UART5)
static void uart_check_config(const UARTDriver *uartp) {
uint16_t cr;
cr = uartp->config->cr2;
chDbgCheck((cr & STM32_UART45_CR2_CHECK_MASK) == 0,
"Some flags from CR2 unavailable for this UART");
cr = uartp->config->cr3;
chDbgCheck((cr & STM32_UART45_CR3_CHECK_MASK) == 0,
"Some flags from CR3 unavailable for this UART");
}
#endif /* (STM32_UART_USE_UART4 || STM32_UART_USE_UART5) */
/** /**
* @brief Configures and activates the UART peripheral. * @brief Configures and activates the UART peripheral.
* *
@ -538,31 +508,22 @@ static void uart_check_config(const UARTDriver *uartp) {
*/ */
void uart_lld_start(UARTDriver *uartp) { void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_UART4
if (uartp == &UARTD4)
uart_check_config(uartp);
#elif STM32_UART_USE_UART5
else if (uartp == &UARTD5)
uart_check_config(uartp);
#endif
if (uartp->state == UART_STOP) { if (uartp->state == UART_STOP) {
#if STM32_UART_USE_USART1 #if STM32_UART_USE_USART1
if (&UARTD1 == uartp) { if (&UARTD1 == uartp) {
bool_t b; bool b;
b = dmaStreamAllocate(uartp->dmarx, b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART1_IRQ_PRIORITY, STM32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx, b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART1_IRQ_PRIORITY, STM32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
rccEnableUSART1(FALSE); rccEnableUSART1(FALSE);
nvicEnableVector(STM32_USART1_NUMBER, nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY);
CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
} }
@ -570,20 +531,19 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_USART2 #if STM32_UART_USE_USART2
if (&UARTD2 == uartp) { if (&UARTD2 == uartp) {
bool_t b; bool b;
b = dmaStreamAllocate(uartp->dmarx, b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART2_IRQ_PRIORITY, STM32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx, b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART2_IRQ_PRIORITY, STM32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
rccEnableUSART2(FALSE); rccEnableUSART2(FALSE);
nvicEnableVector(STM32_USART2_NUMBER, nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY);
CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
} }
@ -591,20 +551,19 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_USART3 #if STM32_UART_USE_USART3
if (&UARTD3 == uartp) { if (&UARTD3 == uartp) {
bool_t b; bool b;
b = dmaStreamAllocate(uartp->dmarx, b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART3_IRQ_PRIORITY, STM32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx, b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART3_IRQ_PRIORITY, STM32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
rccEnableUSART3(FALSE); rccEnableUSART3(FALSE);
nvicEnableVector(STM32_USART3_NUMBER, nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY);
CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
} }
@ -612,20 +571,19 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_UART4 #if STM32_UART_USE_UART4
if (&UARTD4 == uartp) { if (&UARTD4 == uartp) {
bool_t b; bool b;
b = dmaStreamAllocate(uartp->dmarx, b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_UART4_IRQ_PRIORITY, STM32_UART_UART4_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #7", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx, b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_UART4_IRQ_PRIORITY, STM32_UART_UART4_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #8", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
rccEnableUART4(FALSE); rccEnableUART4(FALSE);
nvicEnableVector(STM32_UART4_NUMBER, nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY);
CORTEX_PRIORITY_MASK(STM32_UART_UART4_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) | uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY);
} }
@ -633,20 +591,19 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_UART5 #if STM32_UART_USE_UART5
if (&UARTD5 == uartp) { if (&UARTD5 == uartp) {
bool_t b; bool b;
b = dmaStreamAllocate(uartp->dmarx, b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_UART5_IRQ_PRIORITY, STM32_UART_UART5_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #9", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx, b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_UART5_IRQ_PRIORITY, STM32_UART_UART5_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #10", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
rccEnableUART5(FALSE); rccEnableUART5(FALSE);
nvicEnableVector(STM32_UART5_NUMBER, nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY);
CORTEX_PRIORITY_MASK(STM32_UART_UART5_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) | uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY);
} }
@ -654,20 +611,19 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_USART6 #if STM32_UART_USE_USART6
if (&UARTD6 == uartp) { if (&UARTD6 == uartp) {
bool_t b; bool b;
b = dmaStreamAllocate(uartp->dmarx, b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART6_IRQ_PRIORITY, STM32_UART_USART6_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #11", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx, b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART6_IRQ_PRIORITY, STM32_UART_USART6_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #12", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
rccEnableUSART6(FALSE); rccEnableUSART6(FALSE);
nvicEnableVector(STM32_USART6_NUMBER, nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY);
CORTEX_PRIORITY_MASK(STM32_UART_USART6_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY);
} }

8
os/hal/platforms/STM32/USARTv1/uart_lld.h
View File

@ -259,7 +259,7 @@
* @note This option is only available on platforms with enhanced DMA. * @note This option is only available on platforms with enhanced DMA.
*/ */
#if !defined(STM32_UART_UART4_RX_DMA_STREAM) || defined(__DOXYGEN__) #if !defined(STM32_UART_UART4_RX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#endif #endif
/** /**
@ -267,7 +267,7 @@
* @note This option is only available on platforms with enhanced DMA. * @note This option is only available on platforms with enhanced DMA.
*/ */
#if !defined(STM32_UART_UART4_TX_DMA_STREAM) || defined(__DOXYGEN__) #if !defined(STM32_UART_UART4_TX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#endif #endif
/** /**
@ -275,7 +275,7 @@
* @note This option is only available on platforms with enhanced DMA. * @note This option is only available on platforms with enhanced DMA.
*/ */
#if !defined(STM32_UART_UART5_RX_DMA_STREAM) || defined(__DOXYGEN__) #if !defined(STM32_UART_UART5_RX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#endif #endif
/** /**
@ -283,7 +283,7 @@
* @note This option is only available on platforms with enhanced DMA. * @note This option is only available on platforms with enhanced DMA.
*/ */
#if !defined(STM32_UART_UART5_TX_DMA_STREAM) || defined(__DOXYGEN__) #if !defined(STM32_UART_UART5_TX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#endif #endif
/** /**

10
testhal/STM32F4xx/ADC/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

10
testhal/STM32F4xx/CAN/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

10
testhal/STM32F4xx/DMA_STORM/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

10
testhal/STM32F4xx/EXT/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

10
testhal/STM32F4xx/GPT/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

10
testhal/STM32F4xx/I2C/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

10
testhal/STM32F4xx/IRQ_STORM/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

10
testhal/STM32F4xx/IRQ_STORM_FPU/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

10
testhal/STM32F4xx/PWM-ICU/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

10
testhal/STM32F4xx/RTC/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

10
testhal/STM32F4xx/SDC/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

2
testhal/STM32F4xx/SPI/.project
View File

@ -27,7 +27,7 @@
<link> <link>
<name>board</name> <name>board</name>
<type>2</type> <type>2</type>
<locationURI>CHIBIOS/boards/ST_STM32F4_DISCOVERY</locationURI> <locationURI>CHIBIOS/os/hal/boards/ST_STM32F4_DISCOVERY</locationURI>
</link> </link>
<link> <link>
<name>os</name> <name>os</name>

19
testhal/STM32F4xx/SPI/Makefile
View File

@ -65,12 +65,13 @@ PROJECT = ch
# Imported source files and paths # Imported source files and paths
CHIBIOS = ../../.. CHIBIOS = ../../..
include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk include $(CHIBIOS)/os/hal/osal/chibios/osal.mk
include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk
include $(CHIBIOS)/test/test.mk include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/rt/ports/ARMCMx/devices/STM32F4xx/port.mk
#include $(CHIBIOS)/test/test.mk
# Define linker script file here # Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld LDSCRIPT= $(PORTLD)/STM32F407xG.ld
@ -82,9 +83,9 @@ CSRC = $(PORTSRC) \
$(KERNSRC) \ $(KERNSRC) \
$(TESTSRC) \ $(TESTSRC) \
$(HALSRC) \ $(HALSRC) \
$(OSALSRC) \
$(PLATFORMSRC) \ $(PLATFORMSRC) \
$(BOARDSRC) \ $(BOARDSRC) \
$(CHIBIOS)/os/various/chprintf.c \
main.c main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global # C++ sources that can be compiled in ARM or THUMB mode depending on the global
@ -115,7 +116,7 @@ TCPPSRC =
ASMSRC = $(PORTASM) ASMSRC = $(PORTASM)
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \ $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \
$(CHIBIOS)/os/various $(CHIBIOS)/os/various
# #
@ -208,8 +209,10 @@ ULIBS =
ifeq ($(USE_FPU),yes) ifeq ($(USE_FPU),yes)
USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
DDEFS += -DCORTEX_USE_FPU=TRUE DDEFS += -DCORTEX_USE_FPU=TRUE
DADEFS += -DCORTEX_USE_FPU=TRUE
else else
DDEFS += -DCORTEX_USE_FPU=FALSE DDEFS += -DCORTEX_USE_FPU=FALSE
DADEFS += -DCORTEX_USE_FPU=FALSE
endif endif
ifeq ($(USE_FWLIB),yes) ifeq ($(USE_FWLIB),yes)
@ -219,4 +222,4 @@ ifeq ($(USE_FWLIB),yes)
USE_OPT += -DUSE_STDPERIPH_DRIVER USE_OPT += -DUSE_STDPERIPH_DRIVER
endif endif
include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/rules.mk

273
testhal/STM32F4xx/SPI/chconf.h
View File

@ -40,8 +40,29 @@
* @details Frequency of the system timer that drives the system ticks. This * @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit. * setting also defines the system tick time unit.
*/ */
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #if !defined(CH_CFG_ST_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000 #define CH_CFG_ST_FREQUENCY 10000
#endif
/**
* @brief Realtime Counter frequency.
* @details Frequency of the system counter used for realtime delays and
* measurements.
*/
#if !defined(CH_CFG_RTC_FREQUENCY) || defined(__DOXYGEN__)
#define CH_CFG_RTC_FREQUENCY 168000000
#endif
/**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#if !defined(CH_CFG_TIMEDELTA) || defined(__DOXYGEN__)
#define CH_CFG_TIMEDELTA 2
#endif #endif
/** /**
@ -51,12 +72,13 @@
* disables the preemption for threads with equal priority and the * disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority * round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive. * threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact * @note Disabling the round robin preemption makes the kernel more compact
* and generally faster. * and generally faster.
* @note The round robin preemption is not supported in tickless mode and
* must be set to zero in that case.
*/ */
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #if !defined(CH_CFG_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20 #define CH_CFG_TIME_QUANTUM 0
#endif #endif
/** /**
@ -68,27 +90,20 @@
* *
* @note In order to let the OS manage the whole RAM the linker script must * @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols. * provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE. * @note Requires @p CH_CFG_USE_MEMCORE.
*/ */
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #if !defined(CH_CFG_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0 #define CH_CFG_MEMCORE_SIZE 0
#endif #endif
/** /**
* @brief Idle thread automatic spawn suppression. * @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit() * @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has * does not spawn the idle thread. The application @p main()
* then the responsibility to do one of the following: * function becomes the idle thread and must implement an
* - Spawn a custom idle thread at priority @p IDLEPRIO. * infinite loop. */
* - Change the main() thread priority to @p IDLEPRIO then enter #if !defined(CH_CFG_NO_IDLE_THREAD) || defined(__DOXYGEN__)
* an endless loop. In this scenario the @p main() thread acts as #define CH_CFG_NO_IDLE_THREAD FALSE
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif #endif
/** @} */ /** @} */
@ -108,8 +123,8 @@
* @note This is not related to the compiler optimization options. * @note This is not related to the compiler optimization options.
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #if !defined(CH_CFG_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE #define CH_CFG_OPTIMIZE_SPEED TRUE
#endif #endif
/** @} */ /** @} */
@ -121,14 +136,25 @@
*/ */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief Time Measurement APIs.
* @details If enabled then the time measurement APIs are included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_TM) || defined(__DOXYGEN__)
#define CH_CFG_USE_TM TRUE
#endif
/** /**
* @brief Threads registry APIs. * @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel. * @details If enabled then the registry APIs are included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE #define CH_CFG_USE_REGISTRY TRUE
#endif #endif
/** /**
@ -138,8 +164,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE #define CH_CFG_USE_WAITEXIT TRUE
#endif #endif
/** /**
@ -148,8 +174,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE #define CH_CFG_USE_SEMAPHORES TRUE
#endif #endif
/** /**
@ -157,23 +183,12 @@
* @details If enabled then the threads are enqueued on semaphores by * @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order. * priority rather than in FIFO order.
* *
* @note The default is @p FALSE. Enable this if you have special requirements. * @note The default is @p FALSE. Enable this if you have special
* @note Requires @p CH_USE_SEMAPHORES. * requirements.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/ */
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE #define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif #endif
/** /**
@ -182,8 +197,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE #define CH_CFG_USE_MUTEXES TRUE
#endif #endif
/** /**
@ -192,10 +207,10 @@
* in the kernel. * in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES. * @note Requires @p CH_CFG_USE_MUTEXES.
*/ */
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE #define CH_CFG_USE_CONDVARS TRUE
#endif #endif
/** /**
@ -204,10 +219,10 @@
* specification are included in the kernel. * specification are included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS. * @note Requires @p CH_CFG_USE_CONDVARS.
*/ */
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE #define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
#endif #endif
/** /**
@ -216,8 +231,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE #define CH_CFG_USE_EVENTS TRUE
#endif #endif
/** /**
@ -226,10 +241,10 @@
* are included in the kernel. * are included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS. * @note Requires @p CH_CFG_USE_EVENTS.
*/ */
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE #define CH_CFG_USE_EVENTS_TIMEOUT TRUE
#endif #endif
/** /**
@ -239,8 +254,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE #define CH_CFG_USE_MESSAGES TRUE
#endif #endif
/** /**
@ -248,11 +263,12 @@
* @details If enabled then messages are served by priority rather than in * @details If enabled then messages are served by priority rather than in
* FIFO order. * FIFO order.
* *
* @note The default is @p FALSE. Enable this if you have special requirements. * @note The default is @p FALSE. Enable this if you have special
* @note Requires @p CH_USE_MESSAGES. * requirements.
* @note Requires @p CH_CFG_USE_MESSAGES.
*/ */
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE #define CH_CFG_USE_MESSAGES_PRIORITY FALSE
#endif #endif
/** /**
@ -261,10 +277,10 @@
* included in the kernel. * included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES. * @note Requires @p CH_CFG_USE_SEMAPHORES.
*/ */
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE #define CH_CFG_USE_MAILBOXES TRUE
#endif #endif
/** /**
@ -273,8 +289,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE #define CH_CFG_USE_QUEUES TRUE
#endif #endif
/** /**
@ -284,8 +300,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE #define CH_CFG_USE_MEMCORE TRUE
#endif #endif
/** /**
@ -294,26 +310,12 @@
* in the kernel. * in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
* @p CH_USE_SEMAPHORES. * @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended. * @note Mutexes are recommended.
*/ */
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE #define CH_CFG_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif #endif
/** /**
@ -323,8 +325,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE #define CH_CFG_USE_MEMPOOLS TRUE
#endif #endif
/** /**
@ -333,11 +335,11 @@
* in the kernel. * in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT. * @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/ */
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE #define CH_CFG_USE_DYNAMIC TRUE
#endif #endif
/** @} */ /** @} */
@ -349,6 +351,15 @@
*/ */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief Debug option, kernel statistics.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_STATISTICS) || defined(__DOXYGEN__)
#define CH_DBG_STATISTICS TRUE
#endif
/** /**
* @brief Debug option, system state check. * @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked * @details If enabled the correct call protocol for system APIs is checked
@ -357,7 +368,7 @@
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) #if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_SYSTEM_STATE_CHECK TRUE #define CH_DBG_SYSTEM_STATE_CHECK TRUE
#endif #endif
/** /**
@ -368,7 +379,7 @@
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_CHECKS TRUE #define CH_DBG_ENABLE_CHECKS TRUE
#endif #endif
/** /**
@ -380,7 +391,7 @@
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_ASSERTS TRUE #define CH_DBG_ENABLE_ASSERTS TRUE
#endif #endif
/** /**
@ -391,7 +402,7 @@
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_TRACE TRUE #define CH_DBG_ENABLE_TRACE TRUE
#endif #endif
/** /**
@ -405,7 +416,7 @@
* @p panic_msg variable set to @p NULL. * @p panic_msg variable set to @p NULL.
*/ */
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_STACK_CHECK TRUE #define CH_DBG_ENABLE_STACK_CHECK TRUE
#endif #endif
/** /**
@ -417,20 +428,20 @@
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
#define CH_DBG_FILL_THREADS TRUE #define CH_DBG_FILL_THREADS TRUE
#endif #endif
/** /**
* @brief Debug option, threads profiling. * @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that * @details If enabled then a field is added to the @p thread_t structure that
* counts the system ticks occurred while executing the thread. * counts the system ticks occurred while executing the thread.
* *
* @note The default is @p TRUE. * @note The default is @p FALSE.
* @note This debug option is defaulted to TRUE because it is required by * @note This debug option is not currently compatible with the
* some test cases into the test suite. * tickless mode.
*/ */
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING TRUE #define CH_DBG_THREADS_PROFILING FALSE
#endif #endif
/** @} */ /** @} */
@ -444,10 +455,10 @@
/** /**
* @brief Threads descriptor structure extension. * @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure. * @details User fields added to the end of the @p thread_t structure.
*/ */
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #if !defined(CH_CFG_THREAD_EXTRA_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \ #define CH_CFG_THREAD_EXTRA_FIELDS \
/* Add threads custom fields here.*/ /* Add threads custom fields here.*/
#endif #endif
@ -458,8 +469,8 @@
* @note It is invoked from within @p chThdInit() and implicitly from all * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs. * the threads creation APIs.
*/ */
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_THREAD_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \ #define CH_CFG_THREAD_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \ /* Add threads initialization code here.*/ \
} }
#endif #endif
@ -472,8 +483,8 @@
* @note It is also invoked when the threads simply return in order to * @note It is also invoked when the threads simply return in order to
* terminate. * terminate.
*/ */
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_THREAD_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \ #define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \ /* Add threads finalization code here.*/ \
} }
#endif #endif
@ -482,18 +493,40 @@
* @brief Context switch hook. * @brief Context switch hook.
* @details This hook is invoked just before switching between threads. * @details This hook is invoked just before switching between threads.
*/ */
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ #define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \ /* System halt code here.*/ \
} }
#endif #endif
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#if !defined(CH_CFG_IDLE_ENTER_HOOK) || defined(__DOXYGEN__)
#define CH_CFG_IDLE_ENTER_HOOK() { \
}
#endif
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#if !defined(CH_CFG_IDLE_LEAVE_HOOK) || defined(__DOXYGEN__)
#define CH_CFG_IDLE_LEAVE_HOOK() { \
}
#endif
/** /**
* @brief Idle Loop hook. * @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop. * @details This hook is continuously invoked by the idle thread loop.
*/ */
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \ #define CH_CFG_IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \ /* Idle loop code here.*/ \
} }
#endif #endif
@ -503,8 +536,8 @@
* @details This hook is invoked in the system tick handler immediately * @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue. * after processing the virtual timers queue.
*/ */
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_SYSTEM_TICK_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \ #define CH_CFG_SYSTEM_TICK_HOOK() { \
/* System tick event code here.*/ \ /* System tick event code here.*/ \
} }
#endif #endif
@ -514,8 +547,8 @@
* @details This hook is invoked in case to a system halting error before * @details This hook is invoked in case to a system halting error before
* the system is halted. * the system is halted.
*/ */
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \ #define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \ /* System halt code here.*/ \
} }
#endif #endif

7
testhal/STM32F4xx/SPI/halconf.h
View File

@ -30,13 +30,6 @@
#include "mcuconf.h" #include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM TRUE
#endif
/** /**
* @brief Enables the PAL subsystem. * @brief Enables the PAL subsystem.
*/ */

10
testhal/STM32F4xx/SPI/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

2
testhal/STM32F4xx/UART/.project
View File

@ -27,7 +27,7 @@
<link> <link>
<name>board</name> <name>board</name>
<type>2</type> <type>2</type>
<locationURI>CHIBIOS/boards/ST_STM32F4_DISCOVERY</locationURI> <locationURI>CHIBIOS/os/hal/boards/ST_STM32F4_DISCOVERY</locationURI>
</link> </link>
<link> <link>
<name>os</name> <name>os</name>

19
testhal/STM32F4xx/UART/Makefile
View File

@ -65,12 +65,13 @@ PROJECT = ch
# Imported source files and paths # Imported source files and paths
CHIBIOS = ../../.. CHIBIOS = ../../..
include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk include $(CHIBIOS)/os/hal/osal/chibios/osal.mk
include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk
include $(CHIBIOS)/test/test.mk include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/rt/ports/ARMCMx/devices/STM32F4xx/port.mk
#include $(CHIBIOS)/test/test.mk
# Define linker script file here # Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld LDSCRIPT= $(PORTLD)/STM32F407xG.ld
@ -82,9 +83,9 @@ CSRC = $(PORTSRC) \
$(KERNSRC) \ $(KERNSRC) \
$(TESTSRC) \ $(TESTSRC) \
$(HALSRC) \ $(HALSRC) \
$(OSALSRC) \
$(PLATFORMSRC) \ $(PLATFORMSRC) \
$(BOARDSRC) \ $(BOARDSRC) \
$(CHIBIOS)/os/various/chprintf.c \
main.c main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global # C++ sources that can be compiled in ARM or THUMB mode depending on the global
@ -115,7 +116,7 @@ TCPPSRC =
ASMSRC = $(PORTASM) ASMSRC = $(PORTASM)
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \ $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \
$(CHIBIOS)/os/various $(CHIBIOS)/os/various
# #
@ -208,8 +209,10 @@ ULIBS =
ifeq ($(USE_FPU),yes) ifeq ($(USE_FPU),yes)
USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
DDEFS += -DCORTEX_USE_FPU=TRUE DDEFS += -DCORTEX_USE_FPU=TRUE
DADEFS += -DCORTEX_USE_FPU=TRUE
else else
DDEFS += -DCORTEX_USE_FPU=FALSE DDEFS += -DCORTEX_USE_FPU=FALSE
DADEFS += -DCORTEX_USE_FPU=FALSE
endif endif
ifeq ($(USE_FWLIB),yes) ifeq ($(USE_FWLIB),yes)
@ -219,4 +222,4 @@ ifeq ($(USE_FWLIB),yes)
USE_OPT += -DUSE_STDPERIPH_DRIVER USE_OPT += -DUSE_STDPERIPH_DRIVER
endif endif
include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/rules.mk

273
testhal/STM32F4xx/UART/chconf.h
View File

@ -40,8 +40,29 @@
* @details Frequency of the system timer that drives the system ticks. This * @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit. * setting also defines the system tick time unit.
*/ */
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #if !defined(CH_CFG_ST_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000 #define CH_CFG_ST_FREQUENCY 10000
#endif
/**
* @brief Realtime Counter frequency.
* @details Frequency of the system counter used for realtime delays and
* measurements.
*/
#if !defined(CH_CFG_RTC_FREQUENCY) || defined(__DOXYGEN__)
#define CH_CFG_RTC_FREQUENCY 168000000
#endif
/**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#if !defined(CH_CFG_TIMEDELTA) || defined(__DOXYGEN__)
#define CH_CFG_TIMEDELTA 2
#endif #endif
/** /**
@ -51,12 +72,13 @@
* disables the preemption for threads with equal priority and the * disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority * round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive. * threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact * @note Disabling the round robin preemption makes the kernel more compact
* and generally faster. * and generally faster.
* @note The round robin preemption is not supported in tickless mode and
* must be set to zero in that case.
*/ */
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #if !defined(CH_CFG_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20 #define CH_CFG_TIME_QUANTUM 0
#endif #endif
/** /**
@ -68,27 +90,20 @@
* *
* @note In order to let the OS manage the whole RAM the linker script must * @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols. * provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE. * @note Requires @p CH_CFG_USE_MEMCORE.
*/ */
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #if !defined(CH_CFG_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0 #define CH_CFG_MEMCORE_SIZE 0
#endif #endif
/** /**
* @brief Idle thread automatic spawn suppression. * @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit() * @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has * does not spawn the idle thread. The application @p main()
* then the responsibility to do one of the following: * function becomes the idle thread and must implement an
* - Spawn a custom idle thread at priority @p IDLEPRIO. * infinite loop. */
* - Change the main() thread priority to @p IDLEPRIO then enter #if !defined(CH_CFG_NO_IDLE_THREAD) || defined(__DOXYGEN__)
* an endless loop. In this scenario the @p main() thread acts as #define CH_CFG_NO_IDLE_THREAD FALSE
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif #endif
/** @} */ /** @} */
@ -108,8 +123,8 @@
* @note This is not related to the compiler optimization options. * @note This is not related to the compiler optimization options.
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #if !defined(CH_CFG_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE #define CH_CFG_OPTIMIZE_SPEED TRUE
#endif #endif
/** @} */ /** @} */
@ -121,14 +136,25 @@
*/ */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief Time Measurement APIs.
* @details If enabled then the time measurement APIs are included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_TM) || defined(__DOXYGEN__)
#define CH_CFG_USE_TM TRUE
#endif
/** /**
* @brief Threads registry APIs. * @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel. * @details If enabled then the registry APIs are included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE #define CH_CFG_USE_REGISTRY TRUE
#endif #endif
/** /**
@ -138,8 +164,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE #define CH_CFG_USE_WAITEXIT TRUE
#endif #endif
/** /**
@ -148,8 +174,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE #define CH_CFG_USE_SEMAPHORES TRUE
#endif #endif
/** /**
@ -157,23 +183,12 @@
* @details If enabled then the threads are enqueued on semaphores by * @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order. * priority rather than in FIFO order.
* *
* @note The default is @p FALSE. Enable this if you have special requirements. * @note The default is @p FALSE. Enable this if you have special
* @note Requires @p CH_USE_SEMAPHORES. * requirements.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/ */
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE #define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif #endif
/** /**
@ -182,8 +197,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE #define CH_CFG_USE_MUTEXES TRUE
#endif #endif
/** /**
@ -192,10 +207,10 @@
* in the kernel. * in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES. * @note Requires @p CH_CFG_USE_MUTEXES.
*/ */
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE #define CH_CFG_USE_CONDVARS TRUE
#endif #endif
/** /**
@ -204,10 +219,10 @@
* specification are included in the kernel. * specification are included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS. * @note Requires @p CH_CFG_USE_CONDVARS.
*/ */
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE #define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
#endif #endif
/** /**
@ -216,8 +231,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE #define CH_CFG_USE_EVENTS TRUE
#endif #endif
/** /**
@ -226,10 +241,10 @@
* are included in the kernel. * are included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS. * @note Requires @p CH_CFG_USE_EVENTS.
*/ */
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE #define CH_CFG_USE_EVENTS_TIMEOUT TRUE
#endif #endif
/** /**
@ -239,8 +254,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE #define CH_CFG_USE_MESSAGES TRUE
#endif #endif
/** /**
@ -248,11 +263,12 @@
* @details If enabled then messages are served by priority rather than in * @details If enabled then messages are served by priority rather than in
* FIFO order. * FIFO order.
* *
* @note The default is @p FALSE. Enable this if you have special requirements. * @note The default is @p FALSE. Enable this if you have special
* @note Requires @p CH_USE_MESSAGES. * requirements.
* @note Requires @p CH_CFG_USE_MESSAGES.
*/ */
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE #define CH_CFG_USE_MESSAGES_PRIORITY FALSE
#endif #endif
/** /**
@ -261,10 +277,10 @@
* included in the kernel. * included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES. * @note Requires @p CH_CFG_USE_SEMAPHORES.
*/ */
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE #define CH_CFG_USE_MAILBOXES TRUE
#endif #endif
/** /**
@ -273,8 +289,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE #define CH_CFG_USE_QUEUES TRUE
#endif #endif
/** /**
@ -284,8 +300,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE #define CH_CFG_USE_MEMCORE TRUE
#endif #endif
/** /**
@ -294,26 +310,12 @@
* in the kernel. * in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
* @p CH_USE_SEMAPHORES. * @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended. * @note Mutexes are recommended.
*/ */
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE #define CH_CFG_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif #endif
/** /**
@ -323,8 +325,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE #define CH_CFG_USE_MEMPOOLS TRUE
#endif #endif
/** /**
@ -333,11 +335,11 @@
* in the kernel. * in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT. * @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/ */
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE #define CH_CFG_USE_DYNAMIC TRUE
#endif #endif
/** @} */ /** @} */
@ -349,6 +351,15 @@
*/ */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief Debug option, kernel statistics.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_STATISTICS) || defined(__DOXYGEN__)
#define CH_DBG_STATISTICS TRUE
#endif
/** /**
* @brief Debug option, system state check. * @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked * @details If enabled the correct call protocol for system APIs is checked
@ -357,7 +368,7 @@
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) #if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_SYSTEM_STATE_CHECK TRUE #define CH_DBG_SYSTEM_STATE_CHECK TRUE
#endif #endif
/** /**
@ -368,7 +379,7 @@
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_CHECKS TRUE #define CH_DBG_ENABLE_CHECKS TRUE
#endif #endif
/** /**
@ -380,7 +391,7 @@
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_ASSERTS TRUE #define CH_DBG_ENABLE_ASSERTS TRUE
#endif #endif
/** /**
@ -391,7 +402,7 @@
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_TRACE TRUE #define CH_DBG_ENABLE_TRACE TRUE
#endif #endif
/** /**
@ -405,7 +416,7 @@
* @p panic_msg variable set to @p NULL. * @p panic_msg variable set to @p NULL.
*/ */
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_STACK_CHECK TRUE #define CH_DBG_ENABLE_STACK_CHECK TRUE
#endif #endif
/** /**
@ -417,20 +428,20 @@
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
#define CH_DBG_FILL_THREADS TRUE #define CH_DBG_FILL_THREADS TRUE
#endif #endif
/** /**
* @brief Debug option, threads profiling. * @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that * @details If enabled then a field is added to the @p thread_t structure that
* counts the system ticks occurred while executing the thread. * counts the system ticks occurred while executing the thread.
* *
* @note The default is @p TRUE. * @note The default is @p FALSE.
* @note This debug option is defaulted to TRUE because it is required by * @note This debug option is not currently compatible with the
* some test cases into the test suite. * tickless mode.
*/ */
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING TRUE #define CH_DBG_THREADS_PROFILING FALSE
#endif #endif
/** @} */ /** @} */
@ -444,10 +455,10 @@
/** /**
* @brief Threads descriptor structure extension. * @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure. * @details User fields added to the end of the @p thread_t structure.
*/ */
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #if !defined(CH_CFG_THREAD_EXTRA_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \ #define CH_CFG_THREAD_EXTRA_FIELDS \
/* Add threads custom fields here.*/ /* Add threads custom fields here.*/
#endif #endif
@ -458,8 +469,8 @@
* @note It is invoked from within @p chThdInit() and implicitly from all * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs. * the threads creation APIs.
*/ */
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_THREAD_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \ #define CH_CFG_THREAD_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \ /* Add threads initialization code here.*/ \
} }
#endif #endif
@ -472,8 +483,8 @@
* @note It is also invoked when the threads simply return in order to * @note It is also invoked when the threads simply return in order to
* terminate. * terminate.
*/ */
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_THREAD_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \ #define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \ /* Add threads finalization code here.*/ \
} }
#endif #endif
@ -482,18 +493,40 @@
* @brief Context switch hook. * @brief Context switch hook.
* @details This hook is invoked just before switching between threads. * @details This hook is invoked just before switching between threads.
*/ */
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ #define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \ /* System halt code here.*/ \
} }
#endif #endif
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#if !defined(CH_CFG_IDLE_ENTER_HOOK) || defined(__DOXYGEN__)
#define CH_CFG_IDLE_ENTER_HOOK() { \
}
#endif
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#if !defined(CH_CFG_IDLE_LEAVE_HOOK) || defined(__DOXYGEN__)
#define CH_CFG_IDLE_LEAVE_HOOK() { \
}
#endif
/** /**
* @brief Idle Loop hook. * @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop. * @details This hook is continuously invoked by the idle thread loop.
*/ */
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \ #define CH_CFG_IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \ /* Idle loop code here.*/ \
} }
#endif #endif
@ -503,8 +536,8 @@
* @details This hook is invoked in the system tick handler immediately * @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue. * after processing the virtual timers queue.
*/ */
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_SYSTEM_TICK_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \ #define CH_CFG_SYSTEM_TICK_HOOK() { \
/* System tick event code here.*/ \ /* System tick event code here.*/ \
} }
#endif #endif
@ -514,8 +547,8 @@
* @details This hook is invoked in case to a system halting error before * @details This hook is invoked in case to a system halting error before
* the system is halted. * the system is halted.
*/ */
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \ #define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \ /* System halt code here.*/ \
} }
#endif #endif

7
testhal/STM32F4xx/UART/halconf.h
View File

@ -30,13 +30,6 @@
#include "mcuconf.h" #include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM TRUE
#endif
/** /**
* @brief Enables the PAL subsystem. * @brief Enables the PAL subsystem.
*/ */

14
testhal/STM32F4xx/UART/main.c
View File

@ -17,7 +17,7 @@
#include "ch.h" #include "ch.h"
#include "hal.h" #include "hal.h"
static VirtualTimer vt3, vt4, vt5; static virtual_timer_t vt3, vt4, vt5;
static const uint8_t message[] = "0123456789ABCDEF"; static const uint8_t message[] = "0123456789ABCDEF";
static uint8_t buffer[16]; static uint8_t buffer[16];
@ -56,11 +56,11 @@ static void txend2(UARTDriver *uartp) {
(void)uartp; (void)uartp;
palSetPad(GPIOD, GPIOD_LED5); palSetPad(GPIOD, GPIOD_LED5);
chSysLockFromIsr(); chSysLockFromISR();
if (chVTIsArmedI(&vt5)) if (chVTIsArmedI(&vt5))
chVTResetI(&vt5); chVTResetI(&vt5);
chVTSetI(&vt5, MS2ST(200), led5off, NULL); chVTSetI(&vt5, MS2ST(200), led5off, NULL);
chSysUnlockFromIsr(); chSysUnlockFromISR();
} }
/* /*
@ -83,11 +83,11 @@ static void rxchar(UARTDriver *uartp, uint16_t c) {
(void)c; (void)c;
/* Flashing the LED each time a character is received.*/ /* Flashing the LED each time a character is received.*/
palSetPad(GPIOD, GPIOD_LED4); palSetPad(GPIOD, GPIOD_LED4);
chSysLockFromIsr(); chSysLockFromISR();
if (chVTIsArmedI(&vt4)) if (chVTIsArmedI(&vt4))
chVTResetI(&vt4); chVTResetI(&vt4);
chVTSetI(&vt4, MS2ST(200), led4off, NULL); chVTSetI(&vt4, MS2ST(200), led4off, NULL);
chSysUnlockFromIsr(); chSysUnlockFromISR();
} }
/* /*
@ -99,11 +99,11 @@ static void rxend(UARTDriver *uartp) {
/* Flashing the LED each time a character is received.*/ /* Flashing the LED each time a character is received.*/
palSetPad(GPIOD, GPIOD_LED3); palSetPad(GPIOD, GPIOD_LED3);
chSysLockFromIsr(); chSysLockFromISR();
if (chVTIsArmedI(&vt3)) if (chVTIsArmedI(&vt3))
chVTResetI(&vt3); chVTResetI(&vt3);
chVTSetI(&vt3, MS2ST(200), led3off, NULL); chVTSetI(&vt3, MS2ST(200), led3off, NULL);
chSysUnlockFromIsr(); chSysUnlockFromISR();
} }
/* /*

10
testhal/STM32F4xx/UART/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 TRUE #define STM32_UART_USE_USART1 TRUE
#define STM32_UART_USE_USART2 TRUE #define STM32_UART_USE_USART2 TRUE
#define STM32_UART_USE_USART3 TRUE #define STM32_UART_USE_USART3 TRUE
#define STM32_UART_USE_UART4 TRUE
#define STM32_UART_USE_UART5 TRUE
#define STM32_UART_USE_USART6 TRUE #define STM32_UART_USE_USART6 TRUE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

10
testhal/STM32F4xx/USB_CDC/mcuconf.h
View File

@ -245,6 +245,8 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
@ -252,15 +254,23 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")