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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@355 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2008-07-25 15:13:41 +00:00
parent f88d25da6f
commit 5816f95f28
2 changed files with 33 additions and 20 deletions
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52
ports/ARMCM3/chcore.c
View File

@ -118,6 +118,34 @@ void SVCallVector(Thread *otp, Thread *ntp) {
#endif
}
#ifdef CH_CURRP_REGISTER_CACHE
#define PUSH_CONTEXT(sp) { \
register uint32_t tmp asm ("r3") = BASEPRI_USER; \
asm volatile ("mrs %0, PSP \n\t" \
"stmdb %0!, {r3-r6,r8-r11, lr}" : \
"=r" (sp) : "r" (sp), "r" (tmp)); \
}
#define POP_CONTEXT(sp) { \
asm volatile ("ldmia %0!, {r3-r6,r8-r11, lr} \n\t" \
"msr PSP, %0 \n\t" \
"msr BASEPRI, r3" : "=r" (sp) : "r" (sp)); \
}
#else
#define PUSH_CONTEXT(sp) { \
register uint32_t tmp asm ("r3") = BASEPRI_USER; \
asm volatile ("mrs %0, PSP \n\t" \
"stmdb %0!, {r3-r11,lr}" : \
"=r" (sp) : "r" (sp), "r" (tmp)); \
}
#define POP_CONTEXT(sp) { \
asm volatile ("ldmia %0!, {r3-r11, lr} \n\t" \
"msr PSP, %0 \n\t" \
"msr BASEPRI, r3" : "=r" (sp) : "r" (sp)); \
}
#endif
/*
* Preemption invoked context switch.
*/
@ -134,18 +162,7 @@ void PendSVVector(void) {
}
asm volatile ("pop {lr}");
register uint32_t tmp asm ("r3") = BASEPRI_USER;
#ifdef CH_CURRP_REGISTER_CACHE
asm volatile ("mrs %0, PSP \n\t" \
"stmdb %0!, {r3-r6,r8-r11, lr}" :
"=r" (sp_thd) :
"r" (sp_thd), "r" (tmp));
#else
asm volatile ("mrs %0, PSP \n\t" \
"stmdb %0!, {r3-r11,lr}" :
"=r" (sp_thd) :
"r" (sp_thd), "r" (tmp));
#endif
PUSH_CONTEXT(sp_thd);
(otp = currp)->p_ctx.r13 = sp_thd;
chSchReadyI(otp);
@ -159,12 +176,7 @@ void PendSVVector(void) {
#endif
sp_thd = currp->p_ctx.r13;
#ifdef CH_CURRP_REGISTER_CACHE
asm volatile ("ldmia %0!, {r3-r6,r8-r11, lr}" : : "r" (sp_thd));
#else
asm volatile ("ldmia %0!, {r3-r11, lr}" : : "r" (sp_thd));
#endif
asm volatile ("msr PSP, %0 \n\t" \
"msr BASEPRI, r3 \n\t" \
"bx lr" : : "r" (sp_thd));
POP_CONTEXT(sp_thd);
asm volatile ("bx lr");
}

1
readme.txt
View File

@ -81,6 +81,7 @@ Win32-MinGW - ChibiOS/RT simulator and demo into a WIN32 process,
faster if the feature is not required. Threads at the same priority are
still supported when the feature is disabled but the scheduling among them
becomes cooperative.
- Made the Cortex-M3 port preemption code more readable.
*** 0.6.8 ***
- FIX: Fixed a bug in the priority inheritance mechanism, the bug was only a