I2C. All is broken. Need rewrite.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@2919 35acf78f-673a-0410-8e92-d51de3d6d3f4master
barthess
parent
2459b2beb0
commit
5387a1b39f
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@ -33,7 +33,24 @@
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver constants. */
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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#define I2CD_NO_ERROR 0
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/** @brief Bus Error.*/
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#define I2CD_BUS_ERROR 0x01
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/** @brief Arbitration Lost (master mode).*/
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#define I2CD_ARBITRATION_LOST 0x02
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/** @brief Acknowledge Failure.*/
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#define I2CD_ACK_FAILURE 0x04
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/** @brief Overrun/Underrun.*/
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#define I2CD_OVERRUN 0x08
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/** @brief PEC Error in reception.*/
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#define I2CD_PEC_ERROR 0x10
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/** @brief Timeout or Tlow Error.*/
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#define I2CD_TIMEOUT 0x20
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/** @brief SMBus Alert.*/
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#define I2CD_SMB_ALERT 0x40
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -48,6 +65,9 @@
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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#if I2C_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES
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#error "I2C_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES"
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#endif
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/* Driver data structures and types. */
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@ -57,16 +77,11 @@
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* @brief Driver state machine possible states.
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* @brief Driver state machine possible states.
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*/
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*/
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typedef enum {
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typedef enum {
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I2C_UNINIT = 0, /**< Not initialized. */
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I2C_UNINIT = 0, /**< @brief Not initialized. */
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I2C_STOP = 1, /**< Stopped. */
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I2C_STOP = 1, /**< @brief Stopped. */
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I2C_READY = 2, /**< Ready. Start condition generated. */
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I2C_READY = 2, /**< @brief Ready. */
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I2C_MACTIVE = 3, /**< I2C configured and waiting start cond. */
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I2C_ACTIVE = 3, /**< @brief In communication. */
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I2C_10BIT_HANDSHAKE = 4, /**< 10-bit address sending */
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I2C_COMPLETE = 4, /**< @brief Asynchronous operation complete. */
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I2C_MWAIT_ADDR_ACK = 5, /**< Waiting ACK on address sending. */
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I2C_MTRANSMIT = 6, /**< Master transmitting. */
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I2C_MRECEIVE = 7, /**< Master receiving. */
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I2C_MWAIT_TF = 8, /**< Master wait Transmission Finished */
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I2C_MERROR = 9, /**< Error condition. */
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// slave part
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// slave part
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I2C_SACTIVE = 10,
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I2C_SACTIVE = 10,
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@ -33,203 +33,203 @@ I2CDriver I2CD2;
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/* Driver local functions. */
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/**
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* @brief Interrupt service routine.
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static uint32_t i2c_get_event(I2CDriver *i2cp){
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* @details This function handle all ERROR interrupt conditions.
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uint32_t regSR1 = i2cp->i2c_register->SR1;
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*
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uint32_t regSR2 = i2cp->i2c_register->SR2;
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* @param[in] i2cp pointer to the @p I2CDriver object
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/* return the last event value from I2C status registers */
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*/
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return (I2C_EV_MASK & (regSR1 | (regSR2 << 16)));
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static void i2c_serve_error_interrupt(I2CDriver *i2cp) {
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//TODO: more robust error handling
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chSysLockFromIsr();
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i2cp->id_slave_config->id_err_callback(i2cp, i2cp->id_slave_config);
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chSysUnlockFromIsr();
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}
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}
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/* helper function, not API
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* write bytes in DR register
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* return TRUE if last byte written
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*/
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inline bool_t i2c_lld_txbyte(I2CDriver *i2cp) {
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#define _txbufhead (i2cp->id_slave_config->txbufhead)
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#define _txbytes (i2cp->id_slave_config->txbytes)
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#define _txbuf (i2cp->id_slave_config->txbuf)
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if (_txbufhead < _txbytes){
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/* disable interrupt to avoid jumping to ISR */
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if ( _txbytes - _txbufhead == 1)
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i2cp->id_i2c->CR2 &= (~I2C_CR2_ITBUFEN);
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i2cp->id_i2c->DR = _txbuf[_txbufhead];
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(_txbufhead)++;
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return(FALSE);
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}
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_txbufhead = 0;
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return(TRUE); // last byte written
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#undef _txbufhead
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#undef _txbytes
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#undef _txbuf
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}
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/* helper function, not API
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* read bytes from DR register
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* return TRUE if last byte read
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*/
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inline bool_t i2c_lld_rxbyte(I2CDriver *i2cp) {
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// temporal variables
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#define _rxbuf (i2cp->id_slave_config->rxbuf)
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#define _rxbufhead (i2cp->id_slave_config->rxbufhead)
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#define _rxbytes (i2cp->id_slave_config->rxbytes)
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/* In order to generate the non-acknowledge pulse after the last received
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* data byte, the ACK bit must be cleared just after reading the second
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* last data byte (after second last RxNE event).
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*/
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if (_rxbufhead < (_rxbytes - 1)){
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_rxbuf[_rxbufhead] = i2cp->id_i2c->DR;
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if ((_rxbytes - _rxbufhead) <= 2){
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// clear ACK bit for automatically send NACK
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i2cp->id_i2c->CR1 &= (~I2C_CR1_ACK);
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}
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(_rxbufhead)++;
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return(FALSE);
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}
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/* disable interrupt to avoid jumping to ISR */
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i2cp->id_i2c->CR2 &= (~I2C_CR2_ITBUFEN);
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_rxbuf[_rxbufhead] = i2cp->id_i2c->DR; // read last byte
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_rxbufhead = 0;
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return(TRUE); // last byte read
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#undef _rxbuf
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#undef _rxbufhead
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#undef _rxbytes
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}
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/**
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* @brief Interrupt service routine.
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* @details This function handle all regular interrupt conditions.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*/
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static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
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static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
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static __IO uint8_t *txBuffp, *rxBuffp, *datap;
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#if CH_DBG_ENABLE_CHECKS
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I2C_TypeDef *dp = i2cp->i2c_register;
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// debug variables
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int i = 0;
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int n = 0;
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int m = 0;
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#endif
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/* In 10-bit addressing mode,
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switch(i2c_get_event(i2cp)) {
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– To enter Transmitter mode, a master sends the header (11110xx0) and then the
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case I2C_EV5_MASTER_MODE_SELECT:
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slave address, (where xx denotes the two most significant bits of the address).
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i2cp->flags &= ~I2C_FLG_HEADER_SENT;
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– To enter Receiver mode, a master sends the header (11110xx0) and then the
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dp->DR = i2cp->slave_addr1;
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slave address. Then it should send a repeated Start condition followed by the
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break;
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header (11110xx1), (where xx denotes the two most significant bits of the
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case I2C_EV9_MASTER_ADDR_10BIT:
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address).
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if(i2cp->flags & I2C_FLG_MASTER_RECEIVER) {
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The TRA bit indicates whether the master is in Receiver or Transmitter mode.*/
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i2cp->slave_addr1 |= 0x01;
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i2cp->flags |= I2C_FLG_HEADER_SENT;
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if ((i2cp->id_state == I2C_READY) && (i2cp->id_i2c->SR1 & I2C_SR1_SB)){// start bit sent
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i2cp->id_state = I2C_MACTIVE;
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if(!(i2cp->id_slave_config->address & 0x8000)){ // slave address is 7-bit
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i2cp->id_i2c->DR = ((i2cp->id_slave_config->address & 0x7F) << 1) |
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i2cp->rw_bit;
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i2cp->id_state = I2C_MWAIT_ADDR_ACK;
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return;
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}
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}
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else{ // slave address is 10-bit
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dp->DR = i2cp->slave_addr2;
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i2cp->id_state = I2C_10BIT_HANDSHAKE;
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break;
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// send MSB with header. LSB = 0.
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//------------------------------------------------------------------------
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i2cp->id_i2c->DR = ((i2cp->id_slave_config->address >> 7) & 0x6) | 0xF0;
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// Master Transmitter ----------------------------------------------------
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return;
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//------------------------------------------------------------------------
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case I2C_EV6_MASTER_TRA_MODE_SELECTED:
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if(i2cp->flags & I2C_FLG_HEADER_SENT){
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dp->CR1 |= I2C_CR1_START; // re-send the start in 10-Bit address mode
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break;
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}
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}
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//Initialize the transmit buffer pointer
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txBuffp = (uint8_t*)i2cp->txbuf;
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datap = txBuffp;
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txBuffp++;
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i2cp->remaining_bytes--;
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/* If no further data to be sent, disable the I2C ITBUF in order to not have a TxE interrupt */
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if(i2cp->remaining_bytes == 0) {
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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}
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}
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//EV8_1 write the first data
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// "wait" interrupt with ADD10 flag
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dp->DR = *datap;
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if ((i2cp->id_state == I2C_10BIT_HANDSHAKE) && (i2cp->id_i2c->SR1 & I2C_SR1_ADD10)){
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break;
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i2cp->id_i2c->DR = i2cp->id_slave_config->address & 0x00FF; // send remaining bits of address
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case I2C_EV8_MASTER_BYTE_TRANSMITTING:
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if (!(i2cp->rw_bit))
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if(i2cp->remaining_bytes > 0) {
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// in transmit mode there is nothing to do with 10-bit handshaking
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datap = txBuffp;
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i2cp->id_state = I2C_MWAIT_ADDR_ACK;
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txBuffp++;
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return;
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i2cp->remaining_bytes--;
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if(i2cp->remaining_bytes == 0) {
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/* If no further data to be sent, disable the ITBUF in order to not have a TxE interrupt */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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}
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}
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dp->DR = *datap;
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// "wait" interrupt with ADDR flag
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if ((i2cp->id_state == I2C_10BIT_HANDSHAKE) && (i2cp->id_i2c->SR1 & I2C_SR1_ADDR)){// address ACKed
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i2cp->id_i2c->CR1 |= I2C_CR1_START;
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return;
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}
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}
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break;
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if ((i2cp->id_state == I2C_10BIT_HANDSHAKE) && (i2cp->id_i2c->SR1 & I2C_SR1_SB)){// restart generated
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case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
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// send MSB with header. LSB = 1
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dp->CR1 |= I2C_CR1_STOP; // stop generation
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i2cp->id_i2c->DR = ((i2cp->id_slave_config->address >> 7) & 0x6) | 0xF1;
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/* Disable ITEVT In order to not have again a BTF IT */
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i2cp->id_state = I2C_MWAIT_ADDR_ACK;
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dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN;
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return;
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/* Portable I2C ISR code defined in the high level driver, note, it is a macro.*/
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}
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_i2c_isr_code(i2cp);
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break;
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// "wait" interrupt with ADDR (ADD10 in 10-bit receiver mode) flag
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//------------------------------------------------------------------------
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if ((i2cp->id_state == I2C_MWAIT_ADDR_ACK) && (i2cp->id_i2c->SR1 & (I2C_SR1_ADDR | I2C_SR1_ADD10))){// address ACKed
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// Master Receiver -------------------------------------------------------
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if(i2cp->id_i2c->SR2 & I2C_SR2_TRA){// I2C is transmitting data
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//------------------------------------------------------------------------
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i2cp->id_state = I2C_MTRANSMIT; // change state
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case I2C_EV6_MASTER_REC_MODE_SELECTED:
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i2c_lld_txbyte(i2cp); // send first byte
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return;
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}
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else {// I2C is receiving data
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/* In order to generate the non-acknowledge pulse after the last received
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* data byte, the ACK bit must be cleared just after reading the second
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* last data byte (after second last RxNE event).
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*/
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if (i2cp->id_slave_config->rxbytes > 1)
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i2cp->id_i2c->CR1 |= I2C_CR1_ACK; // set ACK bit
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i2cp->id_state = I2C_MRECEIVE; // change state
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return;
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}
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}
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// transmitting bytes one by one
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if ((i2cp->id_state == I2C_MTRANSMIT) && (i2cp->id_i2c->SR1 & I2C_SR1_TXE)){
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if (i2c_lld_txbyte(i2cp))
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i2cp->id_state = I2C_MWAIT_TF; // last byte written
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return;
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}
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//receiving bytes one by one
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if ((i2cp->id_state == I2C_MRECEIVE) && (i2cp->id_i2c->SR1 & I2C_SR1_RXNE)){
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if (i2c_lld_rxbyte(i2cp))
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i2cp->id_state = I2C_MWAIT_TF; // last byte read
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return;
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}
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// "wait" BTF bit in status register
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if ((i2cp->id_state == I2C_MWAIT_TF) && (i2cp->id_i2c->SR1 & I2C_SR1_BTF)){
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chSysLockFromIsr();
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chSysLockFromIsr();
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i2cp->id_i2c->CR2 &= (~I2C_CR2_ITEVTEN); // disable BTF interrupt
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switch(i2cp->flags & EV6_SUBEV_MASK) {
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case I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED: // only an single byte to receive
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/* Clear ACK */
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dp->CR1 &= (uint16_t)~I2C_CR1_ACK;
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/* Program the STOP */
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dp->CR1 |= I2C_CR1_STOP;
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break;
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case I2C_EV6_1_MASTER_REC_2BTR_MODE_SELECTED: // only two bytes to receive
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/* Clear ACK */
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dp->CR1 &= (uint16_t)~I2C_CR1_ACK;
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/* Disable the ITBUF in order to have only the BTF interrupt */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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break;
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}
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chSysUnlockFromIsr();
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chSysUnlockFromIsr();
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/* now driver is ready to generate (re)start/stop condition.
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/* Initialize receive buffer pointer */
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* Callback function is good place to do that. If not callback was
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rxBuffp = i2cp->rxbuf;
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* set - driver only generate stop condition. */
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break;
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i2cp->id_state = I2C_READY;
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case I2C_EV7_MASTER_REC_BYTE_RECEIVED:
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if(i2cp->remaining_bytes != 3) {
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if (i2cp->id_slave_config->id_callback != NULL)
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/* Read the data register */
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i2cp->id_slave_config->id_callback(i2cp, i2cp->id_slave_config);
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*rxBuffp = dp->DR;
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else /* No callback function set. Generate stop */
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rxBuffp++;
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i2c_lld_master_stop(i2cp);
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i2cp->remaining_bytes--;
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switch(i2cp->remaining_bytes){
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return;
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case 3:
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/* Disable the ITBUF in order to have only the BTF interrupt */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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i2cp->flags |= I2C_FLG_3BTR;
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break;
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case 0:
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/* Portable I2C ISR code defined in the high level driver, note, it is a macro.*/
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_i2c_isr_code(i2cp);
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break;
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}
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}
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#if CH_DBG_ENABLE_CHECKS
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else{ // debugging trap
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i = i2cp->id_i2c->SR1;
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n = i2cp->id_i2c->SR2;
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m = i2cp->id_i2c->CR1;
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while(TRUE);
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}
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}
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#endif /* CH_DBG_ENABLE_CHECKS */
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// when remaining 3 bytes do nothing, wait until RXNE and BTF are set (until 2 bytes are received)
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break;
|
||||||
|
case I2C_EV7_MASTER_REC_BYTE_QUEUED:
|
||||||
|
switch(i2cp->flags & EV7_SUBEV_MASK) {
|
||||||
|
case I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS:
|
||||||
|
// DataN-2 and DataN-1 are received
|
||||||
|
chSysLockFromIsr();
|
||||||
|
dp->CR2 |= I2C_CR2_ITBUFEN;
|
||||||
|
/* Clear ACK */
|
||||||
|
dp->CR1 &= (uint16_t)~I2C_CR1_ACK;
|
||||||
|
/* Read the DataN-2*/
|
||||||
|
*rxBuffp = dp->DR; //This clear the RXE & BFT flags and launch the DataN reception in the shift register (ending the SCL stretch)
|
||||||
|
rxBuffp++;
|
||||||
|
/* Program the STOP */
|
||||||
|
dp->CR1 |= I2C_CR1_STOP;
|
||||||
|
/* Read the DataN-1 */
|
||||||
|
*rxBuffp = dp->DR;
|
||||||
|
chSysUnlockFromIsr();
|
||||||
|
rxBuffp++;
|
||||||
|
/* Decrement the number of readed bytes */
|
||||||
|
i2cp->remaining_bytes -= 2;
|
||||||
|
i2cp->flags = 0;
|
||||||
|
// ready for read DataN on the next EV7
|
||||||
|
break;
|
||||||
|
case I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS: // only for case of two bytes to be received
|
||||||
|
// DataN-1 and DataN are received
|
||||||
|
chSysLockFromIsr();
|
||||||
|
/* Program the STOP */
|
||||||
|
dp->CR1 |= I2C_CR1_STOP;
|
||||||
|
/* Read the DataN-1*/
|
||||||
|
*rxBuffp = dp->DR;
|
||||||
|
chSysUnlockFromIsr();
|
||||||
|
rxBuffp++;
|
||||||
|
/* Read the DataN*/
|
||||||
|
*rxBuffp = dp->DR;
|
||||||
|
i2cp->remaining_bytes = 0;
|
||||||
|
i2cp->flags = 0;
|
||||||
|
/* Portable I2C ISR code defined in the high level driver, note, it is a macro.*/
|
||||||
|
_i2c_isr_code(i2cp);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void i2c_serve_error_interrupt(I2CDriver *i2cp) {
|
||||||
|
i2cflags_t flags;
|
||||||
|
I2C_TypeDef *reg;
|
||||||
|
|
||||||
|
reg = i2cp->i2c_register;
|
||||||
|
flags = I2CD_NO_ERROR;
|
||||||
|
|
||||||
|
if(reg->SR1 & I2C_SR1_BERR) { // Bus error
|
||||||
|
reg->SR1 &= ~I2C_SR1_BERR;
|
||||||
|
flags |= I2CD_BUS_ERROR;
|
||||||
|
}
|
||||||
|
if(reg->SR1 & I2C_SR1_ARLO) { // Arbitration lost
|
||||||
|
reg->SR1 &= ~I2C_SR1_ARLO;
|
||||||
|
flags |= I2CD_ARBITRATION_LOST;
|
||||||
|
}
|
||||||
|
if(reg->SR1 & I2C_SR1_AF) { // Acknowledge fail
|
||||||
|
reg->SR1 &= ~I2C_SR1_AF;
|
||||||
|
reg->CR1 |= I2C_CR1_STOP; // setting stop bit
|
||||||
|
flags |= I2CD_ACK_FAILURE;
|
||||||
|
}
|
||||||
|
if(reg->SR1 & I2C_SR1_OVR) { // Overrun
|
||||||
|
reg->SR1 &= ~I2C_SR1_OVR;
|
||||||
|
flags |= I2CD_OVERRUN;
|
||||||
|
}
|
||||||
|
if(reg->SR1 & I2C_SR1_PECERR) { // PEC error
|
||||||
|
reg->SR1 &= ~I2C_SR1_PECERR;
|
||||||
|
flags |= I2CD_PEC_ERROR;
|
||||||
|
}
|
||||||
|
if(reg->SR1 & I2C_SR1_TIMEOUT) { // SMBus Timeout
|
||||||
|
reg->SR1 &= ~I2C_SR1_TIMEOUT;
|
||||||
|
flags |= I2CD_TIMEOUT;
|
||||||
|
}
|
||||||
|
if(reg->SR1 & I2C_SR1_SMBALERT) { // SMBus alert
|
||||||
|
reg->SR1 &= ~I2C_SR1_SMBALERT;
|
||||||
|
flags |= I2CD_SMB_ALERT;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(flags != I2CD_NO_ERROR) {
|
||||||
|
// send communication end signal
|
||||||
|
_i2c_isr_code(i2cp);
|
||||||
|
chSysLockFromIsr();
|
||||||
|
i2cAddFlagsI(i2cp, flags);
|
||||||
|
chSysUnlockFromIsr();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
|
#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
|
||||||
/**
|
/**
|
||||||
* @brief I2C1 event interrupt handler.
|
* @brief I2C1 event interrupt handler.
|
||||||
|
|
@ -329,6 +329,15 @@ void i2c_lld_start(I2CDriver *i2cp) {
|
||||||
i2cp->id_i2c->CR1 |= 1; // enable interface
|
i2cp->id_i2c->CR1 |= 1; // enable interface
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void i2c_lld_reset(I2CDriver *i2cp){
|
||||||
|
chDbgCheck((i2cp->state == I2C_STOP)||(i2cp->state == I2C_READY),
|
||||||
|
"i2c_lld_reset: invalid state");
|
||||||
|
|
||||||
|
RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; // reset I2C 1
|
||||||
|
RCC->APB1RSTR = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Set clock speed.
|
* @brief Set clock speed.
|
||||||
*
|
*
|
||||||
|
|
@ -488,137 +497,97 @@ void i2c_lld_stop(I2CDriver *i2cp) {
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Generate start condition.
|
* @brief Transmits data ever the I2C bus as master.
|
||||||
*
|
*
|
||||||
* @param[in] i2cp pointer to the @p I2CDriver object
|
* @param[in] i2cp pointer to the @p I2CDriver object
|
||||||
*/
|
* @param[in] n number of words to send
|
||||||
void i2c_lld_master_start(I2CDriver *i2cp){
|
* @param[in] slave_addr1 the 7-bit address of the slave (should be aligned to left)
|
||||||
i2cp->id_i2c->CR1 |= I2C_CR1_START;
|
* @param[in] slave_addr2 used in 10 bit address mode
|
||||||
while (i2cp->id_i2c->CR1 & I2C_CR1_START);
|
* @param[in] txbuf the pointer to the transmit buffer
|
||||||
|
|
||||||
/* enable interrupts from I2C hardware. They will disable in driver state
|
|
||||||
machine after the transfer finish.*/
|
|
||||||
i2cp->id_i2c->CR2 |= I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Generate stop condition.
|
|
||||||
*
|
*
|
||||||
* @param[in] i2cp pointer to the @p I2CDriver object
|
|
||||||
*/
|
*/
|
||||||
void i2c_lld_master_stop(I2CDriver *i2cp){
|
void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, size_t n, void *txbuf) {
|
||||||
i2cp->id_i2c->CR1 |= I2C_CR1_STOP;
|
|
||||||
while (i2cp->id_i2c->CR1 & I2C_CR1_STOP);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
// enable ERR, EVT & BUF ITs
|
||||||
* @brief Begin data transmitting.
|
i2cp->i2c_register->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN);
|
||||||
*
|
i2cp->i2c_register->CR1 &= ~I2C_CR1_POS;
|
||||||
* @param[in] i2cp pointer to the @p I2CDriver object
|
|
||||||
* @param[in] i2cscfg pointer to the @p I2CSlaveConfig object
|
|
||||||
*/
|
|
||||||
void i2c_lld_master_transmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
|
|
||||||
|
|
||||||
i2cp->id_slave_config = i2cscfg;
|
switch(i2cp->nbit_address){
|
||||||
i2cp->rw_bit = I2C_WRITE;
|
case 7:
|
||||||
|
i2cp->slave_addr1 = ((slave_addr <<1) & 0x00FE); // LSB = 0 -> write
|
||||||
// generate start condition. Later transmission goes in background
|
break;
|
||||||
i2c_lld_master_start(i2cp);
|
case 10:
|
||||||
}
|
i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); // add the two msb of 10-bit address to the header
|
||||||
|
i2cp->slave_addr1 |= 0xF0; // add the header bits with LSB = 0 -> write
|
||||||
/**
|
i2cp->slave_addr2 = slave_addr & 0x00FF; // the remaining 8 bit of 10-bit address
|
||||||
* @brief Begin data receiving.
|
break;
|
||||||
*
|
|
||||||
* @param[in] i2cp pointer to the @p I2CDriver object
|
|
||||||
* @param[in] i2cscfg pointer to the @p I2CSlaveConfig object
|
|
||||||
*/
|
|
||||||
void i2c_lld_master_receive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
|
|
||||||
|
|
||||||
i2cp->id_slave_config = i2cscfg;
|
|
||||||
i2cp->rw_bit = I2C_READ;
|
|
||||||
|
|
||||||
// generate (re)start condition. Later connection goes asynchronously
|
|
||||||
i2c_lld_master_start(i2cp);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Transmits data via I2C bus.
|
|
||||||
*
|
|
||||||
* @note This function does not use interrupts
|
|
||||||
*
|
|
||||||
* @param[in] i2cp pointer to the @p I2CDriver object
|
|
||||||
* @param[in] i2cscfg pointer to the @p I2CSlaveConfig object
|
|
||||||
* @param[in] restart bool. If TRUE then generate restart condition instead of stop
|
|
||||||
*/
|
|
||||||
void i2c_lld_master_transmit_NI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, bool_t restart) {
|
|
||||||
|
|
||||||
int i = 0;
|
|
||||||
|
|
||||||
i2cp->id_slave_config = i2cscfg;
|
|
||||||
i2cp->rw_bit = I2C_WRITE;
|
|
||||||
|
|
||||||
|
|
||||||
i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate start condition
|
|
||||||
while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)); // wait Address sent
|
|
||||||
|
|
||||||
i2cp->id_i2c->DR = (i2cp->id_slave_config->address << 1) | I2C_WRITE; // write slave addres in DR
|
|
||||||
while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)); // wait Address sent
|
|
||||||
i = i2cp->id_i2c->SR2;
|
|
||||||
i = i2cp->id_i2c->SR1; //i2cp->id_i2c->SR1 &= (~I2C_SR1_ADDR); // clear ADDR bit
|
|
||||||
|
|
||||||
// now write data byte by byte in DR register
|
|
||||||
uint32_t n = 0;
|
|
||||||
for (n = 0; n < i2cp->id_slave_config->txbytes; n++){
|
|
||||||
i2cp->id_i2c->DR = i2cscfg->txbuf[n];
|
|
||||||
while (!(i2cp->id_i2c->SR1 & I2C_SR1_TXE));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
while (!(i2cp->id_i2c->SR1 & I2C_SR1_BTF));
|
i2cp->txbuf = txbuf;
|
||||||
|
i2cp->remaining_bytes = n;
|
||||||
|
i2cp->flags = 0;
|
||||||
|
i2cp->errors = 0;
|
||||||
|
|
||||||
if (restart){
|
i2cp->i2c_register->CR1 |= I2C_CR1_START; // send start bit
|
||||||
i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate restart condition
|
|
||||||
while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)); // wait start bit
|
#if !I2C_USE_WAIT
|
||||||
}
|
/* Wait until the START condition is generated on the bus: the START bit is cleared by hardware */
|
||||||
else i2cp->id_i2c->CR1 |= I2C_CR1_STOP; // generate stop condition
|
uint32_t tmo = 0xfffff;
|
||||||
|
while((i2cp->i2c_register->CR1 & I2C_CR1_START) && tmo--)
|
||||||
|
;
|
||||||
|
#endif /* I2C_USE_WAIT */
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Receives data from the I2C bus.
|
* @brief Receives data from the I2C bus.
|
||||||
* @note This function does not use interrupts
|
|
||||||
*
|
*
|
||||||
* @param[in] i2cp pointer to the @p I2CDriver object
|
* @param[in] i2cp pointer to the @p I2CDriver object
|
||||||
* @param[in] i2cscfg pointer to the @p I2CSlaveConfig object
|
* @param[in] slave_addr1 7-bit address of he slave
|
||||||
|
* @param[in] slave_addr2 used in 10-bit address mode
|
||||||
|
* @param[in] n number of words to receive
|
||||||
|
* @param[out] rxbuf the pointer to the receive buffer
|
||||||
|
*
|
||||||
*/
|
*/
|
||||||
void i2c_lld_master_receive_NI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {
|
void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, size_t n, void *rxbuf) {
|
||||||
|
// enable ERR, EVT & BUF ITs
|
||||||
|
i2cp->i2c_register->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN);
|
||||||
|
i2cp->i2c_register->CR1 |= I2C_CR1_ACK; // acknowledge returned
|
||||||
|
i2cp->i2c_register->CR1 &= ~I2C_CR1_POS;
|
||||||
|
|
||||||
i2cp->id_slave_config = i2cscfg;
|
switch(i2cp->nbit_address){
|
||||||
|
case 7:
|
||||||
uint16_t i = 0;
|
i2cp->slave_addr1 = ((slave_addr <<1) | 0x01); // LSB = 1 -> receive
|
||||||
|
break;
|
||||||
// send slave addres with read-bit
|
case 10:
|
||||||
i2cp->id_i2c->DR = (i2cp->id_slave_config->address << 1) | I2C_READ;
|
i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); // add the two msb of 10-bit address to the header
|
||||||
while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)); // wait Address sent
|
i2cp->slave_addr1 |= 0xF0; // add the header bits (the LSB -> 1 will be add to second
|
||||||
|
i2cp->slave_addr2 = slave_addr & 0x00FF; // the remaining 8 bit of 10-bit address
|
||||||
i = i2cp->id_i2c->SR2;
|
break;
|
||||||
i = i2cp->id_i2c->SR1; //i2cp->id_i2c->SR1 &= (~I2C_SR1_ADDR); // clear ADDR bit
|
|
||||||
|
|
||||||
// set ACK bit
|
|
||||||
i2cp->id_i2c->CR1 |= I2C_CR1_ACK;
|
|
||||||
|
|
||||||
// collect data from slave
|
|
||||||
for (i = 0; i < i2cp->id_slave_config->rxbytes; i++){
|
|
||||||
if ((i2cp->id_slave_config->rxbytes - i) == 1){
|
|
||||||
// clear ACK bit for automatically send NACK
|
|
||||||
i2cp->id_i2c->CR1 &= (~I2C_CR1_ACK);}
|
|
||||||
while (!(i2cp->id_i2c->SR1 & I2C_SR1_RXNE));
|
|
||||||
|
|
||||||
i2cp->id_slave_config->rxbuf[i] = i2cp->id_i2c->DR;
|
|
||||||
}
|
}
|
||||||
// generate STOP
|
|
||||||
i2cp->id_i2c->CR1 |= I2C_CR1_STOP;
|
i2cp->rxbuf = rxbuf;
|
||||||
|
i2cp->remaining_bytes = n;
|
||||||
|
i2cp->flags = I2C_FLG_MASTER_RECEIVER;
|
||||||
|
i2cp->errors = 0;
|
||||||
|
|
||||||
|
// Only one byte to be received
|
||||||
|
if(i2cp->remaining_bytes == 1) {
|
||||||
|
i2cp->flags |= I2C_FLG_1BTR;
|
||||||
|
}
|
||||||
|
// Only two bytes to be received
|
||||||
|
else if(i2cp->remaining_bytes == 2) {
|
||||||
|
i2cp->flags |= I2C_FLG_2BTR;
|
||||||
|
i2cp->i2c_register->CR1 |= I2C_CR1_POS; // Acknowledge Position
|
||||||
|
}
|
||||||
|
|
||||||
|
i2cp->i2c_register->CR1 |= I2C_CR1_START; // send start bit
|
||||||
|
|
||||||
|
#if !I2C_USE_WAIT
|
||||||
|
/* Wait until the START condition is generated on the bus: the START bit is cleared by hardware */
|
||||||
|
uint32_t tmo = 0xfffff;
|
||||||
|
while((i2cp->i2c_register->CR1 & I2C_CR1_START) && tmo--)
|
||||||
|
;
|
||||||
|
#endif /* I2C_USE_WAIT */
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -55,25 +55,45 @@
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Derived constants and error checks. */
|
/* Derived constants and error checks. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
#define I2CD_NO_ERROR 0
|
|
||||||
/** @brief Bus Error.*/
|
/** @brief EV5 */
|
||||||
#define I2CD_BUS_ERROR 0x01
|
#define I2C_EV5_MASTER_MODE_SELECT ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_SB)) /* BUSY, MSL and SB flag */
|
||||||
/** @brief Arbitration Lost (master mode).*/
|
/** @brief EV6 */
|
||||||
#define I2CD_ARBITRATION_LOST 0x02
|
#define I2C_EV6_MASTER_TRA_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_ADDR|I2C_SR1_TXE)) /* BUSY, MSL, ADDR, TXE and TRA flags */
|
||||||
/** @brief Acknowledge Failure.*/
|
#define I2C_EV6_MASTER_REC_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_ADDR)) /* BUSY, MSL and ADDR flags */
|
||||||
#define I2CD_ACK_FAILURE 0x04
|
/** @brief EV7 */
|
||||||
/** @brief Overrun/Underrun.*/
|
#define I2C_EV7_MASTER_REC_BYTE_RECEIVED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_RXNE)) /* BUSY, MSL and RXNE flags */
|
||||||
#define I2CD_OVERRUN 0x08
|
#define I2C_EV7_MASTER_REC_BYTE_QUEUED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_BTF|I2C_SR1_RXNE)) /* BUSY, MSL, RXNE and BTF flags*/
|
||||||
/** @brief PEC Error in reception.*/
|
/** @brief EV8 */
|
||||||
#define I2CD_PEC_ERROR 0x10
|
#define I2C_EV8_MASTER_BYTE_TRANSMITTING ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE flags */
|
||||||
/** @brief Timeout or Tlow Error.*/
|
/** @brief EV8_2 */
|
||||||
#define I2CD_TIMEOUT 0x20
|
#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_BTF|I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE and BTF flags */
|
||||||
/** @brief SMBus Alert.*/
|
/** @brief EV9 */
|
||||||
#define I2CD_SMB_ALERT 0x40
|
#define I2C_EV9_MASTER_ADDR_10BIT ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_ADD10)) /* BUSY, MSL and ADD10 flags */
|
||||||
|
#define I2C_EV_MASK 0x00FFFFFF
|
||||||
|
|
||||||
|
#define I2C_FLG_1BTR 0x01 // Single byte to be received and processed
|
||||||
|
#define I2C_FLG_2BTR 0x02 // Two bytes to be received and processed
|
||||||
|
#define I2C_FLG_3BTR 0x04 // Last three received bytes to be processed
|
||||||
|
#define I2C_FLG_MASTER_RECEIVER 0x10
|
||||||
|
#define I2C_FLG_HEADER_SENT 0x80
|
||||||
|
|
||||||
|
#define EV6_SUBEV_MASK (I2C_FLG_1BTR|I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER)
|
||||||
|
#define EV7_SUBEV_MASK (I2C_FLG_2BTR|I2C_FLG_3BTR|I2C_FLG_MASTER_RECEIVER)
|
||||||
|
|
||||||
|
#define I2C_EV6_1_MASTER_REC_2BTR_MODE_SELECTED (I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER)
|
||||||
|
#define I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED (I2C_FLG_1BTR|I2C_FLG_MASTER_RECEIVER)
|
||||||
|
#define I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS (I2C_FLG_3BTR|I2C_FLG_MASTER_RECEIVER)
|
||||||
|
#define I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS (I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER)
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver data structures and types. */
|
/* Driver data structures and types. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Serial Driver condition flags type.
|
||||||
|
*/
|
||||||
|
typedef uint32_t i2cflags_t;
|
||||||
|
|
||||||
typedef enum {
|
typedef enum {
|
||||||
opmodeI2C,
|
opmodeI2C,
|
||||||
opmodeSMBusDevice,
|
opmodeSMBusDevice,
|
||||||
|
|
@ -176,20 +196,14 @@ extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void i2c_lld_init(void);
|
void i2c_lld_init(void);
|
||||||
|
void i2c_lld_reset(I2CDriver *i2cp);
|
||||||
|
void i2c_lld_set_clock(I2CDriver *i2cp, int32_t clock_speed, I2C_DutyCycle_t duty);
|
||||||
|
void i2c_lld_set_opmode(I2CDriver *i2cp, I2C_opMode_t opmode);
|
||||||
|
void i2c_lld_set_own_address(I2CDriver *i2cp, int16_t address, int8_t nr_bit);
|
||||||
void i2c_lld_start(I2CDriver *i2cp);
|
void i2c_lld_start(I2CDriver *i2cp);
|
||||||
void i2c_lld_stop(I2CDriver *i2cp);
|
void i2c_lld_stop(I2CDriver *i2cp);
|
||||||
void i2c_lld_set_clock(I2CDriver *i2cp);
|
void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, size_t n, void *txbuf);
|
||||||
void i2c_lld_set_opmode(I2CDriver *i2cp);
|
void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, size_t n, void *rxbuf);
|
||||||
void i2c_lld_set_own_address(I2CDriver *i2cp);
|
|
||||||
|
|
||||||
void i2c_lld_master_start(I2CDriver *i2cp);
|
|
||||||
void i2c_lld_master_stop(I2CDriver *i2cp);
|
|
||||||
|
|
||||||
void i2c_lld_master_transmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
|
|
||||||
void i2c_lld_master_receive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
|
|
||||||
|
|
||||||
void i2c_lld_master_transmit_NI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, bool_t restart);
|
|
||||||
void i2c_lld_master_receive_NI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue