zcy
/
tinySA
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fixed DMAv1 errors. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8323 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
Giovanni Di Sirio 2015-09-22 10:19:58 +00:00
parent 6a008186f9
commit 4dc2ac9a14
2 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
View File

@ -135,16 +135,16 @@ const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
{DMA1_Channel5, DMA1_CH5_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 16, 4, STM32_DMA1_CH5_NUMBER},
#if STM32_DMA1_NUM_CHANNELS > 5
{DMA1_Channel6, DMA1_CH6_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 20, 5, STM32_DMA1_CH6_NUMBER},
#endif
#if STM32_DMA1_NUM_CHANNELS > 6
{DMA1_Channel7, DMA1_CH7_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 24, 6, STM32_DMA1_CH7_NUMBER},
#endif
#if STM32_DMA2_NUM_CHANNELS > 0
{DMA2_Channel1, DMA2_CH1_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 0, 8, STM32_DMA2_CH1_NUMBER},
{DMA2_Channel2, DMA2_CH2_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 4, 9, STM32_DMA2_CH2_NUMBER},
{DMA2_Channel3, DMA2_CH3_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 8, 10, STM32_DMA2_CH3_NUMBER},
{DMA2_Channel4, DMA2_CH4_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 12, 11, STM32_DMA2_CH4_NUMBER},
{DMA2_Channel5, DMA2_CH5_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 16, 13, STM32_DMA2_CH5_NUMBER},
{DMA2_Channel1, DMA2_CH1_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 0, 7, STM32_DMA2_CH1_NUMBER},
{DMA2_Channel2, DMA2_CH2_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 4, 8, STM32_DMA2_CH2_NUMBER},
{DMA2_Channel3, DMA2_CH3_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 8, 9, STM32_DMA2_CH3_NUMBER},
{DMA2_Channel4, DMA2_CH4_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 12, 10, STM32_DMA2_CH4_NUMBER},
{DMA2_Channel5, DMA2_CH5_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 16, 11, STM32_DMA2_CH5_NUMBER},
#endif
#endif
#endif
};

10
os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h
View File

@ -117,11 +117,11 @@
#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4)
#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5)
#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6)
#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(8)
#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(9)
#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(10)
#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(11)
#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(12)
#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7)
#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8)
#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9)
#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10)
#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11)
/** @} */
/**