[FSMC SRAM] Added driver code.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7195 35acf78f-673a-0410-8e92-d51de3d6d3f4master
barthess
parent
d12b4ee252
commit
4c53f50dd3
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@ -25,10 +25,10 @@
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* @addtogroup FSMC
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* @{
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*/
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#include "hal.h"
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#include "fsmc.h"
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#if HAL_USE_NAND || defined(__DOXYGEN__)
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#if HAL_USE_NAND || STM32_USE_FSMC_SRAM || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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@ -72,19 +72,37 @@ FSMCDriver FSMCD1;
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*/
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void fsmc_init(void) {
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FSMCD1.state = FSMC_STOP;
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if (FSMCD1.state == FSMC_UNINIT) {
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FSMCD1.state = FSMC_STOP;
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#if STM32_SRAM_USE_FSMC_SRAM1
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FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE);
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#endif
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#if STM32_SRAM_USE_FSMC_SRAM2
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FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8);
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#endif
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#if STM32_SRAM_USE_FSMC_SRAM3
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FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2);
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#endif
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#if STM32_SRAM_USE_FSMC_SRAM4
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FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3);
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#endif
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#if STM32_NAND_USE_FSMC_NAND1
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FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE;
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FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE;
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#endif
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#if STM32_NAND_USE_FSMC_NAND2
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FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE;
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FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE;
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#endif
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#if STM32_USE_FSMC_PCCARD
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FSMCD1.pccard = (FSMC_PCCARD_TypeDef *)FSMC_Bank4_R_BASE;
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FSMCD1.pccard = (FSMC_PCCARD_TypeDef *)FSMC_Bank4_R_BASE;
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#endif
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}
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}
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/**
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@ -96,7 +114,6 @@ void fsmc_init(void) {
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*/
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void fsmc_start(FSMCDriver *fsmcp) {
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osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY),
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"invalid state");
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@ -106,7 +123,7 @@ void fsmc_start(FSMCDriver *fsmcp) {
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if (&FSMCD1 == fsmcp) {
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rccResetFSMC();
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rccEnableFSMC(FALSE);
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#if !STM32_NAND_USE_EXT_INT
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#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND)
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nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY);
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#endif
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}
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@ -132,7 +149,7 @@ void fsmc_stop(FSMCDriver *fsmcp) {
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/* Disables the peripheral.*/
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#if STM32_FSMC_USE_FSMC1
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if (&FSMCD1 == fsmcp) {
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#if !STM32_NAND_USE_EXT_INT
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#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND)
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nvicDisableVector(STM32_FSMC_NUMBER);
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#endif
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rccDisableFSMC(FALSE);
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@ -166,6 +183,6 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) {
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}
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#endif /* !STM32_NAND_USE_EXT_INT */
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#endif /* HAL_USE_FSMC */
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#endif /* HAL_USE_FSMC || STM32_USE_FSMC_SRAM */
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/** @} */
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@ -20,17 +20,16 @@
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/**
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* @file fsmc.h
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* @brief FSMC Driver subsystem low level driver header template.
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* @brief FSMC Driver subsystem low level driver header.
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*
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* @addtogroup FSMC
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* @{
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*/
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#ifndef _FSMC_H_
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#define _FSMC_H_
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#if HAL_USE_NAND || defined(__DOXYGEN__)
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#if HAL_USE_NAND || STM32_USE_FSMC_SRAM || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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@ -44,6 +43,15 @@
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#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000)
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#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000)
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/*
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* Subbunks of bank1
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*/
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#define FSMC_SUBBUNK_OFFSET (1024 * 1024 * 64)
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#define FSMC_Bank1_1_MAP (FSMC_Bank1_MAP_BASE)
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#define FSMC_Bank1_2_MAP (FSMC_Bank1_1_MAP + FSMC_SUBBUNK_OFFSET)
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#define FSMC_Bank1_3_MAP (FSMC_Bank1_2_MAP + FSMC_SUBBUNK_OFFSET)
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#define FSMC_Bank1_4_MAP (FSMC_Bank1_3_MAP + FSMC_SUBBUNK_OFFSET)
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/*
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* Bank 2 (NAND)
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*/
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@ -99,6 +107,13 @@ typedef struct {
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__IO uint32_t PIO; /**< PC Card I/O space timing */
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} FSMC_PCCard_TypeDef;
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typedef struct {
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__IO uint32_t BCR; /**< SRAM/NOR chip-select control registers */
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__IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */
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uint32_t RESERVED[63]; /**< Reserved */
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__IO uint32_t BWTR; /**< SRAM/NOR write timing registers */
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} FSMC_SRAM_NOR_TypeDef;
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/**
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* @brief PCR register
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*/
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@ -122,10 +137,11 @@ typedef struct {
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#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS)
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/**
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* @brief RCR register
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* @brief BCR register
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*/
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#define FSMC_BCR_MBKEN ((uint32_t)0x00000001)
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#define FSMC_BCR_MUXEN ((uint32_t)0x00000002)
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#define FSMC_BCR_MWID_0 ((uint32_t)0x00000010)
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#define FSMC_BCR_FACCEN ((uint32_t)0x00000040)
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#define FSMC_BCR_BURSTEN ((uint32_t)0x00000100)
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#define FSMC_BCR_WAITPOL ((uint32_t)0x00000200)
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@ -189,14 +205,6 @@ typedef enum {
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FSMC_READY = 2, /**< Ready. */
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} fsmcstate_t;
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/**
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* @brief Driver configuration structure.
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* @note Empty on this architecture.
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*/
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typedef struct {
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} FSMCConfig;
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/**
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* @brief Structure representing an FSMC driver.
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*/
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@ -206,6 +214,19 @@ struct FSMCDriver {
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*/
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fsmcstate_t state;
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/* End of the mandatory fields.*/
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#if STM32_SRAM_USE_FSMC_SRAM1
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FSMC_SRAM_NOR_TypeDef *sram1;
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#endif
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#if STM32_SRAM_USE_FSMC_SRAM2
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FSMC_SRAM_NOR_TypeDef *sram2;
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#endif
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#if STM32_SRAM_USE_FSMC_SRAM3
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FSMC_SRAM_NOR_TypeDef *sram3;
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#endif
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#if STM32_SRAM_USE_FSMC_SRAM4
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FSMC_SRAM_NOR_TypeDef *sram4;
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#endif
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#if STM32_NAND_USE_FSMC_NAND1
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FSMC_NAND_TypeDef *nand1;
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#endif
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@ -239,7 +260,7 @@ extern "C" {
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}
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#endif
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#endif /* HAL_USE_NAND */
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#endif /* HAL_USE_NAND || STM32_USE_FSMC_SRAM */
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#endif /* _FSMC_H_ */
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@ -0,0 +1,159 @@
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/*
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ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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Concepts and parts of this file have been contributed by Uladzimir Pylinsky
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aka barthess.
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*/
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/**
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* @file fsmc_sram.c
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* @brief SRAM Driver subsystem low level driver source.
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*
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* @addtogroup SRAM
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* @{
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*/
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#include "hal.h"
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#include "fsmc_sram.h"
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#if STM32_USE_FSMC_SRAM || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief SRAM1 driver identifier.
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*/
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#if STM32_SRAM_USE_FSMC_SRAM1 || defined(__DOXYGEN__)
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SRAMDriver SRAMD1;
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#endif
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/**
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* @brief SRAM2 driver identifier.
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*/
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#if STM32_SRAM_USE_FSMC_SRAM2 || defined(__DOXYGEN__)
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SRAMDriver SRAMD2;
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#endif
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/**
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* @brief SRAM3 driver identifier.
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*/
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#if STM32_SRAM_USE_FSMC_SRAM3 || defined(__DOXYGEN__)
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SRAMDriver SRAMD3;
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#endif
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/**
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* @brief SRAM4 driver identifier.
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*/
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#if STM32_SRAM_USE_FSMC_SRAM4 || defined(__DOXYGEN__)
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SRAMDriver SRAMD4;
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#endif
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/*===========================================================================*/
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/* Driver local types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level SRAM driver initialization.
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*
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* @notapi
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*/
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void fsmc_sram_init(void) {
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fsmc_init();
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#if STM32_SRAM_USE_FSMC_SRAM1
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SRAMD1.sram = FSMCD1.sram1;
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SRAMD1.state = SRAM_STOP;
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#endif /* STM32_SRAM_USE_FSMC_SRAM1 */
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#if STM32_SRAM_USE_FSMC_SRAM2
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SRAMD2.sram = FSMCD1.sram2;
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SRAMD2.state = SRAM_STOP;
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#endif /* STM32_SRAM_USE_FSMC_SRAM2 */
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#if STM32_SRAM_USE_FSMC_SRAM3
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SRAMD3.sram = FSMCD1.sram3;
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SRAMD3.state = SRAM_STOP;
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#endif /* STM32_SRAM_USE_FSMC_SRAM3 */
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#if STM32_SRAM_USE_FSMC_SRAM4
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SRAMD4.sram = FSMCD1.sram4;
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SRAMD4.state = SRAM_STOP;
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#endif /* STM32_SRAM_USE_FSMC_SRAM4 */
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}
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/**
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* @brief Configures and activates the SRAM peripheral.
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*
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* @param[in] sramp pointer to the @p SRAMDriver object
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* @param[in] cfgp pointer to the @p SRAMConfig object
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*
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* @notapi
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*/
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void fsmc_sram_start(SRAMDriver *sramp, const SRAMConfig *cfgp) {
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if (FSMCD1.state == FSMC_STOP)
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fsmc_start(&FSMCD1);
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osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY),
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"invalid state");
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if (sramp->state == SRAM_STOP) {
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sramp->sram->BCR = FSMC_BCR_WREN | FSMC_BCR_MBKEN | FSMC_BCR_MWID_0;
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sramp->sram->BTR = cfgp->btr;
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sramp->state = SRAM_READY;
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}
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}
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/**
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* @brief Deactivates the SRAM peripheral.
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*
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* @param[in] sramp pointer to the @p SRAMDriver object
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*
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* @notapi
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*/
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void fsmc_sram_stop(SRAMDriver *sramp) {
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if (sramp->state == SRAM_READY) {
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sramp->sram->BCR &= ~FSMC_BCR_MBKEN;
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sramp->state = SRAM_STOP;
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}
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}
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#endif /* STM32_USE_FSMC_SRAM */
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/** @} */
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@ -0,0 +1,173 @@
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/*
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ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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Concepts and parts of this file have been contributed by Uladzimir Pylinsky
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aka barthess.
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*/
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/**
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* @file fsmc_sram.h
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* @brief SRAM Driver subsystem low level driver header.
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*
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* @addtogroup SRAM
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* @{
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*/
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#ifndef _FSMC_SRAM_H_
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#define _FSMC_SRAM_H_
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#include "fsmc.h"
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#if STM32_USE_FSMC_SRAM || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief SRAM driver enable switch.
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* @details If set to @p TRUE the support for SRAM1 is included.
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*/
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#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__)
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#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
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#endif
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/**
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* @brief SRAM driver enable switch.
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* @details If set to @p TRUE the support for SRAM2 is included.
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*/
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#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__)
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#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
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#endif
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/**
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* @brief SRAM driver enable switch.
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* @details If set to @p TRUE the support for SRAM3 is included.
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*/
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#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__)
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#define STM32_SRAM_USE_FSMC_SRAM3 FALSE
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#endif
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/**
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* @brief SRAM driver enable switch.
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* @details If set to @p TRUE the support for SRAM4 is included.
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*/
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#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__)
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#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \
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!STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4
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#error "SRAM driver activated but no SRAM peripheral assigned"
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#endif
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#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \
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STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC
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#error "FSMC not present in the selected device"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Driver state machine possible states.
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*/
|
||||
typedef enum {
|
||||
SRAM_UNINIT = 0, /**< Not initialized. */
|
||||
SRAM_STOP = 1, /**< Stopped. */
|
||||
SRAM_READY = 2, /**< Ready. */
|
||||
} sramstate_t;
|
||||
|
||||
/**
|
||||
* @brief Type of a structure representing an NAND driver.
|
||||
*/
|
||||
typedef struct SRAMDriver SRAMDriver;
|
||||
|
||||
/**
|
||||
* @brief Driver configuration structure.
|
||||
* @note It could be empty on some architectures.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t btr;
|
||||
} SRAMConfig;
|
||||
|
||||
/**
|
||||
* @brief Structure representing an NAND driver.
|
||||
*/
|
||||
struct SRAMDriver {
|
||||
/**
|
||||
* @brief Driver state.
|
||||
*/
|
||||
sramstate_t state;
|
||||
/**
|
||||
* @brief Pointer to the FSMC SRAM registers block.
|
||||
*/
|
||||
FSMC_SRAM_NOR_TypeDef *sram;
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__)
|
||||
extern SRAMDriver SRAMD1;
|
||||
#endif
|
||||
|
||||
#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__)
|
||||
extern SRAMDriver SRAMD2;
|
||||
#endif
|
||||
|
||||
#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__)
|
||||
extern SRAMDriver SRAMD3;
|
||||
#endif
|
||||
|
||||
#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__)
|
||||
extern SRAMDriver SRAMD4;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void fsmc_sram_init(void);
|
||||
void fsmc_sram_start(SRAMDriver *sramp, const SRAMConfig *cfgp);
|
||||
void fsmc_sram_stop(SRAMDriver *sramp);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32_USE_FSMC_SRAM */
|
||||
|
||||
#endif /* _FSMC_SRAM_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -22,7 +22,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
|
|||
${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c \
|
||||
${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c \
|
||||
${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c \
|
||||
${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c
|
||||
${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c \
|
||||
${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c
|
||||
|
||||
# Required include directories
|
||||
PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
|
||||
|
|
|
|||
Loading…
Reference in New Issue