[FSMC SRAM] Added driver code.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7195 35acf78f-673a-0410-8e92-d51de3d6d3f4master
barthess
parent
d12b4ee252
commit
4c53f50dd3
|
|
@ -25,10 +25,10 @@
|
||||||
* @addtogroup FSMC
|
* @addtogroup FSMC
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "hal.h"
|
#include "hal.h"
|
||||||
|
#include "fsmc.h"
|
||||||
|
|
||||||
#if HAL_USE_NAND || defined(__DOXYGEN__)
|
#if HAL_USE_NAND || STM32_USE_FSMC_SRAM || defined(__DOXYGEN__)
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver local definitions. */
|
/* Driver local definitions. */
|
||||||
|
|
@ -72,19 +72,37 @@ FSMCDriver FSMCD1;
|
||||||
*/
|
*/
|
||||||
void fsmc_init(void) {
|
void fsmc_init(void) {
|
||||||
|
|
||||||
FSMCD1.state = FSMC_STOP;
|
if (FSMCD1.state == FSMC_UNINIT) {
|
||||||
|
FSMCD1.state = FSMC_STOP;
|
||||||
|
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM1
|
||||||
|
FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM2
|
||||||
|
FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM3
|
||||||
|
FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM4
|
||||||
|
FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3);
|
||||||
|
#endif
|
||||||
|
|
||||||
#if STM32_NAND_USE_FSMC_NAND1
|
#if STM32_NAND_USE_FSMC_NAND1
|
||||||
FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE;
|
FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_NAND_USE_FSMC_NAND2
|
#if STM32_NAND_USE_FSMC_NAND2
|
||||||
FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE;
|
FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_USE_FSMC_PCCARD
|
#if STM32_USE_FSMC_PCCARD
|
||||||
FSMCD1.pccard = (FSMC_PCCARD_TypeDef *)FSMC_Bank4_R_BASE;
|
FSMCD1.pccard = (FSMC_PCCARD_TypeDef *)FSMC_Bank4_R_BASE;
|
||||||
#endif
|
#endif
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -96,7 +114,6 @@ void fsmc_init(void) {
|
||||||
*/
|
*/
|
||||||
void fsmc_start(FSMCDriver *fsmcp) {
|
void fsmc_start(FSMCDriver *fsmcp) {
|
||||||
|
|
||||||
|
|
||||||
osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY),
|
osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY),
|
||||||
"invalid state");
|
"invalid state");
|
||||||
|
|
||||||
|
|
@ -106,7 +123,7 @@ void fsmc_start(FSMCDriver *fsmcp) {
|
||||||
if (&FSMCD1 == fsmcp) {
|
if (&FSMCD1 == fsmcp) {
|
||||||
rccResetFSMC();
|
rccResetFSMC();
|
||||||
rccEnableFSMC(FALSE);
|
rccEnableFSMC(FALSE);
|
||||||
#if !STM32_NAND_USE_EXT_INT
|
#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND)
|
||||||
nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY);
|
nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
@ -132,7 +149,7 @@ void fsmc_stop(FSMCDriver *fsmcp) {
|
||||||
/* Disables the peripheral.*/
|
/* Disables the peripheral.*/
|
||||||
#if STM32_FSMC_USE_FSMC1
|
#if STM32_FSMC_USE_FSMC1
|
||||||
if (&FSMCD1 == fsmcp) {
|
if (&FSMCD1 == fsmcp) {
|
||||||
#if !STM32_NAND_USE_EXT_INT
|
#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND)
|
||||||
nvicDisableVector(STM32_FSMC_NUMBER);
|
nvicDisableVector(STM32_FSMC_NUMBER);
|
||||||
#endif
|
#endif
|
||||||
rccDisableFSMC(FALSE);
|
rccDisableFSMC(FALSE);
|
||||||
|
|
@ -166,6 +183,6 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) {
|
||||||
}
|
}
|
||||||
#endif /* !STM32_NAND_USE_EXT_INT */
|
#endif /* !STM32_NAND_USE_EXT_INT */
|
||||||
|
|
||||||
#endif /* HAL_USE_FSMC */
|
#endif /* HAL_USE_FSMC || STM32_USE_FSMC_SRAM */
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
|
||||||
|
|
@ -20,17 +20,16 @@
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @file fsmc.h
|
* @file fsmc.h
|
||||||
* @brief FSMC Driver subsystem low level driver header template.
|
* @brief FSMC Driver subsystem low level driver header.
|
||||||
*
|
*
|
||||||
* @addtogroup FSMC
|
* @addtogroup FSMC
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#ifndef _FSMC_H_
|
#ifndef _FSMC_H_
|
||||||
#define _FSMC_H_
|
#define _FSMC_H_
|
||||||
|
|
||||||
#if HAL_USE_NAND || defined(__DOXYGEN__)
|
#if HAL_USE_NAND || STM32_USE_FSMC_SRAM || defined(__DOXYGEN__)
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver constants. */
|
/* Driver constants. */
|
||||||
|
|
@ -44,6 +43,15 @@
|
||||||
#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000)
|
#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000)
|
||||||
#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000)
|
#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Subbunks of bank1
|
||||||
|
*/
|
||||||
|
#define FSMC_SUBBUNK_OFFSET (1024 * 1024 * 64)
|
||||||
|
#define FSMC_Bank1_1_MAP (FSMC_Bank1_MAP_BASE)
|
||||||
|
#define FSMC_Bank1_2_MAP (FSMC_Bank1_1_MAP + FSMC_SUBBUNK_OFFSET)
|
||||||
|
#define FSMC_Bank1_3_MAP (FSMC_Bank1_2_MAP + FSMC_SUBBUNK_OFFSET)
|
||||||
|
#define FSMC_Bank1_4_MAP (FSMC_Bank1_3_MAP + FSMC_SUBBUNK_OFFSET)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Bank 2 (NAND)
|
* Bank 2 (NAND)
|
||||||
*/
|
*/
|
||||||
|
|
@ -99,6 +107,13 @@ typedef struct {
|
||||||
__IO uint32_t PIO; /**< PC Card I/O space timing */
|
__IO uint32_t PIO; /**< PC Card I/O space timing */
|
||||||
} FSMC_PCCard_TypeDef;
|
} FSMC_PCCard_TypeDef;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
__IO uint32_t BCR; /**< SRAM/NOR chip-select control registers */
|
||||||
|
__IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */
|
||||||
|
uint32_t RESERVED[63]; /**< Reserved */
|
||||||
|
__IO uint32_t BWTR; /**< SRAM/NOR write timing registers */
|
||||||
|
} FSMC_SRAM_NOR_TypeDef;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief PCR register
|
* @brief PCR register
|
||||||
*/
|
*/
|
||||||
|
|
@ -122,10 +137,11 @@ typedef struct {
|
||||||
#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS)
|
#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief RCR register
|
* @brief BCR register
|
||||||
*/
|
*/
|
||||||
#define FSMC_BCR_MBKEN ((uint32_t)0x00000001)
|
#define FSMC_BCR_MBKEN ((uint32_t)0x00000001)
|
||||||
#define FSMC_BCR_MUXEN ((uint32_t)0x00000002)
|
#define FSMC_BCR_MUXEN ((uint32_t)0x00000002)
|
||||||
|
#define FSMC_BCR_MWID_0 ((uint32_t)0x00000010)
|
||||||
#define FSMC_BCR_FACCEN ((uint32_t)0x00000040)
|
#define FSMC_BCR_FACCEN ((uint32_t)0x00000040)
|
||||||
#define FSMC_BCR_BURSTEN ((uint32_t)0x00000100)
|
#define FSMC_BCR_BURSTEN ((uint32_t)0x00000100)
|
||||||
#define FSMC_BCR_WAITPOL ((uint32_t)0x00000200)
|
#define FSMC_BCR_WAITPOL ((uint32_t)0x00000200)
|
||||||
|
|
@ -189,14 +205,6 @@ typedef enum {
|
||||||
FSMC_READY = 2, /**< Ready. */
|
FSMC_READY = 2, /**< Ready. */
|
||||||
} fsmcstate_t;
|
} fsmcstate_t;
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Driver configuration structure.
|
|
||||||
* @note Empty on this architecture.
|
|
||||||
*/
|
|
||||||
typedef struct {
|
|
||||||
|
|
||||||
} FSMCConfig;
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Structure representing an FSMC driver.
|
* @brief Structure representing an FSMC driver.
|
||||||
*/
|
*/
|
||||||
|
|
@ -206,6 +214,19 @@ struct FSMCDriver {
|
||||||
*/
|
*/
|
||||||
fsmcstate_t state;
|
fsmcstate_t state;
|
||||||
/* End of the mandatory fields.*/
|
/* End of the mandatory fields.*/
|
||||||
|
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM1
|
||||||
|
FSMC_SRAM_NOR_TypeDef *sram1;
|
||||||
|
#endif
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM2
|
||||||
|
FSMC_SRAM_NOR_TypeDef *sram2;
|
||||||
|
#endif
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM3
|
||||||
|
FSMC_SRAM_NOR_TypeDef *sram3;
|
||||||
|
#endif
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM4
|
||||||
|
FSMC_SRAM_NOR_TypeDef *sram4;
|
||||||
|
#endif
|
||||||
#if STM32_NAND_USE_FSMC_NAND1
|
#if STM32_NAND_USE_FSMC_NAND1
|
||||||
FSMC_NAND_TypeDef *nand1;
|
FSMC_NAND_TypeDef *nand1;
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -239,7 +260,7 @@ extern "C" {
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* HAL_USE_NAND */
|
#endif /* HAL_USE_NAND || STM32_USE_FSMC_SRAM */
|
||||||
|
|
||||||
#endif /* _FSMC_H_ */
|
#endif /* _FSMC_H_ */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,159 @@
|
||||||
|
/*
|
||||||
|
ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
Concepts and parts of this file have been contributed by Uladzimir Pylinsky
|
||||||
|
aka barthess.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file fsmc_sram.c
|
||||||
|
* @brief SRAM Driver subsystem low level driver source.
|
||||||
|
*
|
||||||
|
* @addtogroup SRAM
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#include "hal.h"
|
||||||
|
#include "fsmc_sram.h"
|
||||||
|
|
||||||
|
#if STM32_USE_FSMC_SRAM || defined(__DOXYGEN__)
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver local definitions. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver exported variables. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
/**
|
||||||
|
* @brief SRAM1 driver identifier.
|
||||||
|
*/
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM1 || defined(__DOXYGEN__)
|
||||||
|
SRAMDriver SRAMD1;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SRAM2 driver identifier.
|
||||||
|
*/
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM2 || defined(__DOXYGEN__)
|
||||||
|
SRAMDriver SRAMD2;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SRAM3 driver identifier.
|
||||||
|
*/
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM3 || defined(__DOXYGEN__)
|
||||||
|
SRAMDriver SRAMD3;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SRAM4 driver identifier.
|
||||||
|
*/
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM4 || defined(__DOXYGEN__)
|
||||||
|
SRAMDriver SRAMD4;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver local types. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver local variables and types. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver local functions. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver interrupt handlers. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver exported functions. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Low level SRAM driver initialization.
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
void fsmc_sram_init(void) {
|
||||||
|
|
||||||
|
fsmc_init();
|
||||||
|
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM1
|
||||||
|
SRAMD1.sram = FSMCD1.sram1;
|
||||||
|
SRAMD1.state = SRAM_STOP;
|
||||||
|
#endif /* STM32_SRAM_USE_FSMC_SRAM1 */
|
||||||
|
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM2
|
||||||
|
SRAMD2.sram = FSMCD1.sram2;
|
||||||
|
SRAMD2.state = SRAM_STOP;
|
||||||
|
#endif /* STM32_SRAM_USE_FSMC_SRAM2 */
|
||||||
|
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM3
|
||||||
|
SRAMD3.sram = FSMCD1.sram3;
|
||||||
|
SRAMD3.state = SRAM_STOP;
|
||||||
|
#endif /* STM32_SRAM_USE_FSMC_SRAM3 */
|
||||||
|
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM4
|
||||||
|
SRAMD4.sram = FSMCD1.sram4;
|
||||||
|
SRAMD4.state = SRAM_STOP;
|
||||||
|
#endif /* STM32_SRAM_USE_FSMC_SRAM4 */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures and activates the SRAM peripheral.
|
||||||
|
*
|
||||||
|
* @param[in] sramp pointer to the @p SRAMDriver object
|
||||||
|
* @param[in] cfgp pointer to the @p SRAMConfig object
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
void fsmc_sram_start(SRAMDriver *sramp, const SRAMConfig *cfgp) {
|
||||||
|
|
||||||
|
if (FSMCD1.state == FSMC_STOP)
|
||||||
|
fsmc_start(&FSMCD1);
|
||||||
|
|
||||||
|
osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY),
|
||||||
|
"invalid state");
|
||||||
|
|
||||||
|
if (sramp->state == SRAM_STOP) {
|
||||||
|
sramp->sram->BCR = FSMC_BCR_WREN | FSMC_BCR_MBKEN | FSMC_BCR_MWID_0;
|
||||||
|
sramp->sram->BTR = cfgp->btr;
|
||||||
|
sramp->state = SRAM_READY;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deactivates the SRAM peripheral.
|
||||||
|
*
|
||||||
|
* @param[in] sramp pointer to the @p SRAMDriver object
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
void fsmc_sram_stop(SRAMDriver *sramp) {
|
||||||
|
|
||||||
|
if (sramp->state == SRAM_READY) {
|
||||||
|
sramp->sram->BCR &= ~FSMC_BCR_MBKEN;
|
||||||
|
sramp->state = SRAM_STOP;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* STM32_USE_FSMC_SRAM */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
|
@ -0,0 +1,173 @@
|
||||||
|
/*
|
||||||
|
ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
Concepts and parts of this file have been contributed by Uladzimir Pylinsky
|
||||||
|
aka barthess.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file fsmc_sram.h
|
||||||
|
* @brief SRAM Driver subsystem low level driver header.
|
||||||
|
*
|
||||||
|
* @addtogroup SRAM
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _FSMC_SRAM_H_
|
||||||
|
#define _FSMC_SRAM_H_
|
||||||
|
|
||||||
|
#include "fsmc.h"
|
||||||
|
|
||||||
|
#if STM32_USE_FSMC_SRAM || defined(__DOXYGEN__)
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver constants. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver pre-compile time settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
/**
|
||||||
|
* @name Configuration options
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SRAM driver enable switch.
|
||||||
|
* @details If set to @p TRUE the support for SRAM1 is included.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SRAM driver enable switch.
|
||||||
|
* @details If set to @p TRUE the support for SRAM2 is included.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SRAM driver enable switch.
|
||||||
|
* @details If set to @p TRUE the support for SRAM3 is included.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_SRAM_USE_FSMC_SRAM3 FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SRAM driver enable switch.
|
||||||
|
* @details If set to @p TRUE the support for SRAM4 is included.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Derived constants and error checks. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \
|
||||||
|
!STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4
|
||||||
|
#error "SRAM driver activated but no SRAM peripheral assigned"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \
|
||||||
|
STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC
|
||||||
|
#error "FSMC not present in the selected device"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver data structures and types. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
/**
|
||||||
|
* @brief Driver state machine possible states.
|
||||||
|
*/
|
||||||
|
typedef enum {
|
||||||
|
SRAM_UNINIT = 0, /**< Not initialized. */
|
||||||
|
SRAM_STOP = 1, /**< Stopped. */
|
||||||
|
SRAM_READY = 2, /**< Ready. */
|
||||||
|
} sramstate_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Type of a structure representing an NAND driver.
|
||||||
|
*/
|
||||||
|
typedef struct SRAMDriver SRAMDriver;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Driver configuration structure.
|
||||||
|
* @note It could be empty on some architectures.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t btr;
|
||||||
|
} SRAMConfig;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Structure representing an NAND driver.
|
||||||
|
*/
|
||||||
|
struct SRAMDriver {
|
||||||
|
/**
|
||||||
|
* @brief Driver state.
|
||||||
|
*/
|
||||||
|
sramstate_t state;
|
||||||
|
/**
|
||||||
|
* @brief Pointer to the FSMC SRAM registers block.
|
||||||
|
*/
|
||||||
|
FSMC_SRAM_NOR_TypeDef *sram;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver macros. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* External declarations. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__)
|
||||||
|
extern SRAMDriver SRAMD1;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__)
|
||||||
|
extern SRAMDriver SRAMD2;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__)
|
||||||
|
extern SRAMDriver SRAMD3;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__)
|
||||||
|
extern SRAMDriver SRAMD4;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
void fsmc_sram_init(void);
|
||||||
|
void fsmc_sram_start(SRAMDriver *sramp, const SRAMConfig *cfgp);
|
||||||
|
void fsmc_sram_stop(SRAMDriver *sramp);
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* STM32_USE_FSMC_SRAM */
|
||||||
|
|
||||||
|
#endif /* _FSMC_SRAM_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -22,7 +22,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
|
||||||
${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c \
|
${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c \
|
||||||
${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c \
|
${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c \
|
||||||
${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c \
|
${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c \
|
||||||
${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c
|
${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c \
|
||||||
|
${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c
|
||||||
|
|
||||||
# Required include directories
|
# Required include directories
|
||||||
PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
|
PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue