I2C. Added DMA masks for other MCUs.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3565 35acf78f-673a-0410-8e92-d51de3d6d3f4master
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@ -295,8 +295,22 @@
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_I2C1_RX_DMA_CHN 0x00000000
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_I2C1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_I2C2_RX_DMA_CHN 0x00000000
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#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_I2C2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C3 FALSE
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#define STM32_I2C3_RX_DMA_MSK 0
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#define STM32_I2C3_RX_DMA_CHN 0x00000000
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#define STM32_I2C3_TX_DMA_MSK 0
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#define STM32_I2C3_TX_DMA_CHN 0x00000000
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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@ -166,8 +166,22 @@
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_I2C1_RX_DMA_CHN 0x00000000
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_I2C1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_I2C2_RX_DMA_CHN 0x00000000
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#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_I2C2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C3 FALSE
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#define STM32_I2C3_RX_DMA_MSK 0
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#define STM32_I2C3_RX_DMA_CHN 0x00000000
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#define STM32_I2C3_TX_DMA_MSK 0
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#define STM32_I2C3_TX_DMA_CHN 0x00000000
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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@ -157,8 +157,27 @@
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#define STM32_HAS_GPIOH TRUE
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#define STM32_HAS_GPIOI TRUE
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 0) | \
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STM32_DMA_STREAM_ID_MSK(1, 5)))
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#define STM32_I2C1_RX_DMA_CHN 0x00100001
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#define STM32_I2C1_TX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 7)) | \
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(STM32_DMA_STREAM_ID_MSK(1, 6)))
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#define STM32_I2C1_TX_DMA_CHN 0x10000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 2) | \
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STM32_DMA_STREAM_ID_MSK(1, 3)))
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#define STM32_I2C2_RX_DMA_CHN 0x00007700
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#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_I2C2_TX_DMA_CHN 0x70000000
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#define STM32_HAS_I2C3 TRUE
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#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_I2C3_RX_DMA_CHN 0x00000300
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#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_I2C3_TX_DMA_CHN 0x00030000
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#define STM32_HAS_RTC TRUE
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@ -198,8 +198,22 @@
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_I2C1_RX_DMA_CHN 0x00000000
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_I2C1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_I2C2_RX_DMA_CHN 0x00000000
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#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_I2C2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C3 FALSE
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#define STM32_I2C3_RX_DMA_MSK 0
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#define STM32_I2C3_RX_DMA_CHN 0x00000000
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#define STM32_I2C3_TX_DMA_MSK 0
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#define STM32_I2C3_TX_DMA_CHN 0x00000000
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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