diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
index 3f5d9502b..96f5a7f33 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
@@ -295,8 +295,22 @@
 
 /* I2C attributes.*/
 #define STM32_HAS_I2C1          TRUE
+#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN   0x00000000
+#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN   0x00000000
+
 #define STM32_HAS_I2C2          TRUE
+#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C2_RX_DMA_CHN   0x00000000
+#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C2_TX_DMA_CHN   0x00000000
+
 #define STM32_HAS_I2C3          FALSE
+#define STM32_I2C3_RX_DMA_MSK   0
+#define STM32_I2C3_RX_DMA_CHN   0x00000000
+#define STM32_I2C3_TX_DMA_MSK   0
+#define STM32_I2C3_TX_DMA_CHN   0x00000000
 
 /* RTC attributes.*/
 #define STM32_HAS_RTC           TRUE
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
index 882ec6094..9a612b0ee 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
@@ -166,8 +166,22 @@
 
 /* I2C attributes.*/
 #define STM32_HAS_I2C1          TRUE
+#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN   0x00000000
+#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN   0x00000000
+
 #define STM32_HAS_I2C2          TRUE
+#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C2_RX_DMA_CHN   0x00000000
+#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C2_TX_DMA_CHN   0x00000000
+
 #define STM32_HAS_I2C3          FALSE
+#define STM32_I2C3_RX_DMA_MSK   0
+#define STM32_I2C3_RX_DMA_CHN   0x00000000
+#define STM32_I2C3_TX_DMA_MSK   0
+#define STM32_I2C3_TX_DMA_CHN   0x00000000
 
 /* RTC attributes.*/
 #define STM32_HAS_RTC           TRUE
diff --git a/os/hal/platforms/STM32F2xx/hal_lld.h b/os/hal/platforms/STM32F2xx/hal_lld.h
index 91135950f..cad926330 100644
--- a/os/hal/platforms/STM32F2xx/hal_lld.h
+++ b/os/hal/platforms/STM32F2xx/hal_lld.h
@@ -157,8 +157,27 @@
 #define STM32_HAS_GPIOH         TRUE
 #define STM32_HAS_GPIOI         TRUE
 
+/* I2C attributes.*/
 #define STM32_HAS_I2C1          TRUE
+#define STM32_I2C1_RX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 0) |             \
+                               STM32_DMA_STREAM_ID_MSK(1, 5)))
+#define STM32_I2C1_RX_DMA_CHN 0x00100001
+#define STM32_I2C1_TX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 7)) |            \
+                              (STM32_DMA_STREAM_ID_MSK(1, 6)))
+#define STM32_I2C1_TX_DMA_CHN 0x10000000
+
 #define STM32_HAS_I2C2          TRUE
+#define STM32_I2C2_RX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 2) |             \
+                               STM32_DMA_STREAM_ID_MSK(1, 3)))
+#define STM32_I2C2_RX_DMA_CHN 0x00007700
+#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C2_TX_DMA_CHN 0x70000000
+
+#define STM32_HAS_I2C3          TRUE
+#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C3_TX_DMA_CHN 0x00030000
 
 #define STM32_HAS_RTC           TRUE
 
diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h
index b25bad51d..8d6cfd6f0 100644
--- a/os/hal/platforms/STM32L1xx/hal_lld.h
+++ b/os/hal/platforms/STM32L1xx/hal_lld.h
@@ -198,8 +198,22 @@
 
 /* I2C attributes.*/
 #define STM32_HAS_I2C1          TRUE
+#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN   0x00000000
+#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN   0x00000000
+
 #define STM32_HAS_I2C2          TRUE
+#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C2_RX_DMA_CHN   0x00000000
+#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C2_TX_DMA_CHN   0x00000000
+
 #define STM32_HAS_I2C3          FALSE
+#define STM32_I2C3_RX_DMA_MSK   0
+#define STM32_I2C3_RX_DMA_CHN   0x00000000
+#define STM32_I2C3_TX_DMA_MSK   0
+#define STM32_I2C3_TX_DMA_CHN   0x00000000
 
 /* RTC attributes.*/
 #define STM32_HAS_RTC           TRUE