git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5119 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
parent
bd4e2c6c64
commit
46cc8ccb2b
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@ -116,8 +116,7 @@
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mtspr 319, %r31
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/* HW configuration.*/
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bl _hwconf
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bl _ivorinit
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bl _coreinit
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b _boot_address
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@ -19,8 +19,8 @@
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*/
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/**
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* @file SPC56ELxx/hwconf.s
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* @brief SPC56ELxx low level hardware configuration.
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* @file SPC56ELxx/core.s
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* @brief e200z4 core configuration.
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*
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* @addtogroup PPC_CORE
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* @{
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@ -153,85 +153,165 @@
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#if !defined(__DOXYGEN__)
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.section .handlers, "ax"
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/*
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* Unhandled exceptions handler.
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*/
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.weak _IVOR0
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_IVOR0:
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.weak _IVOR1
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_IVOR1:
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.weak _IVOR2
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_IVOR2:
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.weak _IVOR3
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_IVOR3:
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.weak _IVOR5
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_IVOR5:
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.weak _IVOR6
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_IVOR6:
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.weak _IVOR7
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_IVOR7:
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.weak _IVOR8
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_IVOR8:
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.weak _IVOR9
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_IVOR9:
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.weak _IVOR11
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_IVOR11:
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.weak _IVOR12
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_IVOR12:
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.weak _IVOR13
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_IVOR13:
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.weak _IVOR14
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_IVOR14:
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.weak _IVOR15
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_IVOR15:
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.weak _unhandled_exception
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.type _unhandled_exception, @function
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_unhandled_exception:
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b _unhandled_exception
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.section .coreinit, "ax"
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.align 2
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.globl _coreinit
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.type _coreinit, @function
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_coreinit:
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/* MSR settings.*/
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lis r3, MSR_DEFAULT@h
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ori r3, r3, MSR_DEFAULT@l
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mtMSR r3
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/* MSR initialization.*/
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lis %r3, MSR_DEFAULT@h
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ori %r3, %r3, MSR_DEFAULT@l
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mtMSR %r3
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/* TLB0 allocated to flash.*/
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lis r3, TLB0_MAS0@h
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mtspr 624, r3 /* MAS0 */
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lis r3, TLB0_MAS1@h
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ori r3, r3, TLB0_MAS1@l
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mtspr 625, r3 /* MAS1 */
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lis r3, TLB0_MAS2@h
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ori r3, r3, TLB0_MAS2@l
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mtspr 626, r3 /* MAS2 */
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lis r3, TLB0_MAS3@h
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ori r3, r3, TLB0_MAS3@l
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mtspr 627, r3 /* MAS3 */
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/*
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* IVPR initialization.
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*/
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lis %r3, __ivpr_base__@h
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ori %r3, %r3, __ivpr_base__@l
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mtIVPR %r3
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/*
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* IVORs initialization.
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*/
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lis %r3, _unhandled_exception@h
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ori %r3, %r3, _unhandled_exception@l
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mtspr 400, %r3 /* IVOR0-15 */
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mtspr 401, %r3
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mtspr 402, %r3
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mtspr 403, %r3
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mtspr 404, %r3
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mtspr 405, %r3
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mtspr 406, %r3
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mtspr 407, %r3
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mtspr 408, %r3
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mtspr 409, %r3
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mtspr 410, %r3
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mtspr 411, %r3
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mtspr 412, %r3
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mtspr 413, %r3
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mtspr 414, %r3
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mtspr 415, %r3
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mtspr 528, %r3 /* IVOR32-34 */
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mtspr 529, %r3
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mtspr 530, %r3
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/*
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* TLB0 allocated to flash.
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*/
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lis %r3, TLB0_MAS0@h
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mtspr 624, %r3 /* MAS0 */
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lis %r3, TLB0_MAS1@h
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ori %r3, %r3, TLB0_MAS1@l
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mtspr 625, %r3 /* MAS1 */
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lis %r3, TLB0_MAS2@h
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ori %r3, %r3, TLB0_MAS2@l
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mtspr 626, %r3 /* MAS2 */
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lis %r3, TLB0_MAS3@h
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ori %r3, %r3, TLB0_MAS3@l
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mtspr 627, %r3 /* MAS3 */
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tlbwe
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/* TLB1 allocated to external RAM, if any.*/
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lis r3, TLB1_MAS0@h
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mtspr 624, r3 /* MAS0 */
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lis r3, TLB1_MAS1@h
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ori r3, r3, TLB1_MAS1@l
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mtspr 625, r3 /* MAS1 */
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lis r3, TLB1_MAS2@h
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ori r3, r3, TLB1_MAS2@l
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mtspr 626, r3 /* MAS2 */
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lis r3, TLB1_MAS3@h
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ori r3, r3, TLB1_MAS3@l
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mtspr 627, r3 /* MAS3 */
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/*
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* TLB1 allocated to external RAM, if any.
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*/
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lis %r3, TLB1_MAS0@h
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mtspr 624, %r3 /* MAS0 */
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lis %r3, TLB1_MAS1@h
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ori %r3, %r3, TLB1_MAS1@l
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mtspr 625, %r3 /* MAS1 */
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lis %r3, TLB1_MAS2@h
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ori %r3, %r3, TLB1_MAS2@l
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mtspr 626, %r3 /* MAS2 */
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lis %r3, TLB1_MAS3@h
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ori %r3, %r3, TLB1_MAS3@l
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mtspr 627, %r3 /* MAS3 */
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tlbwe
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/* TLB2 allocated to internal RAM.*/
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lis r3, TLB2_MAS0@h
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mtspr 624, r3 /* MAS0 */
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lis r3, TLB2_MAS1@h
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ori r3, r3, TLB2_MAS1@l
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mtspr 625, r3 /* MAS1 */
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lis r3, TLB2_MAS2@h
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ori r3, r3, TLB2_MAS2@l
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mtspr 626, r3 /* MAS2 */
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lis r3, TLB2_MAS3@h
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ori r3, r3, TLB2_MAS3@l
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mtspr 627, r3 /* MAS3 */
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/*
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* TLB2 allocated to internal RAM.
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*/
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lis %r3, TLB2_MAS0@h
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mtspr 624, %r3 /* MAS0 */
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lis %r3, TLB2_MAS1@h
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ori %r3, %r3, TLB2_MAS1@l
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mtspr 625, %r3 /* MAS1 */
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lis %r3, TLB2_MAS2@h
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ori %r3, %r3, TLB2_MAS2@l
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mtspr 626, %r3 /* MAS2 */
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lis %r3, TLB2_MAS3@h
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ori %r3, %r3, TLB2_MAS3@l
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mtspr 627, %r3 /* MAS3 */
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tlbwe
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/* TLB3 allocated to internal Peripherals Bridge A.*/
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lis r3, TLB3_MAS0@h
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mtspr 624, r3 /* MAS0 */
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lis r3, TLB3_MAS1@h
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ori r3, r3, TLB3_MAS1@l
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mtspr 625, r3 /* MAS1 */
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lis r3, TLB3_MAS2@h
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ori r3, r3, TLB3_MAS2@l
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mtspr 626, r3 /* MAS2 */
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lis r3, TLB3_MAS3@h
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ori r3, r3, TLB3_MAS3@l
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mtspr 627, r3 /* MAS3 */
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/*
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* TLB3 allocated to internal Peripherals Bridge A.
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*/
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lis %r3, TLB3_MAS0@h
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mtspr 624, %r3 /* MAS0 */
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lis %r3, TLB3_MAS1@h
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ori %r3, %r3, TLB3_MAS1@l
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mtspr 625, %r3 /* MAS1 */
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lis %r3, TLB3_MAS2@h
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ori %r3, %r3, TLB3_MAS2@l
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mtspr 626, %r3 /* MAS2 */
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lis %r3, TLB3_MAS3@h
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ori %r3, %r3, TLB3_MAS3@l
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mtspr 627, %r3 /* MAS3 */
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tlbwe
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/* TLB4 allocated to internal Peripherals Bridge B.*/
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lis r3, TLB4_MAS0@h
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mtspr 624, r3 /* MAS0 */
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lis r3, TLB4_MAS1@h
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ori r3, r3, TLB4_MAS1@l
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mtspr 625, r3 /* MAS1 */
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lis r3, TLB4_MAS2@h
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ori r3, r3, TLB4_MAS2@l
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mtspr 626, r3 /* MAS2 */
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lis r3, TLB4_MAS3@h
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ori r3, r3, TLB4_MAS3@l
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mtspr 627, r3 /* MAS3 */
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/*
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* TLB4 allocated to internal Peripherals Bridge B.
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*/
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lis %r3, TLB4_MAS0@h
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mtspr 624, %r3 /* MAS0 */
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lis %r3, TLB4_MAS1@h
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ori %r3, %r3, TLB4_MAS1@l
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mtspr 625, %r3 /* MAS1 */
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lis %r3, TLB4_MAS2@h
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ori %r3, %r3, TLB4_MAS2@l
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mtspr 626, %r3 /* MAS2 */
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lis %r3, TLB4_MAS3@h
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ori %r3, %r3, TLB4_MAS3@l
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mtspr 627, %r3 /* MAS3 */
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tlbwe
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blr
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@ -1,121 +0,0 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file SPC56ELxx/ivor.s
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* @brief SPC56ELxx IVORx handlers.
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*
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* @addtogroup PPC_CORE
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* @{
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*/
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/*
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* Imports the PPC configuration headers.
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*/
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#define _FROM_ASM_
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#include "chconf.h"
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#include "chcore.h"
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#if !defined(__DOXYGEN__)
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/*
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* INTC registers address.
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*/
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.equ INTC_IACKR, 0xfff48010
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.equ INTC_EOIR, 0xfff48018
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.section .handlers, "ax"
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.align 2
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.globl _ivorinit
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.type _ivorinit, @function
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_ivorinit:
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/*
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* IVPR initialization.
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*/
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lis %r4, __ivpr_base__@h
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ori %r4, %r4, __ivpr_base__@l
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mtIVPR %r4
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/*
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* IVOR default settings.
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*/
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lis %r4, _unhandled_exception@h
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ori %r4, %r4, _unhandled_exception@l
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mtspr 400, %r4 /* IVOR0-15 */
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mtspr 401, %r4
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mtspr 402, %r4
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mtspr 403, %r4
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mtspr 404, %r4
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mtspr 405, %r4
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mtspr 406, %r4
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mtspr 407, %r4
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mtspr 408, %r4
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mtspr 409, %r4
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mtspr 410, %r4
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mtspr 411, %r4
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mtspr 412, %r4
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mtspr 413, %r4
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mtspr 414, %r4
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mtspr 415, %r4
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mtspr 528, %r4 /* IVOR32-34 */
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mtspr 529, %r4
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mtspr 530, %r4
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blr
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/*
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* Unhandled exceptions handler.
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*/
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.weak _IVOR0
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_IVOR0:
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.weak _IVOR1
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_IVOR1:
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.weak _IVOR2
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_IVOR2:
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.weak _IVOR3
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_IVOR3:
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.weak _IVOR5
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_IVOR5:
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.weak _IVOR6
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_IVOR6:
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.weak _IVOR7
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_IVOR7:
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.weak _IVOR8
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_IVOR8:
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.weak _IVOR9
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_IVOR9:
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.weak _IVOR11
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_IVOR11:
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.weak _IVOR12
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_IVOR12:
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.weak _IVOR13
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_IVOR13:
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.weak _IVOR14
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_IVOR14:
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.weak _IVOR15
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_IVOR15:
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.weak _unhandled_exception
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.type _unhandled_exception, @function
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_unhandled_exception:
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b _unhandled_exception
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#endif /* !defined(__DOXYGEN__) */
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/** @} */
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@ -48,7 +48,7 @@ SECTIONS
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{
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__ivpr_base__ = .;
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KEEP(*(.bam))
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KEEP(*(.hwconf))
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KEEP(*(.coreinit))
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KEEP(*(.crt0))
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KEEP(*(.handlers))
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. = ALIGN(0x800);
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@ -48,7 +48,7 @@ SECTIONS
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{
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__ivpr_base__ = .;
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KEEP(*(.bam))
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KEEP(*(.hwconf))
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KEEP(*(.coreinit))
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KEEP(*(.crt0))
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KEEP(*(.handlers))
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. = ALIGN(0x800);
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@ -48,7 +48,7 @@ SECTIONS
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{
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__ivpr_base__ = .;
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KEEP(*(.bam))
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KEEP(*(.hwconf))
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KEEP(*(.coreinit))
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KEEP(*(.crt0))
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KEEP(*(.handlers))
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. = ALIGN(0x800);
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@ -2,10 +2,9 @@
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PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c
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PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/bam.s \
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${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/hwconf.s \
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${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/ivor.s \
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${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/core.s \
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${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/vectors.s \
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${CHIBIOS}/os/ports/GCC/PPC/isr.s \
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${CHIBIOS}/os/ports/GCC/PPC/ivor.s \
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${CHIBIOS}/os/ports/GCC/PPC/crt0.s
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PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \
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Loading…
Reference in New Issue