git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6493 35acf78f-673a-0410-8e92-d51de3d6d3f4
parent
5a0d462a55
commit
449f7b1fa6
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@ -37,9 +37,9 @@ endif
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# Exceptions stack size
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ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
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LDOPT := $(LDOPT),--defsym=__main_stack_size__=0x400
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LDOPT := $(LDOPT),--defsym=__irq_stack_size__=0x400
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else
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LDOPT := $(LDOPT),--defsym=__main_stack_size__=$(USE_EXCEPTIONS_STACKSIZE)
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LDOPT := $(LDOPT),--defsym=__irq_stack_size__=$(USE_EXCEPTIONS_STACKSIZE)
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endif
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# Output directory and files
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@ -86,7 +86,7 @@ ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
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ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
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CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
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CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
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LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),--script=$(LDSCRIPT),$(LDOPT)
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LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),$(LDOPT),--script=$(LDSCRIPT)
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# Generate dependency information
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CFLAGS += -MD -MP -MF .dep/$(@F).d
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@ -29,8 +29,6 @@ SECTIONS
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. = ORIGIN(flash);
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.boot0 : ALIGN(16) SUBALIGN(16)
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{
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. += ${conf.instance.runtime_settings.load_address[0]?trim};
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. = ALIGN(0x10000);
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__ivpr_base__ = .;
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KEEP(*(.boot))
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} > flash
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@ -396,7 +396,7 @@ static inline void port_init(void) {
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* @return The interrupts status.
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*/
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static inline syssts_t port_get_irq_status(void) {
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register uint32_t sts;
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uint32_t sts;
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#if !CORTEX_SIMPLIFIED_PRIORITY
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sts = __get_BASEPRI();
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@ -28,34 +28,29 @@
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#include "ch.h"
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/**
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* @brief Kernel port layer initialization.
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* @details IVOR4 and IVOR10 initialization.
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*/
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void port_init(void) {
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#if PPC_SUPPORTS_IVORS
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/* The CPU supports IVOR registers, the kernel requires IVOR4 and IVOR10
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and the initialization is performed here.*/
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asm volatile ("li %%r3, _IVOR4@l \t\n"
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"mtIVOR4 %%r3 \t\n"
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"li %%r3, _IVOR10@l \t\n"
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"mtIVOR10 %%r3" : : : "memory");
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#endif
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}
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/*===========================================================================*/
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/* Module local definitions. */
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/*===========================================================================*/
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/**
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* @brief Halts the system.
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* @details This function is invoked by the operating system when an
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* unrecoverable error is detected (for example because a programming
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* error in the application code that triggers an assertion while
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* in debug mode).
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*/
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void port_halt(void) {
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/*===========================================================================*/
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/* Module exported variables. */
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/*===========================================================================*/
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port_disable();
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while (TRUE) {
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}
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}
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/*===========================================================================*/
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/* Module local types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module exported functions. */
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/*===========================================================================*/
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/**
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* @brief Performs a context switch between two threads.
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@ -65,9 +60,9 @@ void port_halt(void) {
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* switch performance so optimize here as much as you can.
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*/
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#if !defined(__DOXYGEN__)
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__attribute__((naked))
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__attribute__((naked, required))
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#endif
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void port_dummy1(void) {
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static void port_dummy1(void) {
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asm (".global _port_switch");
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asm ("_port_switch:");
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@ -96,9 +91,9 @@ void port_dummy1(void) {
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* invoked.
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*/
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#if !defined(__DOXYGEN__)
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__attribute__((naked))
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__attribute__((naked, required))
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#endif
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void port_dummy2(void) {
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static void port_dummy2(void) {
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asm (".global _port_thread_start");
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asm ("_port_thread_start:");
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@ -190,9 +190,9 @@ typedef void *regppc_t;
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/**
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* @brief Mandatory part of a stack frame.
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*/
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struct eabi_frame {
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regppc_t slink; /**< Stack back link. */
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regppc_t shole; /**< Stack hole for LR storage. */
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struct port_eabi_frame {
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uint32_t slink; /**< Stack back link. */
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uint32_t shole; /**< Stack hole for LR storage. */
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};
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/**
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* @note R2 and R13 are not saved because those are assumed to be immutable
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* during the system life cycle.
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*/
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struct extctx {
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struct eabi_frame frame;
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struct port_extctx {
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struct port_eabi_frame frame;
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/* Start of the e_stmvsrrw frame (offset 8).*/
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regppc_t pc;
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regppc_t msr;
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* @note LR is stored in the caller contex so it is not present in this
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* structure.
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*/
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struct intctx {
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struct port_intctx {
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regppc_t cr; /* Part of it is not volatile... */
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regppc_t r14;
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regppc_t r15;
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/**
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* @brief Platform dependent part of the @p Thread structure.
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* @details This structure usually contains just the saved stack pointer
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* defined as a pointer to a @p intctx structure.
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* defined as a pointer to a @p port_intctx structure.
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*/
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struct context {
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struct intctx *sp;
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struct port_intctx *sp;
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};
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#endif /* !defined(_FROM_ASM_) */
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@ -277,15 +277,15 @@ struct context {
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/**
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* @brief Platform dependent part of the @p chThdCreateI() API.
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* @details This code usually setup the context switching frame represented
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* by an @p intctx structure.
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* by an @p port_intctx structure.
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*/
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#define PORT_SETUP_CONTEXT(tp, workspace, wsize, pf, arg) { \
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uint8_t *sp = (uint8_t *)(workspace) + \
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(wsize) - \
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sizeof(struct eabi_frame); \
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((struct eabi_frame *)sp)->slink = 0; \
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((struct eabi_frame *)sp)->shole = _port_thread_start; \
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(tp)->p_ctx.sp = (struct intctx *)(sp - sizeof(struct intctx)); \
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sizeof(struct port_eabi_frame); \
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((struct port_eabi_frame *)sp)->slink = 0; \
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((struct port_eabi_frame *)sp)->shole = (uint32_t)_port_thread_start; \
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(tp)->p_ctx.sp = (struct port_intctx *)(sp - sizeof(struct port_intctx)); \
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(tp)->p_ctx.sp->r31 = (regppc_t)(arg); \
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(tp)->p_ctx.sp->r30 = (regppc_t)(pf); \
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}
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#define port_switch(ntp, otp) _port_switch(ntp, otp)
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#else
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#define port_switch(ntp, otp) { \
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register struct intctx *sp asm ("%r1"); \
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register struct port_intctx *sp asm ("%r1"); \
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if ((stkalign_t *)(sp - 1) < otp->p_stklimit) \
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chDbgPanic("stack overflow"); \
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_port_switch(ntp, otp); \
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#ifdef __cplusplus
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extern "C" {
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#endif
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void port_init(void);
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void _port_switch(thread_t *ntp, thread_t *otp);
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void _port_thread_start(void);
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#ifdef __cplusplus
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asm module.*/
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#if !defined(_FROM_ASM_)
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/**
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* @brief Kernel port layer initialization.
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* @details IVOR4 and IVOR10 initialization.
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*/
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static inline void port_init(void) {
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#if PPC_SUPPORTS_IVORS
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/* The CPU supports IVOR registers, the kernel requires IVOR4 and IVOR10
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and the initialization is performed here.*/
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asm volatile ("li %%r3, _IVOR4@l \t\n"
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"mtIVOR4 %%r3 \t\n"
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"li %%r3, _IVOR10@l \t\n"
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"mtIVOR10 %%r3" : : : "memory");
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#endif
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}
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/**
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* @brief Returns a word encoding the current interrupts status.
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*
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* @return The interrupts status.
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*/
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static inline syssts_t port_get_irq_status(void) {
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uint32_t sts;
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sts = 0;
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return sts;
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}
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/**
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* @brief Checks the interrupt status.
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*
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* @param[in] sts the interrupt status word
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*
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* @return The interrupt status.
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* @retvel false the word specified a disabled interrupts status.
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* @retvel true the word specified an enabled interrupts status.
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*/
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static inline bool port_irq_enabled(syssts_t sts) {
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return (sts & 1) == 0;
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}
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/**
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* @brief Determines the current execution context.
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*
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* @return The execution context.
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* @retval false not running in ISR mode.
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* @retval true running in ISR mode.
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*/
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static inline bool port_is_isr_context(void) {
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// return (bool)((__get_IPSR() & 0x1FF) != 0);
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return false;
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}
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/**
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* @brief Kernel-lock action.
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* @note Implemented as global interrupt disable.
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