diff --git a/os/hal/platforms/STM32/I2Cv1/i2c_lld.c b/os/hal/platforms/STM32/I2Cv1/i2c_lld.c
index 9d6fff03c..120368ea4 100644
--- a/os/hal/platforms/STM32/I2Cv1/i2c_lld.c
+++ b/os/hal/platforms/STM32/I2Cv1/i2c_lld.c
@@ -575,9 +575,14 @@ void i2c_lld_init(void) {
 void i2c_lld_start(I2CDriver *i2cp) {
   I2C_TypeDef *dp = i2cp->i2c;
 
-  i2cp->dmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
-                  STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
-                  STM32_DMA_CR_TCIE;
+  i2cp->txdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
+                    STM32_DMA_CR_MINC       | STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE       | STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DIR_M2P;
+  i2cp->rxdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
+                    STM32_DMA_CR_MINC       | STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE       | STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DIR_P2M;
 
   /* If in stopped state then enables the I2C and DMA clocks.*/
   if (i2cp->state == I2C_STOP) {
@@ -603,7 +608,9 @@ void i2c_lld_start(I2CDriver *i2cp) {
       nvicEnableVector(I2C1_ER_IRQn,
           CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
 
-      i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
+      i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
+                       STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
+      i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) |
                        STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
     }
 #endif /* STM32_I2C_USE_I2C1 */
@@ -629,7 +636,9 @@ void i2c_lld_start(I2CDriver *i2cp) {
       nvicEnableVector(I2C2_ER_IRQn,
           CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
 
-      i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
+      i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
+                       STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
+      i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) |
                        STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
     }
 #endif /* STM32_I2C_USE_I2C2 */
@@ -655,16 +664,14 @@ void i2c_lld_start(I2CDriver *i2cp) {
       nvicEnableVector(I2C3_ER_IRQn,
           CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY));
 
-      i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) |
+      i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) |
+                       STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY);
+      i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C3_TX_DMA_CHANNEL) |
                        STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY);
     }
 #endif /* STM32_I2C_USE_I2C3 */
   }
 
-  /* DMA streams mode preparation in advance.*/
-  dmaStreamSetMode(i2cp->dmatx, i2cp->dmamode | STM32_DMA_CR_DIR_M2P);
-  dmaStreamSetMode(i2cp->dmarx, i2cp->dmamode | STM32_DMA_CR_DIR_P2M);
-
   /* I2C registers pointed by the DMA.*/
   dmaStreamSetPeripheral(i2cp->dmarx, &dp->DR);
   dmaStreamSetPeripheral(i2cp->dmatx, &dp->DR);
@@ -770,6 +777,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
   i2cp->errors = 0;
 
   /* RX DMA setup.*/
+  dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
   dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
   dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
 
@@ -852,10 +860,12 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
   i2cp->errors = 0;
 
   /* TX DMA setup.*/
+  dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode);
   dmaStreamSetMemory0(i2cp->dmatx, txbuf);
   dmaStreamSetTransactionSize(i2cp->dmatx, txbytes);
 
   /* RX DMA setup.*/
+  dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
   dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
   dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
 
diff --git a/os/hal/platforms/STM32/I2Cv1/i2c_lld.h b/os/hal/platforms/STM32/I2Cv1/i2c_lld.h
index 116e67b78..0426cced4 100644
--- a/os/hal/platforms/STM32/I2Cv1/i2c_lld.h
+++ b/os/hal/platforms/STM32/I2Cv1/i2c_lld.h
@@ -391,9 +391,13 @@ struct I2CDriver {
    */
   i2caddr_t                 addr;
   /**
-   * @brief     DMA mode bit mask.
+   * @brief RX DMA mode bit mask.
    */
-  uint32_t                  dmamode;
+  uint32_t                  rxdmamode;
+  /**
+   * @brief TX DMA mode bit mask.
+   */
+  uint32_t                  txdmamode;
   /**
    * @brief     Receive DMA channel.
    */
diff --git a/readme.txt b/readme.txt
index 5d838de69..89f971f63 100644
--- a/readme.txt
+++ b/readme.txt
@@ -86,6 +86,7 @@
 *****************************************************************************
 
 *** 2.5.2 ***
+- FIX: Fixed fixed I2C malfunction after fixing bug 3607518 (bug 3607549)
 - FIX: Fixed spurious interrupt disabling an STM32 DMA stream (bug 3607518)
   (backported to 2.4.4).
 - FIX: Fixed start of any ADC disables VREF and VBAT (bug 3607467)