Fixed bug 3607549. I2C malfunction after fixing bug 3607518.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5408 35acf78f-673a-0410-8e92-d51de3d6d3f4master
parent
7f9f396a77
commit
444d818b22
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@ -575,9 +575,14 @@ void i2c_lld_init(void) {
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void i2c_lld_start(I2CDriver *i2cp) {
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I2C_TypeDef *dp = i2cp->i2c;
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i2cp->dmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
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STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
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STM32_DMA_CR_TCIE;
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i2cp->txdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
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STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DIR_M2P;
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i2cp->rxdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
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STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DIR_P2M;
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/* If in stopped state then enables the I2C and DMA clocks.*/
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if (i2cp->state == I2C_STOP) {
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@ -603,7 +608,9 @@ void i2c_lld_start(I2CDriver *i2cp) {
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nvicEnableVector(I2C1_ER_IRQn,
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CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
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i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
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i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
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i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
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}
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#endif /* STM32_I2C_USE_I2C1 */
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@ -629,7 +636,9 @@ void i2c_lld_start(I2CDriver *i2cp) {
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nvicEnableVector(I2C2_ER_IRQn,
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CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
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i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
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i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
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i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
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}
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#endif /* STM32_I2C_USE_I2C2 */
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@ -655,16 +664,14 @@ void i2c_lld_start(I2CDriver *i2cp) {
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nvicEnableVector(I2C3_ER_IRQn,
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CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY));
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i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) |
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i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY);
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i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C3_TX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY);
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}
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#endif /* STM32_I2C_USE_I2C3 */
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}
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/* DMA streams mode preparation in advance.*/
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dmaStreamSetMode(i2cp->dmatx, i2cp->dmamode | STM32_DMA_CR_DIR_M2P);
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dmaStreamSetMode(i2cp->dmarx, i2cp->dmamode | STM32_DMA_CR_DIR_P2M);
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/* I2C registers pointed by the DMA.*/
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dmaStreamSetPeripheral(i2cp->dmarx, &dp->DR);
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dmaStreamSetPeripheral(i2cp->dmatx, &dp->DR);
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@ -770,6 +777,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
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i2cp->errors = 0;
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/* RX DMA setup.*/
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dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
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dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
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dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
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@ -852,10 +860,12 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
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i2cp->errors = 0;
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/* TX DMA setup.*/
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dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode);
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dmaStreamSetMemory0(i2cp->dmatx, txbuf);
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dmaStreamSetTransactionSize(i2cp->dmatx, txbytes);
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/* RX DMA setup.*/
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dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
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dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
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dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
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@ -391,9 +391,13 @@ struct I2CDriver {
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*/
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i2caddr_t addr;
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/**
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* @brief DMA mode bit mask.
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* @brief RX DMA mode bit mask.
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*/
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uint32_t dmamode;
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uint32_t rxdmamode;
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/**
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* @brief TX DMA mode bit mask.
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*/
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uint32_t txdmamode;
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/**
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* @brief Receive DMA channel.
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*/
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@ -86,6 +86,7 @@
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*****************************************************************************
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*** 2.5.2 ***
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- FIX: Fixed fixed I2C malfunction after fixing bug 3607518 (bug 3607549)
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- FIX: Fixed spurious interrupt disabling an STM32 DMA stream (bug 3607518)
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(backported to 2.4.4).
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- FIX: Fixed start of any ADC disables VREF and VBAT (bug 3607467)
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