I2C. Examples update.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3051 35acf78f-673a-0410-8e92-d51de3d6d3f4master
barthess
parent
5cad241306
commit
4044f7d308
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@ -78,8 +78,8 @@ CSRC = $(PORTSRC) \
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main.c \
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i2c_pns.c \
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lis3.c\
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tmp75.c\
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max1236.c\
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tmp75.c\
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# C++ sources that can be compiled in ARM or THUMB mode depending on the global
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# setting.
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@ -1,5 +1,6 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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@ -37,11 +38,32 @@ __ram_end__ = __ram_start__ + __ram_size__;
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SECTIONS
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{
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. = 0;
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_text = .;
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startup : ALIGN(16) SUBALIGN(16)
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{
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KEEP(*(vectors))
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} > flash
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constructors : ALIGN(4) SUBALIGN(4)
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{
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PROVIDE(__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE(__init_array_end = .);
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} > flash
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destructors : ALIGN(4) SUBALIGN(4)
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{
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PROVIDE(__fini_array_start = .);
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KEEP(*(.fini_array))
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KEEP(*(SORT(.fini_array.*)))
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PROVIDE(__fini_array_end = .);
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} > flash
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.text : ALIGN(16) SUBALIGN(16)
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{
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_text = .;
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KEEP(*(vectors))
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*(.text.startup.*)
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*(.text)
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*(.text.*)
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*(.rodata)
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@ -51,31 +73,26 @@ SECTIONS
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*(.gcc*)
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} > flash
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.ctors :
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.ARM.extab :
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{
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PROVIDE(_ctors_start_ = .);
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KEEP(*(SORT(.ctors.*)))
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KEEP(*(.ctors))
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PROVIDE(_ctors_end_ = .);
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > flash
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.dtors :
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.ARM.exidx : {
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PROVIDE(__exidx_start = .);
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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PROVIDE(__exidx_end = .);
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} > flash
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.eh_frame_hdr :
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{
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PROVIDE(_dtors_start_ = .);
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KEEP(*(SORT(.dtors.*)))
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KEEP(*(.dtors))
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PROVIDE(_dtors_end_ = .);
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*(.eh_frame_hdr)
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} > flash
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.ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)}
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__exidx_start = .;
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.ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash
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__exidx_end = .;
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.eh_frame_hdr : {*(.eh_frame_hdr)}
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.eh_frame : ONLY_IF_RO {*(.eh_frame)}
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.eh_frame : ONLY_IF_RO
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{
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*(.eh_frame)
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} > flash
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. = ALIGN(4);
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_etext = .;
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@ -83,26 +100,26 @@ SECTIONS
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.data :
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{
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_data = .;
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PROVIDE(_data = .);
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*(.data)
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. = ALIGN(4);
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*(.data.*)
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. = ALIGN(4);
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*(.ramtext)
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. = ALIGN(4);
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_edata = .;
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PROVIDE(_edata = .);
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} > ram AT > flash
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.bss :
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{
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_bss_start = .;
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PROVIDE(_bss_start = .);
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*(.bss)
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. = ALIGN(4);
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*(.bss.*)
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. = ALIGN(4);
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*(COMMON)
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. = ALIGN(4);
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_bss_end = .;
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PROVIDE(_bss_end = .);
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} > ram
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}
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@ -89,6 +89,23 @@
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#define CH_MEMCORE_SIZE 0
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#endif
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/**
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* @brief Idle thread automatic spawn suppression.
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* @details When this option is activated the function @p chSysInit()
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* does not spawn the idle thread automatically. The application has
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* then the responsibility to do one of the following:
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* - Spawn a custom idle thread at priority @p IDLEPRIO.
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* - Change the main() thread priority to @p IDLEPRIO then enter
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* an endless loop. In this scenario the @p main() thread acts as
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* the idle thread.
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* .
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* @note Unless an idle thread is spawned the @p main() thread must not
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* enter a sleep state.
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*/
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#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
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#define CH_NO_IDLE_THREAD FALSE
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#endif
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/*===========================================================================*/
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/* Performance options. */
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/*===========================================================================*/
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@ -105,26 +122,6 @@
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#define CH_OPTIMIZE_SPEED FALSE
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#endif
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/**
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* @brief Exotic optimization.
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* @details If defined then a CPU register is used as storage for the global
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* @p currp variable. Caching this variable in a register greatly
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* improves both space and time OS efficiency. A side effect is that
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* one less register has to be saved during the context switch
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* resulting in lower RAM usage and faster context switch.
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*
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* @note This option is only usable with the GCC compiler and is only useful
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* on processors with many registers like ARM cores.
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* @note If this option is enabled then ALL the libraries linked to the
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* ChibiOS/RT code <b>must</b> be recompiled with the GCC option @p
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* -ffixed-@<reg@>.
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* @note This option must be enabled in the Makefile, it is listed here for
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* documentation only.
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*/
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#if defined(__DOXYGEN__)
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#define CH_CURRP_REGISTER_CACHE "reg"
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#endif
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/*===========================================================================*/
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/* Subsystem options. */
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/*===========================================================================*/
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@ -54,6 +54,13 @@
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#define HAL_USE_CAN FALSE
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#endif
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/**
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* @brief Enables the GPT subsystem.
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*/
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#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
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#define HAL_USE_GPT FALSE
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#endif
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/**
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* @brief Enables the I2C subsystem.
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*/
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@ -61,6 +68,13 @@
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#define HAL_USE_I2C TRUE
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#endif
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/**
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* @brief Enables the ICU subsystem.
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*/
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#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
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#define HAL_USE_ICU FALSE
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#endif
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/**
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* @brief Enables the MAC subsystem.
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*/
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@ -82,11 +96,25 @@
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#define HAL_USE_PWM TRUE
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#endif
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/**
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* @brief Enables the SDC subsystem.
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*/
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#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
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#define HAL_USE_SDC FALSE
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#endif
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/**
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* @brief Enables the SERIAL subsystem.
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*/
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#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
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#define HAL_USE_SERIAL FALSE
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#define HAL_USE_SERIAL TRUE
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#endif
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/**
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* @brief Enables the SERIAL over USB subsystem.
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*/
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#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
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#define HAL_USE_SERIAL_USB FALSE
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#endif
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/**
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@ -100,7 +128,14 @@
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* @brief Enables the UART subsystem.
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*/
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#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
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#define HAL_USE_UART TRUE
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#define HAL_USE_UART FALSE
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#endif
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/**
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* @brief Enables the USB subsystem.
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*/
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#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
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#define HAL_USE_USB FALSE
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#endif
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/*===========================================================================*/
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@ -206,6 +241,36 @@
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/* PWM driver related settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* SDC driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Number of initialization attempts before rejecting the card.
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* @note Attempts are performed at 10mS intevals.
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*/
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#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
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#define SDC_INIT_RETRY 100
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#endif
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/**
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* @brief Include support for MMC cards.
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* @note MMC support is not yet implemented so this option must be kept
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* at @p FALSE.
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*/
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#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
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#define SDC_MMC_SUPPORT FALSE
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#endif
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/**
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* @brief Delays insertions.
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* @details If enabled this options inserts delays into the MMC waiting
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* routines releasing some extra CPU time for the threads with
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* lower priority, this may slow down the driver a bit however.
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*/
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#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
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#define SDC_NICE_WAITING TRUE
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#endif
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/*===========================================================================*/
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/* SERIAL driver related settings. */
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/*===========================================================================*/
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@ -216,7 +281,7 @@
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* default configuration.
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*/
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#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
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#define SERIAL_DEFAULT_BITRATE 38400
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#define SERIAL_DEFAULT_BITRATE 57600
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#endif
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/**
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@ -227,7 +292,7 @@
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* buffers.
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*/
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#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
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#define SERIAL_BUFFERS_SIZE 16
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#define SERIAL_BUFFERS_SIZE 256
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#endif
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/*===========================================================================*/
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@ -30,19 +30,21 @@ static void i2c_lis3_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
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static I2CSlaveConfig lis3 = {
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NULL,
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i2c_lis3_error_cb,
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0,
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0,
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accel_rx_data,
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ACCEL_RX_DEPTH,
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0,
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0,
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accel_tx_data,
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ACCEL_TX_DEPTH,
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0,
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0,
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0b0011101,
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FALSE,
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7,
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0,
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0,
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{NULL},
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};
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/**
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* This treading need for convenient realize
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* "read through write" process.
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@ -82,26 +84,13 @@ static msg_t I2CAccelThread(void *arg) {
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/* This callback raise up when transfer finished */
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static void i2c_lis3_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
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(void) i2cscfg;
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if (i2cp->id_slave_config->restart){ // is it restart flag set to TRUE
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/* reset restart flag */
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i2cp->id_slave_config->restart = FALSE;
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/* now send restart and read acceleration data.
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* Function i2cMasterReceive() send restart implicitly. */
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i2cMasterReceive(i2cp, i2cscfg);
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}
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else{
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/* If jump here than requested data have been read.
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* Stop communication, release bus and wake up processing thread */
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i2cMasterStop(i2cp);
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i2cReleaseBus(&I2CD1);
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// wake up heavy thread for data processing
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if (i2c_accel_tp != NULL) {
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i2c_accel_tp->p_msg = (msg_t)i2cp;
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chSchReadyI(i2c_accel_tp);
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i2c_accel_tp = NULL;
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}
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// only wake up processing thread
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if (i2c_accel_tp != NULL) {
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i2c_accel_tp->p_msg = (msg_t)i2cp;
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chSchReadyI(i2c_accel_tp);
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i2c_accel_tp = NULL;
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}
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}
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@ -121,25 +110,19 @@ int init_lis3(void){
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while (i2c_accel_tp == NULL)
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chThdSleepMilliseconds(1);
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lis3.txbufhead = 0;
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lis3.rxbufhead = 0;
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lis3.rxbytes = 0; //set to 0 because we need only transmit
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/* Write configuration data */
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/* configure accelerometer */
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lis3.txbytes = 4;
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/* fill transmit buffer. See datasheet to understand what we write */
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lis3.txbuf[0] = ACCEL_CTRL_REG1 | AUTO_INCREMENT_BIT;
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lis3.txbuf[0] = ACCEL_CTRL_REG1 | AUTO_INCREMENT_BIT; // register address
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lis3.txbuf[1] = 0b11100111;
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lis3.txbuf[2] = 0b01000001;
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lis3.txbuf[3] = 0b00000000;
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/* setting callback */
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lis3.id_callback = i2c_lis3_cb;
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i2cAcquireBus(&I2CD1);
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/* sending */
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i2cMasterTransmit(&I2CD1, &lis3);
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chThdSleepMilliseconds(1);
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lis3.id_callback = i2c_lis3_cb;
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return 0;
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}
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@ -148,23 +131,11 @@ int init_lis3(void){
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*
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*/
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void request_acceleration_data(void){
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/* fill transmit buffer with address of register that we want to read */
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lis3.txbufhead = 0;
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lis3.txbuf[0] = ACCEL_OUT_DATA | AUTO_INCREMENT_BIT; // register address
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lis3.txbytes = 1;
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/* tune receive structures */
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lis3.rxbufhead = 0;
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lis3.rxbytes = 6;
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/* Now it is most important action. We must set restart flag to TRUE.
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* And in callback function we must reset it to FALSE after sending
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* of register address. In TMP75 and MAX1236 this flag does not use. */
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lis3.restart = TRUE;
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/* talk to slave what we want from it */
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i2cAcquireBus(&I2CD1);
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i2cMasterTransmit(&I2CD1, &lis3);
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i2cReleaseBus(&I2CD1);
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}
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@ -13,6 +13,9 @@
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// Data buffers
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static i2cblock_t max1236_rx_data[MAX1236_RX_DEPTH];
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static i2cblock_t max1236_tx_data[MAX1236_TX_DEPTH];
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// ADC results
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static uint16_t ch1 = 0, ch2 = 0, ch3 = 0, ch4 = 0;
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/* Error trap */
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static void i2c_max1236_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
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@ -25,17 +28,7 @@ static void i2c_max1236_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
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/* This callback raise up when transfer finished */
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static void i2c_max1236_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
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uint16_t ch1 = 0;
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uint16_t ch2 = 0;
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uint16_t ch3 = 0;
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uint16_t ch4 = 0;
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/* send stop */
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i2cMasterStop(i2cp);
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/* unlock bus */
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i2cReleaseBus(&I2CD2);
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(void)*i2cp;
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/* get ADC data */
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ch1 = ((i2cscfg->rxbuf[0] & 0xF) << 8) + i2cscfg->rxbuf[1];
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ch2 = ((i2cscfg->rxbuf[2] & 0xF) << 8) + i2cscfg->rxbuf[3];
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@ -45,19 +38,19 @@ static void i2c_max1236_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
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// ADC maxim MAX1236 config
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static I2CSlaveConfig max1236 = {
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NULL, // first set to NULL. We will set this pointer to the function later.
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i2c_max1236_error_cb,
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max1236_rx_data,
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MAX1236_RX_DEPTH,
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0,
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0,
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max1236_tx_data,
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MAX1236_TX_DEPTH,
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0,
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0,
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0b0110100,
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FALSE,
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NULL,
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i2c_max1236_error_cb,
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0,
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0,
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max1236_rx_data,
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max1236_tx_data,
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0b0110100,
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7,
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0,
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0,
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{NULL},
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};
|
||||
|
||||
|
||||
|
|
@ -66,41 +59,30 @@ static I2CSlaveConfig max1236 = {
|
|||
* how to initialize ADC.
|
||||
*/
|
||||
void init_max1236(void){
|
||||
/* lock bus */
|
||||
i2cAcquireBus(&I2CD2);
|
||||
|
||||
/* this data we must send to IC to setup ADC settings */
|
||||
max1236.txbufhead = 0;
|
||||
/* this data we must send via IC to setup ADC */
|
||||
max1236.rxbytes = 0;
|
||||
max1236.txbytes = 2; // total 2 bytes to be sent
|
||||
max1236.txbuf[0] = 0b10000011; // config register content. Consult datasheet
|
||||
max1236.txbuf[1] = 0b00000111; // config register content. Consult datasheet
|
||||
|
||||
// transmit out 2 bytes
|
||||
i2cMasterTransmit(&I2CD2, &max1236);
|
||||
while(I2CD2.id_state != I2C_READY) // wait
|
||||
chThdSleepMilliseconds(1);
|
||||
|
||||
// transmit out 2 bytes
|
||||
i2cAcquireBus(&I2CD2);
|
||||
i2cMasterTransmit(&I2CD2, &max1236);
|
||||
while(I2CD2.id_state != I2C_READY){
|
||||
chThdSleepMilliseconds(1);
|
||||
}
|
||||
/* now add pointer to callback function */
|
||||
max1236.id_callback = i2c_max1236_cb;
|
||||
|
||||
/*clear transmitting structures */
|
||||
max1236.txbytes = 0;
|
||||
max1236.txbufhead = 0;
|
||||
|
||||
/* unlock bus */
|
||||
i2cReleaseBus(&I2CD2);
|
||||
}
|
||||
|
||||
|
||||
/* Now simply read 8 bytes to get all 4 ADC channels */
|
||||
void read_max1236(void){
|
||||
/* tune receive buffer */
|
||||
max1236.rxbufhead = 0;
|
||||
max1236.txbytes = 0;
|
||||
max1236.rxbytes = 8;
|
||||
|
||||
/* lock bus */
|
||||
i2cAcquireBus(&I2CD2);
|
||||
|
||||
/* start reading */
|
||||
i2cMasterReceive(&I2CD2, &max1236);
|
||||
i2cReleaseBus(&I2CD2);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -58,25 +58,54 @@
|
|||
#define STM32_CAN_USE_CAN1 FALSE
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 FALSE
|
||||
#define STM32_GPT_USE_TIM2 FALSE
|
||||
#define STM32_GPT_USE_TIM3 FALSE
|
||||
#define STM32_GPT_USE_TIM4 FALSE
|
||||
#define STM32_GPT_USE_TIM5 FALSE
|
||||
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 FALSE
|
||||
#define STM32_ICU_USE_TIM2 FALSE
|
||||
#define STM32_ICU_USE_TIM3 FALSE
|
||||
#define STM32_ICU_USE_TIM4 TRUE
|
||||
#define STM32_ICU_USE_TIM5 FALSE
|
||||
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED FALSE
|
||||
#define STM32_PWM_USE_TIM1 FALSE
|
||||
#define STM32_PWM_USE_TIM2 FALSE
|
||||
#define STM32_PWM_USE_TIM3 TRUE
|
||||
#define STM32_PWM_USE_TIM4 TRUE
|
||||
#define STM32_PWM_USE_TIM5 FALSE
|
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY 2
|
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY 2
|
||||
#define STM32_PWM_TIM3_IRQ_PRIORITY 2
|
||||
#define STM32_PWM_TIM4_IRQ_PRIORITY 2
|
||||
#define STM32_PWM_TIM5_IRQ_PRIORITY 2
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 FALSE
|
||||
#define STM32_SERIAL_USE_USART2 FALSE
|
||||
#define STM32_SERIAL_USE_USART1 TRUE
|
||||
#define STM32_SERIAL_USE_USART2 TRUE
|
||||
#define STM32_SERIAL_USE_USART3 FALSE
|
||||
#define STM32_SERIAL_USE_UART4 FALSE
|
||||
#define STM32_SERIAL_USE_UART5 FALSE
|
||||
|
|
@ -89,24 +118,22 @@
|
|||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 FALSE
|
||||
#define STM32_SPI_USE_SPI2 FALSE
|
||||
#define STM32_SPI_USE_SPI1 TRUE
|
||||
#define STM32_SPI_USE_SPI2 TRUE
|
||||
#define STM32_SPI_USE_SPI3 FALSE
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 2
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 2
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 2
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI1_DMA_ERROR_HOOK() chSysHalt()
|
||||
#define STM32_SPI_SPI2_DMA_ERROR_HOOK() chSysHalt()
|
||||
#define STM32_SPI_SPI3_DMA_ERROR_HOOK() chSysHalt()
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 TRUE
|
||||
#define STM32_UART_USE_USART2 FALSE
|
||||
#define STM32_UART_USE_USART1 FALSE // RF link
|
||||
#define STM32_UART_USE_USART2 FALSE //GPS
|
||||
#define STM32_UART_USE_USART3 FALSE
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||
|
|
@ -114,18 +141,35 @@
|
|||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART1_DMA_ERROR_HOOK() chSysHalt()
|
||||
#define STM32_UART_USART2_DMA_ERROR_HOOK() chSysHalt()
|
||||
#define STM32_UART_USART3_DMA_ERROR_HOOK() chSysHalt()
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 TRUE
|
||||
#define STM32_I2C_USE_I2C2 TRUE
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY 11
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY 11
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY 10
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY 10
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 4
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 4
|
||||
#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
|
||||
#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
|
||||
|
||||
/*
|
||||
* EXTI system settings.
|
||||
*/
|
||||
#define STM32_EXTI0_PRIORITY 5
|
||||
#define STM32_EXTI1_PRIORITY 5
|
||||
#define STM32_EXTI2_PRIORITY 5
|
||||
#define STM32_EXTI3_PRIORITY 5
|
||||
#define STM32_EXTI4_PRIORITY 5
|
||||
#define STM32_EXTI9_5_PRIORITY 5
|
||||
#define STM32_EXTI15_10_PRIORITY 5
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_USB1 TRUE
|
||||
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
|
||||
#define STM32_USB_USB1_HP_IRQ_PRIORITY 6
|
||||
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@
|
|||
// input buffer
|
||||
static i2cblock_t tmp75_rx_data[TMP75_RX_DEPTH];
|
||||
static i2cblock_t tmp75_tx_data[TMP75_TX_DEPTH];
|
||||
// temperature value
|
||||
static int16_t temperature = 0;
|
||||
|
||||
// Simple error trap
|
||||
static void i2c_tmp75_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
|
||||
|
|
@ -26,47 +28,34 @@ static void i2c_tmp75_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
|
|||
|
||||
/* This callback raise up when transfer finished */
|
||||
static void i2c_tmp75_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
|
||||
int16_t temperature = 0;
|
||||
|
||||
/* Manually send stop signal to the bus. This is important! */
|
||||
i2cMasterStop(i2cp);
|
||||
/* unlock bus */
|
||||
i2cReleaseBus(&I2CD2);
|
||||
|
||||
(void)*i2cp;
|
||||
/* store temperature value */
|
||||
temperature = (i2cscfg->rxbuf[0] << 8) + i2cscfg->rxbuf[1];
|
||||
|
||||
}
|
||||
|
||||
// Fill TMP75 config.
|
||||
static I2CSlaveConfig tmp75 = {
|
||||
i2c_tmp75_cb,
|
||||
i2c_tmp75_error_cb,
|
||||
0,
|
||||
0,
|
||||
tmp75_rx_data,
|
||||
TMP75_RX_DEPTH,
|
||||
0,
|
||||
0,
|
||||
tmp75_tx_data,
|
||||
TMP75_TX_DEPTH,
|
||||
0,
|
||||
0,
|
||||
0b1001000,
|
||||
FALSE,
|
||||
7,
|
||||
0,
|
||||
0,
|
||||
{NULL},
|
||||
};
|
||||
|
||||
/* This is main function. */
|
||||
void request_temperature(void){
|
||||
tmp75.txbytes = 0; // set to zero just to be safe
|
||||
tmp75.txbytes = 0; // set to zero because we need only reading
|
||||
tmp75.rxbytes = 2; // we need to read 2 bytes
|
||||
|
||||
/* tune receiving buffer */
|
||||
tmp75.rxbufhead = 0;// point to beginig of buffer
|
||||
tmp75.rxbytes = 2; // we need read 2 bytes
|
||||
|
||||
/* get exclusive access to the bus */
|
||||
i2cAcquireBus(&I2CD2);
|
||||
|
||||
/* start receiving process in background and return */
|
||||
i2cMasterReceive(&I2CD2, &tmp75);
|
||||
i2cReleaseBus(&I2CD2);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue