From 3dea21bb83ff98f9a87b6caafd43fd680f058867 Mon Sep 17 00:00:00 2001 From: Rocco Marco Guglielmi Date: Sun, 10 Apr 2016 18:25:39 +0000 Subject: [PATCH] Added STM32F469 Discovery board file, Added linker script file for STM32F469xI Updated hal_lld.h and stm32_registry supporting STM32F469xx and SM32F479xx Added a demo for STM32F469 Discovery git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9277 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM32/RT-STM32F469I-DISCOVERY/.cproject | 55 + demos/STM32/RT-STM32F469I-DISCOVERY/.project | 95 + demos/STM32/RT-STM32F469I-DISCOVERY/Makefile | 220 +++ demos/STM32/RT-STM32F469I-DISCOVERY/chconf.h | 529 +++++ ...-DISCOVERY (OpenOCD, Flash and Run).launch | 52 + demos/STM32/RT-STM32F469I-DISCOVERY/halconf.h | 381 ++++ demos/STM32/RT-STM32F469I-DISCOVERY/main.c | 127 ++ demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h | 371 ++++ .../STM32/RT-STM32F469I-DISCOVERY/readme.txt | 27 + .../ARMCMx/compilers/GCC/ld/STM32F469xI.ld | 86 + os/hal/boards/ST_STM32F469I_DISCOVERY/board.c | 132 ++ os/hal/boards/ST_STM32F469I_DISCOVERY/board.h | 1725 +++++++++++++++++ .../boards/ST_STM32F469I_DISCOVERY/board.mk | 5 + .../ST_STM32F469I_DISCOVERY/cfg/board.chcfg | 1453 ++++++++++++++ os/hal/ports/STM32/STM32F4xx/hal_lld.h | 18 +- os/hal/ports/STM32/STM32F4xx/stm32_registry.h | 363 +++- 16 files changed, 5633 insertions(+), 6 deletions(-) create mode 100644 demos/STM32/RT-STM32F469I-DISCOVERY/.cproject create mode 100644 demos/STM32/RT-STM32F469I-DISCOVERY/.project create mode 100644 demos/STM32/RT-STM32F469I-DISCOVERY/Makefile create mode 100644 demos/STM32/RT-STM32F469I-DISCOVERY/chconf.h create mode 100644 demos/STM32/RT-STM32F469I-DISCOVERY/debug/RT-STM32F469I-DISCOVERY (OpenOCD, Flash and Run).launch create mode 100644 demos/STM32/RT-STM32F469I-DISCOVERY/halconf.h create mode 100644 demos/STM32/RT-STM32F469I-DISCOVERY/main.c create mode 100644 demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h create mode 100644 demos/STM32/RT-STM32F469I-DISCOVERY/readme.txt create mode 100644 os/common/startup/ARMCMx/compilers/GCC/ld/STM32F469xI.ld create mode 100644 os/hal/boards/ST_STM32F469I_DISCOVERY/board.c create mode 100644 os/hal/boards/ST_STM32F469I_DISCOVERY/board.h create mode 100644 os/hal/boards/ST_STM32F469I_DISCOVERY/board.mk create mode 100644 os/hal/boards/ST_STM32F469I_DISCOVERY/cfg/board.chcfg diff --git a/demos/STM32/RT-STM32F469I-DISCOVERY/.cproject b/demos/STM32/RT-STM32F469I-DISCOVERY/.cproject new file mode 100644 index 000000000..c087bd223 --- /dev/null +++ b/demos/STM32/RT-STM32F469I-DISCOVERY/.cproject @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/STM32/RT-STM32F469I-DISCOVERY/.project b/demos/STM32/RT-STM32F469I-DISCOVERY/.project new file mode 100644 index 000000000..1c246c061 --- /dev/null +++ b/demos/STM32/RT-STM32F469I-DISCOVERY/.project @@ -0,0 +1,95 @@ + + + RT-STM32F469I-DISCOVERY + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j1 + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + C:/ChibiStudio/chibios_trunk/os/hal/boards/ST_STM32F469I_DISCOVERY + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/STM32/RT-STM32F469I-DISCOVERY/Makefile b/demos/STM32/RT-STM32F469I-DISCOVERY/Makefile new file mode 100644 index 000000000..6ec63f64c --- /dev/null +++ b/demos/STM32/RT-STM32F469I-DISCOVERY/Makefile @@ -0,0 +1,220 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_STM32F469I_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +include $(CHIBIOS)/test/rt/test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32F469xI.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + $(STREAMSSRC) \ + $(SHELLSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(STREAMSINC) $(SHELLINC) + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/demos/STM32/RT-STM32F469I-DISCOVERY/chconf.h b/demos/STM32/RT-STM32F469I-DISCOVERY/chconf.h new file mode 100644 index 000000000..a554d3957 --- /dev/null +++ b/demos/STM32/RT-STM32F469I-DISCOVERY/chconf.h @@ -0,0 +1,529 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +#define _CHIBIOS_RT_CONF_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_QUEUES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_NONE. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_NONE + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_NONE. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/STM32/RT-STM32F469I-DISCOVERY/debug/RT-STM32F469I-DISCOVERY (OpenOCD, Flash and Run).launch b/demos/STM32/RT-STM32F469I-DISCOVERY/debug/RT-STM32F469I-DISCOVERY (OpenOCD, Flash and Run).launch new file mode 100644 index 000000000..dd5bffcc3 --- /dev/null +++ b/demos/STM32/RT-STM32F469I-DISCOVERY/debug/RT-STM32F469I-DISCOVERY (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/STM32/RT-STM32F469I-DISCOVERY/halconf.h b/demos/STM32/RT-STM32F469I-DISCOVERY/halconf.h new file mode 100644 index 000000000..dddc44db8 --- /dev/null +++ b/demos/STM32/RT-STM32F469I-DISCOVERY/halconf.h @@ -0,0 +1,381 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/STM32/RT-STM32F469I-DISCOVERY/main.c b/demos/STM32/RT-STM32F469I-DISCOVERY/main.c new file mode 100644 index 000000000..f9f5693d0 --- /dev/null +++ b/demos/STM32/RT-STM32F469I-DISCOVERY/main.c @@ -0,0 +1,127 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "ch_test.h" + +#include "chprintf.h" +#include "shell.h" + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker1"); + while (true) { + palSetPad(GPIOG, GPIOG_LED1); + chThdSleepMilliseconds(50); + palSetPad(GPIOD, GPIOD_LED2); + chThdSleepMilliseconds(300); + palClearPad(GPIOG, GPIOG_LED1); + chThdSleepMilliseconds(50); + palClearPad(GPIOD, GPIOD_LED2); + chThdSleepMilliseconds(300); + } +} + +/* + * Green LED blinker thread, times are in milliseconds. + */ +static THD_WORKING_AREA(waThread2, 128); +static THD_FUNCTION(Thread2, arg) { + + (void)arg; + chRegSetThreadName("blinker2"); + while (true) { + palSetPad(GPIOD, GPIOD_LED3); + chThdSleepMilliseconds(50); + palSetPad(GPIOK, GPIOK_LED4); + chThdSleepMilliseconds(300); + palClearPad(GPIOD, GPIOD_LED3); + chThdSleepMilliseconds(50); + palClearPad(GPIOK, GPIOK_LED4); + chThdSleepMilliseconds(300); + } +} + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048) + +static const ShellCommand commands[] = { + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD3, + commands +}; + +/*===========================================================================*/ +/* Initialization and main thread. */ +/*===========================================================================*/ + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD3, NULL); + + /* + * Creating the blinker threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), + NORMALPRIO + 10, Thread1, NULL); + chThdSleepMilliseconds(100); + chThdCreateStatic(waThread2, sizeof(waThread2), + NORMALPRIO + 10, Thread2, NULL); + + /* + * Normal main() thread activity, spawning shells. + */ + while (true) { + thread_t *shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, + "shell", NORMALPRIO + 1, + shellThread, (void *)&shell_cfg1); + chThdWait(shelltp); /* Waiting termination. */ + chThdSleepMilliseconds(1000); + } +} diff --git a/demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h b/demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h new file mode 100644 index 000000000..eab3ca145 --- /dev/null +++ b/demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h @@ -0,0 +1,371 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_UART7_IRQ_PRIORITY 12 +#define STM32_UART_UART8_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 TRUE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* _MCUCONF_H_ */ diff --git a/demos/STM32/RT-STM32F469I-DISCOVERY/readme.txt b/demos/STM32/RT-STM32F469I-DISCOVERY/readme.txt new file mode 100644 index 000000000..da5584045 --- /dev/null +++ b/demos/STM32/RT-STM32F469I-DISCOVERY/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M4 STM32F469. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F469I-Discovery board. + +** The Demo ** + +A simple command shell is activated on STLink v2-1 virtual serial port SD3 +driver. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F469xI.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F469xI.ld new file mode 100644 index 000000000..a3ad155b8 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F469xI.ld @@ -0,0 +1,86 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * ST32F469xI memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash0 : org = 0x08000000, len = 1M + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 384k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 160k /* SRAM1 */ + ram2 : org = 0x20028000, len = 32k /* SRAM2 */ + ram3 : org = 0x20030000, len = 128k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/hal/boards/ST_STM32F469I_DISCOVERY/board.c b/os/hal/boards/ST_STM32F469I_DISCOVERY/board.c new file mode 100644 index 000000000..c340f41d6 --- /dev/null +++ b/os/hal/boards/ST_STM32F469I_DISCOVERY/board.c @@ -0,0 +1,132 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/os/hal/boards/ST_STM32F469I_DISCOVERY/board.h b/os/hal/boards/ST_STM32F469I_DISCOVERY/board.h new file mode 100644 index 000000000..db2a88784 --- /dev/null +++ b/os/hal/boards/ST_STM32F469I_DISCOVERY/board.h @@ -0,0 +1,1725 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32F469I-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F469I_DISCOVERY +#define BOARD_NAME "STMicroelectronics STM32F469I-Discovery" + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000U +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F469xx + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0U +#define GPIOA_ARD_D3 1U +#define GPIOA_TIM5_CH2 1U +#define GPIOA_ARD_D5 2U +#define GPIOA_TIM5_CH3 2U +#define GPIOA_LCD_BL_CTRL 3U +#define GPIOA_TIM5_CH4 3U +#define GPIOA_ARD_A5 4U +#define GPIOA_EXT_7 5U +#define GPIOA_SPI1_SCK 5U +#define GPIOA_ARD_D6 6U +#define GPIOA_TIM3_CH1 6U +#define GPIOA_ARD_D9 7U +#define GPIOA_TIM3_CH2 7U +#define GPIOA_EXT_3 8U +#define GPIOA_MCO1 8U +#define GPIOA_VBUS_FS1 9U +#define GPIOA_USB_FS1_ID 10U +#define GPIOA_USB_FS1_N 11U +#define GPIOA_USB_FS1_P 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_EXT_11 15U +#define GPIOA_SPI1_NSS 15U + +#define GPIOB_EXT_RESET 0U +#define GPIOB_ARD_A0 1U +#define GPIOB_OTG_FS1_POWERSWITCHON 2U +#define GPIOB_I2S3_CK 3U +#define GPIOB_SPI3_SCK 3U +#define GPIOB_EXT_5 4U +#define GPIOB_SPI1_MISO 4U +#define GPIOB_EXT_9 5U +#define GPIOB_SPI1_MOSI 5U +#define GPIOB_QSPI_BK1_NCS 6U +#define GPIOB_QSPI_FS1_OVERCURRENT 7U +#define GPIOB_I2C1_SCL 8U +#define GPIOB_I2C1_SDA 9U +#define GPIOB_STLK_RX 10U +#define GPIOB_STLK_TX 11U +#define GPIOB_EXT_12 12U +#define GPIOB_CAN2_RX 12U +#define GPIOB_EXT_10 13U +#define GPIOB_CAN2_TX 13U +#define GPIOB_ARD_D12 14U +#define GPIOB_SPI2_MISO 14U +#define GPIOB_ARD_D11 15U +#define GPIOB_SPI2_MOSI 15U + +#define GPIOC_SDNWE 0U +#define GPIOC_EXT_14 1U +#define GPIOC_ADC123_IN11 1U +#define GPIOC_ARD_A1 2U +#define GPIOC_ARD_A2 3U +#define GPIOC_ARD_A3 4U +#define GPIOC_ARD_A4 5U +#define GPIOC_EXT_6 6U +#define GPIOC_USART6_TX 6U +#define GPIOC_EXT_8 7U +#define GPIOC_USART6_RX 7U +#define GPIOC_USD_D0 8U +#define GPIOC_SDIO_D0 8U +#define GPIOC_USD_D1 9U +#define GPIOC_SDIO_D1 9U +#define GPIOC_USD_D2 10U +#define GPIOC_SDIO_D2 10U +#define GPIOC_USD_D3 11U +#define GPIOC_SDIO_D3 11U +#define GPIOC_USD_CLK 12U +#define GPIOC_SDIO_CK 12U +#define GPIOC_EXT_13 13U +#define GPIOC_ANTI_TAMP1 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_USD_CMD 2U +#define GPIOD_SDIO_CMD 2U +#define GPIOD_ARD_D13 3U +#define GPIOD_SPI2_SCK 3U +#define GPIOD_LED2 4U +#define GPIOD_LED3 5U +#define GPIOD_MIC_DATA 6U +#define GPIOD_SAI1_SD_A 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_MIC_CK 13U +#define GPIOD_TIM4_CH2 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +#define GPIOE_FMC_NBL0 0U +#define GPIOE_FMC_NBL1 1U +#define GPIOE_AUDIO_RST 2U +#define GPIOE_SPKR_HP 3U +#define GPIOE_SAI1_FSA 4U +#define GPIOE_SAI1_SCKA 5U +#define GPIOE_SAI1_SDA 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +#define GPIOF_PIN0 0U +#define GPIOF_PIN1 1U +#define GPIOF_PIN2 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_QSPI_BK1_IO3 6U +#define GPIOF_QSPI_BK1_IO2 7U +#define GPIOF_QSPI_BK1_IO0 8U +#define GPIOF_QSPI_BK1_IO1 9U +#define GPIOF_QSPI_CLK 10U +#define GPIOF_SDNRAS 11U +#define GPIOF_PIN12 12U +#define GPIOF_PIN13 13U +#define GPIOF_PIN14 14U +#define GPIOF_PIN15 15U + +#define GPIOG_PIN0 0U +#define GPIOG_PIN1 1U +#define GPIOG_USD_DETECT 2U +#define GPIOG_PIN3 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_LED1 6U +#define GPIOG_SAI1_MCLKA 7U +#define GPIOG_SDCLK 8U +#define GPIOG_ARD_D0 9U +#define GPIOG_ARD_D8 10U +#define GPIOG_ARD_D7 11U +#define GPIOG_ARD_D4 12U +#define GPIOG_ARD_D2 13U +#define GPIOG_ARD_D1 14U +#define GPIOG_SDNCAS 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_SDCKE0 2U +#define GPIOH_SDNE0 3U +#define GPIOH_I2C2_SCL 4U +#define GPIOH_I2C2_SDA 5U +#define GPIOH_ARD_D10 6U +#define GPIOH_SPI2_NSS 6U +#define GPIOH_LCD_RESET 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_FMC_NBL2 4U +#define GPIOI_FMC_NBL3 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U +#define GPIOI_PIN8 8U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U +#define GPIOI_PIN12 12U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U + +#define GPIOJ_PIN0 0U +#define GPIOJ_PIN1 1U +#define GPIOJ_DSI_TE 2U +#define GPIOJ_PIN3 3U +#define GPIOJ_PIN4 4U +#define GPIOJ_LCD_INT 5U +#define GPIOJ_PIN6 6U +#define GPIOJ_PIN7 7U +#define GPIOJ_PIN8 8U +#define GPIOJ_PIN9 9U +#define GPIOJ_PIN10 10U +#define GPIOJ_PIN11 11U +#define GPIOJ_PIN12 12U +#define GPIOJ_PIN13 13U +#define GPIOJ_PIN14 14U +#define GPIOJ_PIN15 15U + +#define GPIOK_PIN0 0U +#define GPIOK_PIN1 1U +#define GPIOK_PIN2 2U +#define GPIOK_LED4 3U +#define GPIOK_PIN4 4U +#define GPIOK_PIN5 5U +#define GPIOK_PIN6 6U +#define GPIOK_PIN7 7U +#define GPIOK_PIN8 8U +#define GPIOK_PIN9 9U +#define GPIOK_PIN10 10U +#define GPIOK_PIN11 11U +#define GPIOK_PIN12 12U +#define GPIOK_PIN13 13U +#define GPIOK_PIN14 14U +#define GPIOK_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_BUTTON PAL_LINE(GPIOA, 0U) +#define LINE_ARD_D3 PAL_LINE(GPIOA, 1U) +#define LINE_TIM5_CH2 PAL_LINE(GPIOA, 1U) +#define LINE_ARD_D5 PAL_LINE(GPIOA, 2U) +#define LINE_TIM5_CH3 PAL_LINE(GPIOA, 2U) +#define LINE_LCD_BL_CTRL PAL_LINE(GPIOA, 3U) +#define LINE_TIM5_CH4 PAL_LINE(GPIOA, 3U) +#define LINE_ARD_A5 PAL_LINE(GPIOA, 4U) +#define LINE_EXT_7 PAL_LINE(GPIOA, 5U) +#define LINE_SPI1_SCK PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D6 PAL_LINE(GPIOA, 6U) +#define LINE_TIM3_CH1 PAL_LINE(GPIOA, 6U) +#define LINE_ARD_D9 PAL_LINE(GPIOA, 7U) +#define LINE_TIM3_CH2 PAL_LINE(GPIOA, 7U) +#define LINE_EXT_3 PAL_LINE(GPIOA, 8U) +#define LINE_MCO1 PAL_LINE(GPIOA, 8U) +#define LINE_VBUS_FS1 PAL_LINE(GPIOA, 9U) +#define LINE_USB_FS1_ID PAL_LINE(GPIOA, 10U) +#define LINE_USB_FS1_N PAL_LINE(GPIOA, 11U) +#define LINE_USB_FS1_P PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_EXT_11 PAL_LINE(GPIOA, 15U) +#define LINE_SPI1_NSS PAL_LINE(GPIOA, 15U) + +#define LINE_EXT_RESET PAL_LINE(GPIOB, 0U) +#define LINE_ARD_A0 PAL_LINE(GPIOB, 1U) +#define LINE_OTG_FS1_POWERSWITCHON PAL_LINE(GPIOB, 2U) +#define LINE_I2S3_CK PAL_LINE(GPIOB, 3U) +#define LINE_SPI3_SCK PAL_LINE(GPIOB, 3U) +#define LINE_EXT_5 PAL_LINE(GPIOB, 4U) +#define LINE_SPI1_MISO PAL_LINE(GPIOB, 4U) +#define LINE_EXT_9 PAL_LINE(GPIOB, 5U) +#define LINE_SPI1_MOSI PAL_LINE(GPIOB, 5U) +#define LINE_QSPI_BK1_NCS PAL_LINE(GPIOB, 6U) +#define LINE_QSPI_FS1_OVERCURRENT PAL_LINE(GPIOB, 7U) +#define LINE_I2C1_SCL PAL_LINE(GPIOB, 8U) +#define LINE_I2C1_SDA PAL_LINE(GPIOB, 9U) +#define LINE_STLK_RX PAL_LINE(GPIOB, 10U) +#define LINE_STLK_TX PAL_LINE(GPIOB, 11U) +#define LINE_EXT_12 PAL_LINE(GPIOB, 12U) +#define LINE_CAN2_RX PAL_LINE(GPIOB, 12U) +#define LINE_EXT_10 PAL_LINE(GPIOB, 13U) +#define LINE_CAN2_TX PAL_LINE(GPIOB, 13U) +#define LINE_ARD_D12 PAL_LINE(GPIOB, 14U) +#define LINE_SPI2_MISO PAL_LINE(GPIOB, 14U) +#define LINE_ARD_D11 PAL_LINE(GPIOB, 15U) +#define LINE_SPI2_MOSI PAL_LINE(GPIOB, 15U) + +#define LINE_SDNWE PAL_LINE(GPIOC, 0U) +#define LINE_EXT_14 PAL_LINE(GPIOC, 1U) +#define LINE_ADC123_IN11 PAL_LINE(GPIOC, 1U) +#define LINE_ARD_A1 PAL_LINE(GPIOC, 2U) +#define LINE_ARD_A2 PAL_LINE(GPIOC, 3U) +#define LINE_ARD_A3 PAL_LINE(GPIOC, 4U) +#define LINE_ARD_A4 PAL_LINE(GPIOC, 5U) +#define LINE_EXT_6 PAL_LINE(GPIOC, 6U) +#define LINE_USART6_TX PAL_LINE(GPIOC, 6U) +#define LINE_EXT_8 PAL_LINE(GPIOC, 7U) +#define LINE_USART6_RX PAL_LINE(GPIOC, 7U) +#define LINE_USD_D0 PAL_LINE(GPIOC, 8U) +#define LINE_SDIO_D0 PAL_LINE(GPIOC, 8U) +#define LINE_USD_D1 PAL_LINE(GPIOC, 9U) +#define LINE_SDIO_D1 PAL_LINE(GPIOC, 9U) +#define LINE_USD_D2 PAL_LINE(GPIOC, 10U) +#define LINE_SDIO_D2 PAL_LINE(GPIOC, 10U) +#define LINE_USD_D3 PAL_LINE(GPIOC, 11U) +#define LINE_SDIO_D3 PAL_LINE(GPIOC, 11U) +#define LINE_USD_CLK PAL_LINE(GPIOC, 12U) +#define LINE_SDIO_CK PAL_LINE(GPIOC, 12U) +#define LINE_EXT_13 PAL_LINE(GPIOC, 13U) +#define LINE_ANTI_TAMP1 PAL_LINE(GPIOC, 13U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) + +#define LINE_USD_CMD PAL_LINE(GPIOD, 2U) +#define LINE_SDIO_CMD PAL_LINE(GPIOD, 2U) +#define LINE_ARD_D13 PAL_LINE(GPIOD, 3U) +#define LINE_SPI2_SCK PAL_LINE(GPIOD, 3U) +#define LINE_LED2 PAL_LINE(GPIOD, 4U) +#define LINE_LED3 PAL_LINE(GPIOD, 5U) +#define LINE_MIC_DATA PAL_LINE(GPIOD, 6U) +#define LINE_SAI1_SD_A PAL_LINE(GPIOD, 6U) +#define LINE_MIC_CK PAL_LINE(GPIOD, 13U) +#define LINE_TIM4_CH2 PAL_LINE(GPIOD, 13U) + +#define LINE_FMC_NBL0 PAL_LINE(GPIOE, 0U) +#define LINE_FMC_NBL1 PAL_LINE(GPIOE, 1U) +#define LINE_AUDIO_RST PAL_LINE(GPIOE, 2U) +#define LINE_SPKR_HP PAL_LINE(GPIOE, 3U) +#define LINE_SAI1_FSA PAL_LINE(GPIOE, 4U) +#define LINE_SAI1_SCKA PAL_LINE(GPIOE, 5U) +#define LINE_SAI1_SDA PAL_LINE(GPIOE, 6U) + +#define LINE_QSPI_BK1_IO3 PAL_LINE(GPIOF, 6U) +#define LINE_QSPI_BK1_IO2 PAL_LINE(GPIOF, 7U) +#define LINE_QSPI_BK1_IO0 PAL_LINE(GPIOF, 8U) +#define LINE_QSPI_BK1_IO1 PAL_LINE(GPIOF, 9U) +#define LINE_QSPI_CLK PAL_LINE(GPIOF, 10U) +#define LINE_SDNRAS PAL_LINE(GPIOF, 11U) + +#define LINE_USD_DETECT PAL_LINE(GPIOG, 2U) +#define LINE_LED1 PAL_LINE(GPIOG, 6U) +#define LINE_SAI1_MCLKA PAL_LINE(GPIOG, 7U) +#define LINE_SDCLK PAL_LINE(GPIOG, 8U) +#define LINE_ARD_D0 PAL_LINE(GPIOG, 9U) +#define LINE_ARD_D8 PAL_LINE(GPIOG, 10U) +#define LINE_ARD_D7 PAL_LINE(GPIOG, 11U) +#define LINE_ARD_D4 PAL_LINE(GPIOG, 12U) +#define LINE_ARD_D2 PAL_LINE(GPIOG, 13U) +#define LINE_ARD_D1 PAL_LINE(GPIOG, 14U) +#define LINE_SDNCAS PAL_LINE(GPIOG, 15U) + +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) +#define LINE_SDCKE0 PAL_LINE(GPIOH, 2U) +#define LINE_SDNE0 PAL_LINE(GPIOH, 3U) +#define LINE_I2C2_SCL PAL_LINE(GPIOH, 4U) +#define LINE_I2C2_SDA PAL_LINE(GPIOH, 5U) +#define LINE_ARD_D10 PAL_LINE(GPIOH, 6U) +#define LINE_SPI2_NSS PAL_LINE(GPIOH, 6U) +#define LINE_LCD_RESET PAL_LINE(GPIOH, 7U) + +#define LINE_FMC_NBL2 PAL_LINE(GPIOI, 4U) +#define LINE_FMC_NBL3 PAL_LINE(GPIOI, 5U) + +#define LINE_DSI_TE PAL_LINE(GPIOJ, 2U) +#define LINE_LCD_INT PAL_LINE(GPIOJ, 5U) + +#define LINE_LED4 PAL_LINE(GPIOK, 3U) + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON (input floating). + * PA1 - ARD_D3 TIM5_CH2 (alternate 2). + * PA2 - ARD_D5 TIM5_CH3 (alternate 2). + * PA3 - LCD_BL_CTRL TIM5_CH4 (alternate 2). + * PA4 - ARD_A5 (analog). + * PA5 - EXT_7 SPI1_SCK (alternate 5). + * PA6 - ARD_D6 TIM3_CH1 (alternate 2). + * PA7 - ARD_D9 TIM3_CH2 (alternate 2). + * PA8 - EXT_3 MCO1 (alternate 0). + * PA9 - VBUS_FS1 (analog). + * PA10 - USB_FS1_ID (alternate 10). + * PA11 - USB_FS1_N (alternate 10). + * PA12 - USB_FS1_P (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - EXT_11 SPI1_NSS (output pushpull maximum). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D3) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D5) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_BL_CTRL) |\ + PIN_MODE_ANALOG(GPIOA_ARD_A5) | \ + PIN_MODE_ALTERNATE(GPIOA_EXT_7) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D6) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D9) | \ + PIN_MODE_ALTERNATE(GPIOA_EXT_3) | \ + PIN_MODE_ANALOG(GPIOA_VBUS_FS1) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_FS1_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_FS1_N) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_FS1_P) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_OUTPUT(GPIOA_EXT_11)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_BL_CTRL) |\ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_EXT_7) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOA_EXT_3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_FS1_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_FS1_N) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_FS1_P) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_EXT_11)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_BUTTON) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D3) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D5) | \ + PIN_OSPEED_HIGH(GPIOA_LCD_BL_CTRL) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A5) | \ + PIN_OSPEED_HIGH(GPIOA_EXT_7) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D6) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D9) | \ + PIN_OSPEED_HIGH(GPIOA_EXT_3) | \ + PIN_OSPEED_HIGH(GPIOA_VBUS_FS1) | \ + PIN_OSPEED_HIGH(GPIOA_USB_FS1_ID) | \ + PIN_OSPEED_HIGH(GPIOA_USB_FS1_N) | \ + PIN_OSPEED_HIGH(GPIOA_USB_FS1_P) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_EXT_11)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D3) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D5) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_BL_CTRL) |\ + PIN_PUPDR_FLOATING(GPIOA_ARD_A5) | \ + PIN_PUPDR_PULLUP(GPIOA_EXT_7) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D6) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D9) | \ + PIN_PUPDR_FLOATING(GPIOA_EXT_3) | \ + PIN_PUPDR_FLOATING(GPIOA_VBUS_FS1) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_FS1_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_FS1_N) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_FS1_P) | \ + PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ + PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_EXT_11)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ + PIN_ODR_HIGH(GPIOA_ARD_D3) | \ + PIN_ODR_HIGH(GPIOA_ARD_D5) | \ + PIN_ODR_HIGH(GPIOA_LCD_BL_CTRL) | \ + PIN_ODR_HIGH(GPIOA_ARD_A5) | \ + PIN_ODR_HIGH(GPIOA_EXT_7) | \ + PIN_ODR_HIGH(GPIOA_ARD_D6) | \ + PIN_ODR_HIGH(GPIOA_ARD_D9) | \ + PIN_ODR_HIGH(GPIOA_EXT_3) | \ + PIN_ODR_HIGH(GPIOA_VBUS_FS1) | \ + PIN_ODR_HIGH(GPIOA_USB_FS1_ID) | \ + PIN_ODR_HIGH(GPIOA_USB_FS1_N) | \ + PIN_ODR_HIGH(GPIOA_USB_FS1_P) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_EXT_11)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \ + PIN_AFIO_AF(GPIOA_ARD_D3, 2) | \ + PIN_AFIO_AF(GPIOA_ARD_D5, 2) | \ + PIN_AFIO_AF(GPIOA_LCD_BL_CTRL, 2) | \ + PIN_AFIO_AF(GPIOA_ARD_A5, 0) | \ + PIN_AFIO_AF(GPIOA_EXT_7, 5) | \ + PIN_AFIO_AF(GPIOA_ARD_D6, 2) | \ + PIN_AFIO_AF(GPIOA_ARD_D9, 2)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_EXT_3, 0) | \ + PIN_AFIO_AF(GPIOA_VBUS_FS1, 0) | \ + PIN_AFIO_AF(GPIOA_USB_FS1_ID, 10) | \ + PIN_AFIO_AF(GPIOA_USB_FS1_N, 10) | \ + PIN_AFIO_AF(GPIOA_USB_FS1_P, 10) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0) | \ + PIN_AFIO_AF(GPIOA_EXT_11, 0)) + +/* + * GPIOB setup: + * + * PB0 - EXT_RESET (output pushpull maximum). + * PB1 - ARD_A0 (analog). + * PB2 - OTG_FS1_POWERSWITCHON (output pushpull maximum). + * PB3 - I2S3_CK SPI3_SCK (alternate 6). + * PB4 - EXT_5 SPI1_MISO (alternate 5). + * PB5 - EXT_9 SPI1_MOSI (alternate 5). + * PB6 - QSPI_BK1_NCS (alternate 10). + * PB7 - QSPI_FS1_OVERCURRENT (input floating). + * PB8 - I2C1_SCL (alternate 4). + * PB9 - I2C1_SDA (alternate 4). + * PB10 - STLK_RX (alternate 7). + * PB11 - STLK_TX (alternate 7). + * PB12 - EXT_12 CAN2_RX (alternate 9). + * PB13 - EXT_10 CAN2_TX (alternate 9). + * PB14 - ARD_D12 SPI2_MISO (alternate 5). + * PB15 - ARD_D11 SPI2_MOSI (alternate 5). + */ +#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_EXT_RESET) | \ + PIN_MODE_ANALOG(GPIOB_ARD_A0) | \ + PIN_MODE_OUTPUT(GPIOB_OTG_FS1_POWERSWITCHON) |\ + PIN_MODE_ALTERNATE(GPIOB_I2S3_CK) | \ + PIN_MODE_ALTERNATE(GPIOB_EXT_5) | \ + PIN_MODE_ALTERNATE(GPIOB_EXT_9) | \ + PIN_MODE_ALTERNATE(GPIOB_QSPI_BK1_NCS) |\ + PIN_MODE_INPUT(GPIOB_QSPI_FS1_OVERCURRENT) |\ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_ALTERNATE(GPIOB_STLK_RX) | \ + PIN_MODE_ALTERNATE(GPIOB_STLK_TX) | \ + PIN_MODE_ALTERNATE(GPIOB_EXT_12) | \ + PIN_MODE_ALTERNATE(GPIOB_EXT_10) | \ + PIN_MODE_ALTERNATE(GPIOB_ARD_D12) | \ + PIN_MODE_ALTERNATE(GPIOB_ARD_D11)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_EXT_RESET) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_FS1_POWERSWITCHON) |\ + PIN_OTYPE_PUSHPULL(GPIOB_I2S3_CK) | \ + PIN_OTYPE_PUSHPULL(GPIOB_EXT_5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_EXT_9) | \ + PIN_OTYPE_PUSHPULL(GPIOB_QSPI_BK1_NCS) |\ + PIN_OTYPE_PUSHPULL(GPIOB_QSPI_FS1_OVERCURRENT) |\ + PIN_OTYPE_PUSHPULL(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_STLK_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOB_STLK_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOB_EXT_12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_EXT_10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D11)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_EXT_RESET) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_A0) | \ + PIN_OSPEED_HIGH(GPIOB_OTG_FS1_POWERSWITCHON) |\ + PIN_OSPEED_HIGH(GPIOB_I2S3_CK) | \ + PIN_OSPEED_HIGH(GPIOB_EXT_5) | \ + PIN_OSPEED_HIGH(GPIOB_EXT_9) | \ + PIN_OSPEED_HIGH(GPIOB_QSPI_BK1_NCS) | \ + PIN_OSPEED_HIGH(GPIOB_QSPI_FS1_OVERCURRENT) |\ + PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_HIGH(GPIOB_STLK_RX) | \ + PIN_OSPEED_HIGH(GPIOB_STLK_TX) | \ + PIN_OSPEED_HIGH(GPIOB_EXT_12) | \ + PIN_OSPEED_HIGH(GPIOB_EXT_10) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D12) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D11)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_EXT_RESET) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_A0) | \ + PIN_PUPDR_PULLUP(GPIOB_OTG_FS1_POWERSWITCHON) |\ + PIN_PUPDR_FLOATING(GPIOB_I2S3_CK) | \ + PIN_PUPDR_FLOATING(GPIOB_EXT_5) | \ + PIN_PUPDR_FLOATING(GPIOB_EXT_9) | \ + PIN_PUPDR_FLOATING(GPIOB_QSPI_BK1_NCS) |\ + PIN_PUPDR_FLOATING(GPIOB_QSPI_FS1_OVERCURRENT) |\ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_FLOATING(GPIOB_STLK_RX) | \ + PIN_PUPDR_FLOATING(GPIOB_STLK_TX) | \ + PIN_PUPDR_FLOATING(GPIOB_EXT_12) | \ + PIN_PUPDR_FLOATING(GPIOB_EXT_10) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D12) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D11)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_EXT_RESET) | \ + PIN_ODR_HIGH(GPIOB_ARD_A0) | \ + PIN_ODR_HIGH(GPIOB_OTG_FS1_POWERSWITCHON) |\ + PIN_ODR_HIGH(GPIOB_I2S3_CK) | \ + PIN_ODR_HIGH(GPIOB_EXT_5) | \ + PIN_ODR_HIGH(GPIOB_EXT_9) | \ + PIN_ODR_HIGH(GPIOB_QSPI_BK1_NCS) | \ + PIN_ODR_HIGH(GPIOB_QSPI_FS1_OVERCURRENT) |\ + PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ + PIN_ODR_HIGH(GPIOB_STLK_RX) | \ + PIN_ODR_HIGH(GPIOB_STLK_TX) | \ + PIN_ODR_HIGH(GPIOB_EXT_12) | \ + PIN_ODR_HIGH(GPIOB_EXT_10) | \ + PIN_ODR_HIGH(GPIOB_ARD_D12) | \ + PIN_ODR_HIGH(GPIOB_ARD_D11)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_EXT_RESET, 0) | \ + PIN_AFIO_AF(GPIOB_ARD_A0, 0) | \ + PIN_AFIO_AF(GPIOB_OTG_FS1_POWERSWITCHON, 0) |\ + PIN_AFIO_AF(GPIOB_I2S3_CK, 6) | \ + PIN_AFIO_AF(GPIOB_EXT_5, 5) | \ + PIN_AFIO_AF(GPIOB_EXT_9, 5) | \ + PIN_AFIO_AF(GPIOB_QSPI_BK1_NCS, 10) | \ + PIN_AFIO_AF(GPIOB_QSPI_FS1_OVERCURRENT, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) | \ + PIN_AFIO_AF(GPIOB_STLK_RX, 7) | \ + PIN_AFIO_AF(GPIOB_STLK_TX, 7) | \ + PIN_AFIO_AF(GPIOB_EXT_12, 9) | \ + PIN_AFIO_AF(GPIOB_EXT_10, 9) | \ + PIN_AFIO_AF(GPIOB_ARD_D12, 5) | \ + PIN_AFIO_AF(GPIOB_ARD_D11, 5)) + +/* + * GPIOC setup: + * + * PC0 - SDNWE (alternate 12). + * PC1 - EXT_14 ADC123_IN11 (analog). + * PC2 - ARD_A1 (analog). + * PC3 - ARD_A2 (analog). + * PC4 - ARD_A3 (analog). + * PC5 - ARD_A4 (analog). + * PC6 - EXT_6 USART6_TX (alternate 8). + * PC7 - EXT_8 USART6_RX (alternate 8). + * PC8 - USD_D0 SDIO_D0 (alternate 12). + * PC9 - USD_D1 SDIO_D1 (alternate 12). + * PC10 - USD_D2 SDIO_D2 (alternate 12). + * PC11 - USD_D3 SDIO_D3 (alternate 12). + * PC12 - USD_CLK SDIO_CK (alternate 12). + * PC13 - EXT_13 ANTI_TAMP1 (input pullup). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_ALTERNATE(GPIOC_SDNWE) | \ + PIN_MODE_ANALOG(GPIOC_EXT_14) | \ + PIN_MODE_ANALOG(GPIOC_ARD_A1) | \ + PIN_MODE_ANALOG(GPIOC_ARD_A2) | \ + PIN_MODE_ANALOG(GPIOC_ARD_A3) | \ + PIN_MODE_ANALOG(GPIOC_ARD_A4) | \ + PIN_MODE_ALTERNATE(GPIOC_EXT_6) | \ + PIN_MODE_ALTERNATE(GPIOC_EXT_8) | \ + PIN_MODE_ALTERNATE(GPIOC_USD_D0) | \ + PIN_MODE_ALTERNATE(GPIOC_USD_D1) | \ + PIN_MODE_ALTERNATE(GPIOC_USD_D2) | \ + PIN_MODE_ALTERNATE(GPIOC_USD_D3) | \ + PIN_MODE_ALTERNATE(GPIOC_USD_CLK) | \ + PIN_MODE_INPUT(GPIOC_EXT_13) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_SDNWE) | \ + PIN_OTYPE_PUSHPULL(GPIOC_EXT_14) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_EXT_6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_EXT_8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_USD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_USD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_USD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_USD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_USD_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_EXT_13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_SDNWE) | \ + PIN_OSPEED_HIGH(GPIOC_EXT_14) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A1) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A2) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A3) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A4) | \ + PIN_OSPEED_HIGH(GPIOC_EXT_6) | \ + PIN_OSPEED_HIGH(GPIOC_EXT_8) | \ + PIN_OSPEED_HIGH(GPIOC_USD_D0) | \ + PIN_OSPEED_HIGH(GPIOC_USD_D1) | \ + PIN_OSPEED_HIGH(GPIOC_USD_D2) | \ + PIN_OSPEED_HIGH(GPIOC_USD_D3) | \ + PIN_OSPEED_HIGH(GPIOC_USD_CLK) | \ + PIN_OSPEED_HIGH(GPIOC_EXT_13) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_SDNWE) | \ + PIN_PUPDR_FLOATING(GPIOC_EXT_14) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_A1) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_A2) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_A3) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_A4) | \ + PIN_PUPDR_FLOATING(GPIOC_EXT_6) | \ + PIN_PUPDR_FLOATING(GPIOC_EXT_8) | \ + PIN_PUPDR_FLOATING(GPIOC_USD_D0) | \ + PIN_PUPDR_FLOATING(GPIOC_USD_D1) | \ + PIN_PUPDR_FLOATING(GPIOC_USD_D2) | \ + PIN_PUPDR_FLOATING(GPIOC_USD_D3) | \ + PIN_PUPDR_FLOATING(GPIOC_USD_CLK) | \ + PIN_PUPDR_PULLUP(GPIOC_EXT_13) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_SDNWE) | \ + PIN_ODR_HIGH(GPIOC_EXT_14) | \ + PIN_ODR_HIGH(GPIOC_ARD_A1) | \ + PIN_ODR_HIGH(GPIOC_ARD_A2) | \ + PIN_ODR_HIGH(GPIOC_ARD_A3) | \ + PIN_ODR_HIGH(GPIOC_ARD_A4) | \ + PIN_ODR_HIGH(GPIOC_EXT_6) | \ + PIN_ODR_HIGH(GPIOC_EXT_8) | \ + PIN_ODR_HIGH(GPIOC_USD_D0) | \ + PIN_ODR_HIGH(GPIOC_USD_D1) | \ + PIN_ODR_HIGH(GPIOC_USD_D2) | \ + PIN_ODR_HIGH(GPIOC_USD_D3) | \ + PIN_ODR_HIGH(GPIOC_USD_CLK) | \ + PIN_ODR_HIGH(GPIOC_EXT_13) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_SDNWE, 12) | \ + PIN_AFIO_AF(GPIOC_EXT_14, 0) | \ + PIN_AFIO_AF(GPIOC_ARD_A1, 0) | \ + PIN_AFIO_AF(GPIOC_ARD_A2, 0) | \ + PIN_AFIO_AF(GPIOC_ARD_A3, 0) | \ + PIN_AFIO_AF(GPIOC_ARD_A4, 0) | \ + PIN_AFIO_AF(GPIOC_EXT_6, 8) | \ + PIN_AFIO_AF(GPIOC_EXT_8, 8)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_USD_D0, 12) | \ + PIN_AFIO_AF(GPIOC_USD_D1, 12) | \ + PIN_AFIO_AF(GPIOC_USD_D2, 12) | \ + PIN_AFIO_AF(GPIOC_USD_D3, 12) | \ + PIN_AFIO_AF(GPIOC_USD_CLK, 12) | \ + PIN_AFIO_AF(GPIOC_EXT_13, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - USD_CMD SDIO_CMD (alternate 12). + * PD3 - ARD_D13 SPI2_SCK (alternate 5). + * PD4 - LED2 (output pushpull maximum). + * PD5 - LED3 (output pushpull maximum). + * PD6 - MIC_DATA SAI1_SD_A (alternate 6). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - PIN12 (input pullup). + * PD13 - MIC_CK TIM4_CH2 (alternate 2). + * PD14 - PIN14 (input pullup). + * PD15 - PIN15 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_ALTERNATE(GPIOD_USD_CMD) | \ + PIN_MODE_ALTERNATE(GPIOD_ARD_D13) | \ + PIN_MODE_OUTPUT(GPIOD_LED2) | \ + PIN_MODE_OUTPUT(GPIOD_LED3) | \ + PIN_MODE_ALTERNATE(GPIOD_MIC_DATA) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOD_MIC_CK) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USD_CMD) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ARD_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MIC_DATA) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MIC_CK) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN1) | \ + PIN_OSPEED_HIGH(GPIOD_USD_CMD) | \ + PIN_OSPEED_HIGH(GPIOD_ARD_D13) | \ + PIN_OSPEED_HIGH(GPIOD_LED2) | \ + PIN_OSPEED_HIGH(GPIOD_LED3) | \ + PIN_OSPEED_HIGH(GPIOD_MIC_DATA) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN12) | \ + PIN_OSPEED_HIGH(GPIOD_MIC_CK) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOD_USD_CMD) | \ + PIN_PUPDR_FLOATING(GPIOD_ARD_D13) | \ + PIN_PUPDR_FLOATING(GPIOD_LED2) | \ + PIN_PUPDR_FLOATING(GPIOD_LED3) | \ + PIN_PUPDR_FLOATING(GPIOD_MIC_DATA) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOD_MIC_CK) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_USD_CMD) | \ + PIN_ODR_HIGH(GPIOD_ARD_D13) | \ + PIN_ODR_HIGH(GPIOD_LED2) | \ + PIN_ODR_HIGH(GPIOD_LED3) | \ + PIN_ODR_HIGH(GPIOD_MIC_DATA) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_MIC_CK) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0) | \ + PIN_AFIO_AF(GPIOD_USD_CMD, 12) | \ + PIN_AFIO_AF(GPIOD_ARD_D13, 5) | \ + PIN_AFIO_AF(GPIOD_LED2, 0) | \ + PIN_AFIO_AF(GPIOD_LED3, 0) | \ + PIN_AFIO_AF(GPIOD_MIC_DATA, 6) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0) | \ + PIN_AFIO_AF(GPIOD_MIC_CK, 2) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0)) + +/* + * GPIOE setup: + * + * PE0 - FMC_NBL0 (alternate 12). + * PE1 - FMC_NBL1 (alternate 12). + * PE2 - AUDIO_RST (alternate 6). + * PE3 - SPKR_HP (alternate 6). + * PE4 - SAI1_FSA (alternate 6). + * PE5 - SAI1_SCKA (alternate 6). + * PE6 - SAI1_SDA (alternate 6). + * PE7 - PIN7 (input pullup). + * PE8 - PIN8 (input pullup). + * PE9 - PIN9 (input pullup). + * PE10 - PIN10 (input pullup). + * PE11 - PIN11 (input pullup). + * PE12 - PIN12 (input pullup). + * PE13 - PIN13 (input pullup). + * PE14 - PIN14 (input pullup). + * PE15 - PIN15 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(GPIOE_FMC_NBL0) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_NBL1) | \ + PIN_MODE_ALTERNATE(GPIOE_AUDIO_RST) | \ + PIN_MODE_ALTERNATE(GPIOE_SPKR_HP) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_FSA) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_SCKA) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_SDA) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_AUDIO_RST) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SPKR_HP) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_FSA) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_SCKA) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_FMC_NBL0) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_NBL1) | \ + PIN_OSPEED_HIGH(GPIOE_AUDIO_RST) | \ + PIN_OSPEED_HIGH(GPIOE_SPKR_HP) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_FSA) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_SCKA) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_SDA) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_FMC_NBL0) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_NBL1) | \ + PIN_PUPDR_FLOATING(GPIOE_AUDIO_RST) | \ + PIN_PUPDR_FLOATING(GPIOE_SPKR_HP) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_FSA) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_SCKA) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_SDA) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_FMC_NBL0) | \ + PIN_ODR_HIGH(GPIOE_FMC_NBL1) | \ + PIN_ODR_HIGH(GPIOE_AUDIO_RST) | \ + PIN_ODR_HIGH(GPIOE_SPKR_HP) | \ + PIN_ODR_HIGH(GPIOE_SAI1_FSA) | \ + PIN_ODR_HIGH(GPIOE_SAI1_SCKA) | \ + PIN_ODR_HIGH(GPIOE_SAI1_SDA) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_FMC_NBL0, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_NBL1, 12) | \ + PIN_AFIO_AF(GPIOE_AUDIO_RST, 6) | \ + PIN_AFIO_AF(GPIOE_SPKR_HP, 6) | \ + PIN_AFIO_AF(GPIOE_SAI1_FSA, 6) | \ + PIN_AFIO_AF(GPIOE_SAI1_SCKA, 6) | \ + PIN_AFIO_AF(GPIOE_SAI1_SDA, 6) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (input pullup). + * PF1 - PIN1 (input pullup). + * PF2 - PIN2 (input pullup). + * PF3 - PIN3 (input pullup). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - QSPI_BK1_IO3 (alternate 9). + * PF7 - QSPI_BK1_IO2 (alternate 9). + * PF8 - QSPI_BK1_IO0 (alternate 9). + * PF9 - QSPI_BK1_IO1 (alternate 9). + * PF10 - QSPI_CLK (alternate 9). + * PF11 - SDNRAS (alternate 12). + * PF12 - PIN12 (input pullup). + * PF13 - PIN13 (input pullup). + * PF14 - PIN14 (input pullup). + * PF15 - PIN15 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOF_QSPI_BK1_IO3) |\ + PIN_MODE_ALTERNATE(GPIOF_QSPI_BK1_IO2) |\ + PIN_MODE_ALTERNATE(GPIOF_QSPI_BK1_IO0) |\ + PIN_MODE_ALTERNATE(GPIOF_QSPI_BK1_IO1) |\ + PIN_MODE_ALTERNATE(GPIOF_QSPI_CLK) | \ + PIN_MODE_ALTERNATE(GPIOF_SDNRAS) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_QSPI_BK1_IO3) |\ + PIN_OTYPE_PUSHPULL(GPIOF_QSPI_BK1_IO2) |\ + PIN_OTYPE_PUSHPULL(GPIOF_QSPI_BK1_IO0) |\ + PIN_OTYPE_PUSHPULL(GPIOF_QSPI_BK1_IO1) |\ + PIN_OTYPE_PUSHPULL(GPIOF_QSPI_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SDNRAS) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN5) | \ + PIN_OSPEED_HIGH(GPIOF_QSPI_BK1_IO3) | \ + PIN_OSPEED_HIGH(GPIOF_QSPI_BK1_IO2) | \ + PIN_OSPEED_HIGH(GPIOF_QSPI_BK1_IO0) | \ + PIN_OSPEED_HIGH(GPIOF_QSPI_BK1_IO1) | \ + PIN_OSPEED_HIGH(GPIOF_QSPI_CLK) | \ + PIN_OSPEED_HIGH(GPIOF_SDNRAS) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOF_QSPI_BK1_IO3) |\ + PIN_PUPDR_FLOATING(GPIOF_QSPI_BK1_IO2) |\ + PIN_PUPDR_FLOATING(GPIOF_QSPI_BK1_IO0) |\ + PIN_PUPDR_FLOATING(GPIOF_QSPI_BK1_IO1) |\ + PIN_PUPDR_FLOATING(GPIOF_QSPI_CLK) | \ + PIN_PUPDR_FLOATING(GPIOF_SDNRAS) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_QSPI_BK1_IO3) | \ + PIN_ODR_HIGH(GPIOF_QSPI_BK1_IO2) | \ + PIN_ODR_HIGH(GPIOF_QSPI_BK1_IO0) | \ + PIN_ODR_HIGH(GPIOF_QSPI_BK1_IO1) | \ + PIN_ODR_HIGH(GPIOF_QSPI_CLK) | \ + PIN_ODR_HIGH(GPIOF_SDNRAS) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0) | \ + PIN_AFIO_AF(GPIOF_QSPI_BK1_IO3, 9) | \ + PIN_AFIO_AF(GPIOF_QSPI_BK1_IO2, 9)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_QSPI_BK1_IO0, 9) | \ + PIN_AFIO_AF(GPIOF_QSPI_BK1_IO1, 9) | \ + PIN_AFIO_AF(GPIOF_QSPI_CLK, 9) | \ + PIN_AFIO_AF(GPIOF_SDNRAS, 12) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (input pullup). + * PG1 - PIN1 (input pullup). + * PG2 - USD_DETECT (input pullup). + * PG3 - PIN3 (input pullup). + * PG4 - PIN4 (input pullup). + * PG5 - PIN5 (input pullup). + * PG6 - LED1 (output pushpull maximum). + * PG7 - SAI1_MCLKA (alternate 6). + * PG8 - SDCLK (alternate 12). + * PG9 - ARD_D0 (input pullup). + * PG10 - ARD_D8 (input pullup). + * PG11 - ARD_D7 (input pullup). + * PG12 - ARD_D4 (input pullup). + * PG13 - ARD_D2 (input pullup). + * PG14 - ARD_D1 (input pullup). + * PG15 - SDNCAS (alternate 12). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ + PIN_MODE_INPUT(GPIOG_PIN1) | \ + PIN_MODE_INPUT(GPIOG_USD_DETECT) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_OUTPUT(GPIOG_LED1) | \ + PIN_MODE_ALTERNATE(GPIOG_SAI1_MCLKA) | \ + PIN_MODE_ALTERNATE(GPIOG_SDCLK) | \ + PIN_MODE_INPUT(GPIOG_ARD_D0) | \ + PIN_MODE_INPUT(GPIOG_ARD_D8) | \ + PIN_MODE_INPUT(GPIOG_ARD_D7) | \ + PIN_MODE_INPUT(GPIOG_ARD_D4) | \ + PIN_MODE_INPUT(GPIOG_ARD_D2) | \ + PIN_MODE_INPUT(GPIOG_ARD_D1) | \ + PIN_MODE_ALTERNATE(GPIOG_SDNCAS)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_USD_DETECT) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LED1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SAI1_MCLKA) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SDCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ARD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ARD_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ARD_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ARD_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ARD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ARD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SDNCAS)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \ + PIN_OSPEED_HIGH(GPIOG_USD_DETECT) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \ + PIN_OSPEED_HIGH(GPIOG_LED1) | \ + PIN_OSPEED_HIGH(GPIOG_SAI1_MCLKA) | \ + PIN_OSPEED_HIGH(GPIOG_SDCLK) | \ + PIN_OSPEED_VERYLOW(GPIOG_ARD_D0) | \ + PIN_OSPEED_VERYLOW(GPIOG_ARD_D8) | \ + PIN_OSPEED_VERYLOW(GPIOG_ARD_D7) | \ + PIN_OSPEED_VERYLOW(GPIOG_ARD_D4) | \ + PIN_OSPEED_VERYLOW(GPIOG_ARD_D2) | \ + PIN_OSPEED_VERYLOW(GPIOG_ARD_D1) | \ + PIN_OSPEED_HIGH(GPIOG_SDNCAS)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOG_USD_DETECT) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOG_LED1) | \ + PIN_PUPDR_FLOATING(GPIOG_SAI1_MCLKA) | \ + PIN_PUPDR_FLOATING(GPIOG_SDCLK) | \ + PIN_PUPDR_PULLUP(GPIOG_ARD_D0) | \ + PIN_PUPDR_PULLUP(GPIOG_ARD_D8) | \ + PIN_PUPDR_PULLUP(GPIOG_ARD_D7) | \ + PIN_PUPDR_PULLUP(GPIOG_ARD_D4) | \ + PIN_PUPDR_PULLUP(GPIOG_ARD_D2) | \ + PIN_PUPDR_PULLUP(GPIOG_ARD_D1) | \ + PIN_PUPDR_FLOATING(GPIOG_SDNCAS)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_USD_DETECT) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_LED1) | \ + PIN_ODR_HIGH(GPIOG_SAI1_MCLKA) | \ + PIN_ODR_HIGH(GPIOG_SDCLK) | \ + PIN_ODR_HIGH(GPIOG_ARD_D0) | \ + PIN_ODR_HIGH(GPIOG_ARD_D8) | \ + PIN_ODR_HIGH(GPIOG_ARD_D7) | \ + PIN_ODR_HIGH(GPIOG_ARD_D4) | \ + PIN_ODR_HIGH(GPIOG_ARD_D2) | \ + PIN_ODR_HIGH(GPIOG_ARD_D1) | \ + PIN_ODR_HIGH(GPIOG_SDNCAS)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0) | \ + PIN_AFIO_AF(GPIOG_USD_DETECT, 0) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0) | \ + PIN_AFIO_AF(GPIOG_LED1, 0) | \ + PIN_AFIO_AF(GPIOG_SAI1_MCLKA, 6)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_SDCLK, 12) | \ + PIN_AFIO_AF(GPIOG_ARD_D0, 0) | \ + PIN_AFIO_AF(GPIOG_ARD_D8, 0) | \ + PIN_AFIO_AF(GPIOG_ARD_D7, 0) | \ + PIN_AFIO_AF(GPIOG_ARD_D4, 0) | \ + PIN_AFIO_AF(GPIOG_ARD_D2, 0) | \ + PIN_AFIO_AF(GPIOG_ARD_D1, 0) | \ + PIN_AFIO_AF(GPIOG_SDNCAS, 12)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - SDCKE0 (alternate 12). + * PH3 - SDNE0 (alternate 12). + * PH4 - I2C2_SCL (alternate 4). + * PH5 - I2C2_SDA (alternate 4). + * PH6 - ARD_D10 SPI2_NSS (output pushpull maximum). + * PH7 - LCD_RESET (output pushpull minimum). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_ALTERNATE(GPIOH_SDCKE0) | \ + PIN_MODE_ALTERNATE(GPIOH_SDNE0) | \ + PIN_MODE_ALTERNATE(GPIOH_I2C2_SCL) | \ + PIN_MODE_ALTERNATE(GPIOH_I2C2_SDA) | \ + PIN_MODE_OUTPUT(GPIOH_ARD_D10) | \ + PIN_MODE_OUTPUT(GPIOH_LCD_RESET) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_SDCKE0) | \ + PIN_OTYPE_PUSHPULL(GPIOH_SDNE0) | \ + PIN_OTYPE_PUSHPULL(GPIOH_I2C2_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOH_I2C2_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOH_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_LCD_RESET) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_HIGH(GPIOH_SDCKE0) | \ + PIN_OSPEED_HIGH(GPIOH_SDNE0) | \ + PIN_OSPEED_HIGH(GPIOH_I2C2_SCL) | \ + PIN_OSPEED_HIGH(GPIOH_I2C2_SDA) | \ + PIN_OSPEED_HIGH(GPIOH_ARD_D10) | \ + PIN_OSPEED_VERYLOW(GPIOH_LCD_RESET) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_FLOATING(GPIOH_SDCKE0) | \ + PIN_PUPDR_FLOATING(GPIOH_SDNE0) | \ + PIN_PUPDR_FLOATING(GPIOH_I2C2_SCL) | \ + PIN_PUPDR_FLOATING(GPIOH_I2C2_SDA) | \ + PIN_PUPDR_PULLUP(GPIOH_ARD_D10) | \ + PIN_PUPDR_PULLUP(GPIOH_LCD_RESET) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_SDCKE0) | \ + PIN_ODR_HIGH(GPIOH_SDNE0) | \ + PIN_ODR_HIGH(GPIOH_I2C2_SCL) | \ + PIN_ODR_HIGH(GPIOH_I2C2_SDA) | \ + PIN_ODR_HIGH(GPIOH_ARD_D10) | \ + PIN_ODR_HIGH(GPIOH_LCD_RESET) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \ + PIN_AFIO_AF(GPIOH_SDCKE0, 12) | \ + PIN_AFIO_AF(GPIOH_SDNE0, 12) | \ + PIN_AFIO_AF(GPIOH_I2C2_SCL, 4) | \ + PIN_AFIO_AF(GPIOH_I2C2_SDA, 4) | \ + PIN_AFIO_AF(GPIOH_ARD_D10, 0) | \ + PIN_AFIO_AF(GPIOH_LCD_RESET, 0)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - FMC_NBL2 (alternate 12). + * PI5 - FMC_NBL3 (alternate 12). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_NBL2) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_NBL3) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_NBL2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_NBL3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_NBL2) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_NBL3) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_NBL2) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_NBL3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_FMC_NBL2) | \ + PIN_ODR_HIGH(GPIOI_FMC_NBL3) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0) | \ + PIN_AFIO_AF(GPIOI_FMC_NBL2, 12) | \ + PIN_AFIO_AF(GPIOI_FMC_NBL3, 12) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0)) + +/* + * GPIOJ setup: + * + * PJ0 - PIN0 (input pullup). + * PJ1 - PIN1 (input pullup). + * PJ2 - DSI_TE (alternate 13). + * PJ3 - PIN3 (input pullup). + * PJ4 - PIN4 (input pullup). + * PJ5 - LCD_INT (input pullup). + * PJ6 - PIN6 (input pullup). + * PJ7 - PIN7 (input pullup). + * PJ8 - PIN8 (input pullup). + * PJ9 - PIN9 (input pullup). + * PJ10 - PIN10 (input pullup). + * PJ11 - PIN11 (input pullup). + * PJ12 - PIN12 (input pullup). + * PJ13 - PIN13 (input pullup). + * PJ14 - PIN14 (input pullup). + * PJ15 - PIN15 (input pullup). + */ +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \ + PIN_MODE_INPUT(GPIOJ_PIN1) | \ + PIN_MODE_ALTERNATE(GPIOJ_DSI_TE) | \ + PIN_MODE_INPUT(GPIOJ_PIN3) | \ + PIN_MODE_INPUT(GPIOJ_PIN4) | \ + PIN_MODE_INPUT(GPIOJ_LCD_INT) | \ + PIN_MODE_INPUT(GPIOJ_PIN6) | \ + PIN_MODE_INPUT(GPIOJ_PIN7) | \ + PIN_MODE_INPUT(GPIOJ_PIN8) | \ + PIN_MODE_INPUT(GPIOJ_PIN9) | \ + PIN_MODE_INPUT(GPIOJ_PIN10) | \ + PIN_MODE_INPUT(GPIOJ_PIN11) | \ + PIN_MODE_INPUT(GPIOJ_PIN12) | \ + PIN_MODE_INPUT(GPIOJ_PIN13) | \ + PIN_MODE_INPUT(GPIOJ_PIN14) | \ + PIN_MODE_INPUT(GPIOJ_PIN15)) +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_DSI_TE) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_INT) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN15)) +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN1) | \ + PIN_OSPEED_HIGH(GPIOJ_DSI_TE) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOJ_LCD_INT) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN15)) +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLUP(GPIOJ_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOJ_DSI_TE) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOJ_LCD_INT) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN15)) +#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \ + PIN_ODR_HIGH(GPIOJ_PIN1) | \ + PIN_ODR_HIGH(GPIOJ_DSI_TE) | \ + PIN_ODR_HIGH(GPIOJ_PIN3) | \ + PIN_ODR_HIGH(GPIOJ_PIN4) | \ + PIN_ODR_HIGH(GPIOJ_LCD_INT) | \ + PIN_ODR_HIGH(GPIOJ_PIN6) | \ + PIN_ODR_HIGH(GPIOJ_PIN7) | \ + PIN_ODR_HIGH(GPIOJ_PIN8) | \ + PIN_ODR_HIGH(GPIOJ_PIN9) | \ + PIN_ODR_HIGH(GPIOJ_PIN10) | \ + PIN_ODR_HIGH(GPIOJ_PIN11) | \ + PIN_ODR_HIGH(GPIOJ_PIN12) | \ + PIN_ODR_HIGH(GPIOJ_PIN13) | \ + PIN_ODR_HIGH(GPIOJ_PIN14) | \ + PIN_ODR_HIGH(GPIOJ_PIN15)) +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN1, 0) | \ + PIN_AFIO_AF(GPIOJ_DSI_TE, 13) | \ + PIN_AFIO_AF(GPIOJ_PIN3, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN4, 0) | \ + PIN_AFIO_AF(GPIOJ_LCD_INT, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN6, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN7, 0)) +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN9, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN10, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN11, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN12, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN13, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN14, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN15, 0)) + +/* + * GPIOK setup: + * + * PK0 - PIN0 (input pullup). + * PK1 - PIN1 (input pullup). + * PK2 - PIN2 (input pullup). + * PK3 - LED4 (output pushpull maximum). + * PK4 - PIN4 (input pullup). + * PK5 - PIN5 (input pullup). + * PK6 - PIN6 (input pullup). + * PK7 - PIN7 (input pullup). + * PK8 - PIN8 (input pullup). + * PK9 - PIN9 (input pullup). + * PK10 - PIN10 (input pullup). + * PK11 - PIN11 (input pullup). + * PK12 - PIN12 (input pullup). + * PK13 - PIN13 (input pullup). + * PK14 - PIN14 (input pullup). + * PK15 - PIN15 (input pullup). + */ +#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \ + PIN_MODE_INPUT(GPIOK_PIN1) | \ + PIN_MODE_INPUT(GPIOK_PIN2) | \ + PIN_MODE_OUTPUT(GPIOK_LED4) | \ + PIN_MODE_INPUT(GPIOK_PIN4) | \ + PIN_MODE_INPUT(GPIOK_PIN5) | \ + PIN_MODE_INPUT(GPIOK_PIN6) | \ + PIN_MODE_INPUT(GPIOK_PIN7) | \ + PIN_MODE_INPUT(GPIOK_PIN8) | \ + PIN_MODE_INPUT(GPIOK_PIN9) | \ + PIN_MODE_INPUT(GPIOK_PIN10) | \ + PIN_MODE_INPUT(GPIOK_PIN11) | \ + PIN_MODE_INPUT(GPIOK_PIN12) | \ + PIN_MODE_INPUT(GPIOK_PIN13) | \ + PIN_MODE_INPUT(GPIOK_PIN14) | \ + PIN_MODE_INPUT(GPIOK_PIN15)) +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOK_LED4) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN15)) +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \ + PIN_OSPEED_HIGH(GPIOK_LED4) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN15)) +#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLUP(GPIOK_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOK_LED4) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN15)) +#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \ + PIN_ODR_HIGH(GPIOK_PIN1) | \ + PIN_ODR_HIGH(GPIOK_PIN2) | \ + PIN_ODR_HIGH(GPIOK_LED4) | \ + PIN_ODR_HIGH(GPIOK_PIN4) | \ + PIN_ODR_HIGH(GPIOK_PIN5) | \ + PIN_ODR_HIGH(GPIOK_PIN6) | \ + PIN_ODR_HIGH(GPIOK_PIN7) | \ + PIN_ODR_HIGH(GPIOK_PIN8) | \ + PIN_ODR_HIGH(GPIOK_PIN9) | \ + PIN_ODR_HIGH(GPIOK_PIN10) | \ + PIN_ODR_HIGH(GPIOK_PIN11) | \ + PIN_ODR_HIGH(GPIOK_PIN12) | \ + PIN_ODR_HIGH(GPIOK_PIN13) | \ + PIN_ODR_HIGH(GPIOK_PIN14) | \ + PIN_ODR_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0) | \ + PIN_AFIO_AF(GPIOK_PIN1, 0) | \ + PIN_AFIO_AF(GPIOK_PIN2, 0) | \ + PIN_AFIO_AF(GPIOK_LED4, 0) | \ + PIN_AFIO_AF(GPIOK_PIN4, 0) | \ + PIN_AFIO_AF(GPIOK_PIN5, 0) | \ + PIN_AFIO_AF(GPIOK_PIN6, 0) | \ + PIN_AFIO_AF(GPIOK_PIN7, 0)) +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0) | \ + PIN_AFIO_AF(GPIOK_PIN9, 0) | \ + PIN_AFIO_AF(GPIOK_PIN10, 0) | \ + PIN_AFIO_AF(GPIOK_PIN11, 0) | \ + PIN_AFIO_AF(GPIOK_PIN12, 0) | \ + PIN_AFIO_AF(GPIOK_PIN13, 0) | \ + PIN_AFIO_AF(GPIOK_PIN14, 0) | \ + PIN_AFIO_AF(GPIOK_PIN15, 0)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/ST_STM32F469I_DISCOVERY/board.mk b/os/hal/boards/ST_STM32F469I_DISCOVERY/board.mk new file mode 100644 index 000000000..17db1cfdf --- /dev/null +++ b/os/hal/boards/ST_STM32F469I_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32F469I_DISCOVERY/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32F469I_DISCOVERY diff --git a/os/hal/boards/ST_STM32F469I_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F469I_DISCOVERY/cfg/board.chcfg new file mode 100644 index 000000000..da6b66773 --- /dev/null +++ b/os/hal/boards/ST_STM32F469I_DISCOVERY/cfg/board.chcfg @@ -0,0 +1,1453 @@ + + + + + resources/gencfg/processors/boards/stm32f4xx/templates + .. + 3.0.x + + STMicroelectronics STM32F469I-Discovery + ST_STM32F469I_DISCOVERY + + STM32F469xx + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h index b1c778552..f4d1f1955 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h @@ -58,12 +58,18 @@ * @name Platform identification macros * @{ */ -#if defined(STM32F439xx) || defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32F439 High Performance with DSP and FPU" +#if defined(STM32F479xx) || defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F479 High Performance with DSP and FPU" + +#elif defined(STM32F469xx) +#define PLATFORM_NAME "STM32F469 High Performance with DSP and FPU" #elif defined(STM32F446xx) #define PLATFORM_NAME "STM32F446 High Performance with DSP and FPU" +#elif defined(STM32F439xx) +#define PLATFORM_NAME "STM32F439 High Performance with DSP and FPU" + #elif defined(STM32F429xx) #define PLATFORM_NAME "STM32F429 High Performance with DSP and FPU" @@ -117,7 +123,8 @@ */ #if defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F446xx) || defined(__DOXYGEN__) + defined(STM32F446xx) || defined(STM32F469xx) || \ + defined(STM32F479xx) || defined(__DOXYGEN__) /** * @brief Absolute maximum system clock. */ @@ -752,7 +759,7 @@ */ #if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ defined(STM32F40_41xxx) || defined(STM32F446xx) || \ - defined(__DOXYGEN__) + defined(STM32F469_479xx) || defined(__DOXYGEN__) #if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__) #define STM32_0WS_THRESHOLD 30000000 #define STM32_1WS_THRESHOLD 60000000 @@ -1162,7 +1169,8 @@ /* Calculating VOS settings, it is different for each sub-platform.*/ #if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ - defined(STM32F446xx) || defined(__DOXYGEN__) + defined(STM32F446xx) || defined(STM32F469_479xx) || \ + defined(__DOXYGEN__) #if STM32_SYSCLK <= 120000000 #define STM32_VOS STM32_VOS_SCALE3 #define STM32_OVERDRIVE_REQUIRED FALSE diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index 68b73d508..34f1e456c 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -25,7 +25,11 @@ #ifndef STM32_REGISTRY_H #define STM32_REGISTRY_H -#if defined(STM32F446xx) +#if defined(STM32F469xx) || defined(STM32F479xx) +#define STM32F469_479xx +#define STM32F4XX + +#elif defined(STM32F446xx) #define STM32F4XX #elif defined(STM32F439xx) || defined(STM32F429xx) @@ -66,6 +70,363 @@ * @{ */ +/*===========================================================================*/ +/* STM32F469xx, STM32F479xx. */ +/*===========================================================================*/ +#if defined(STM32F469_479xx) +/* ADC attributes.*/ +#define STM32_ADC_HANDLER Vector88 +#define STM32_ADC_NUMBER 18 + +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_ADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC2 TRUE +#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_ADC2_DMA_CHN 0x00001100 + +#define STM32_HAS_ADC3 TRUE +#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 1)) +#define STM32_ADC3_DMA_CHN 0x00000022 + +#define STM32_HAS_ADC4 FALSE + +#define STM32_HAS_SDADC1 FALSE +#define STM32_HAS_SDADC2 FALSE +#define STM32_HAS_SDADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 TRUE +#define STM32_CAN_MAX_FILTERS 28 + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_DAC1_CH1_DMA_CHN 0x00700000 + +#define STM32_HAS_DAC1_CH2 TRUE +#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_DAC1_CH2_DMA_CHN 0x07000000 + +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_CACHE_HANDLING FALSE + +#define STM32_HAS_DMA1 TRUE +#define STM32_DMA1_CH0_HANDLER Vector6C +#define STM32_DMA1_CH1_HANDLER Vector70 +#define STM32_DMA1_CH2_HANDLER Vector74 +#define STM32_DMA1_CH3_HANDLER Vector78 +#define STM32_DMA1_CH4_HANDLER Vector7C +#define STM32_DMA1_CH5_HANDLER Vector80 +#define STM32_DMA1_CH6_HANDLER Vector84 +#define STM32_DMA1_CH7_HANDLER VectorFC +#define STM32_DMA1_CH0_NUMBER 11 +#define STM32_DMA1_CH1_NUMBER 12 +#define STM32_DMA1_CH2_NUMBER 13 +#define STM32_DMA1_CH3_NUMBER 14 +#define STM32_DMA1_CH4_NUMBER 15 +#define STM32_DMA1_CH5_NUMBER 16 +#define STM32_DMA1_CH6_NUMBER 17 +#define STM32_DMA1_CH7_NUMBER 47 + +#define STM32_HAS_DMA2 TRUE +#define STM32_DMA2_CH0_HANDLER Vector120 +#define STM32_DMA2_CH1_HANDLER Vector124 +#define STM32_DMA2_CH2_HANDLER Vector128 +#define STM32_DMA2_CH3_HANDLER Vector12C +#define STM32_DMA2_CH4_HANDLER Vector130 +#define STM32_DMA2_CH5_HANDLER Vector150 +#define STM32_DMA2_CH6_HANDLER Vector154 +#define STM32_DMA2_CH7_HANDLER Vector158 +#define STM32_DMA2_CH0_NUMBER 56 +#define STM32_DMA2_CH1_NUMBER 57 +#define STM32_DMA2_CH2_NUMBER 58 +#define STM32_DMA2_CH3_NUMBER 59 +#define STM32_DMA2_CH4_NUMBER 60 +#define STM32_DMA2_CH5_NUMBER 68 +#define STM32_DMA2_CH6_NUMBER 69 +#define STM32_DMA2_CH7_NUMBER 70 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_LINES 23 +#define STM32_EXTI_IMR_MASK 0x00000000U + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOI TRUE +#define STM32_HAS_GPIOJ TRUE +#define STM32_HAS_GPIOK TRUE + +#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \ + RCC_AHB1ENR_GPIOBEN | \ + RCC_AHB1ENR_GPIOCEN | \ + RCC_AHB1ENR_GPIODEN | \ + RCC_AHB1ENR_GPIOEEN | \ + RCC_AHB1ENR_GPIOFEN | \ + RCC_AHB1ENR_GPIOGEN | \ + RCC_AHB1ENR_GPIOHEN | \ + RCC_AHB1ENR_GPIOIEN | \ + RCC_AHB1ENR_GPIOJEN | \ + RCC_AHB1ENR_GPIOKEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C1_RX_DMA_CHN 0x00100001 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x11000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C2_RX_DMA_CHN 0x00007700 +#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_I2C2_TX_DMA_CHN 0x70000000 + +#define STM32_HAS_I2C3 TRUE +#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_I2C3_RX_DMA_CHN 0x00000300 +#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_I2C3_TX_DMA_CHN 0x00030000 + +#define STM32_HAS_I2C4 FALSE + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE +#define STM32_RTC_NUM_ALARMS 2 +#define STM32_RTC_HAS_INTERRUPTS FALSE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO TRUE +#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SDC_SDIO_DMA_CHN 0x04004000 + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S FALSE +#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_SPI1_RX_DMA_CHN 0x00000303 +#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI1_TX_DMA_CHN 0x00303000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S TRUE +#define STM32_SPI2_I2S_FULLDUPLEX TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_SUPPORTS_I2S TRUE +#define STM32_SPI3_I2S_FULLDUPLEX TRUE +#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ + STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI4 TRUE +#define STM32_SPI4_SUPPORTS_I2S FALSE +#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_SPI4_RX_DMA_CHN 0x00005004 +#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_SPI4_TX_DMA_CHN 0x00050040 + +#define STM32_HAS_SPI5 TRUE +#define STM32_SPI5_SUPPORTS_I2S FALSE +#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI5_RX_DMA_CHN 0x00702000 +#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SPI5_TX_DMA_CHN 0x07020000 + +#define STM32_HAS_SPI6 TRUE +#define STM32_SPI6_SUPPORTS_I2S FALSE +#define STM32_SPI6_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6) +#define STM32_SPI6_RX_DMA_CHN 0x01000000 +#define STM32_SPI6_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5) +#define STM32_SPI6_TX_DMA_CHN 0x00100000 + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 4 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 4 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 + +#define STM32_HAS_TIM5 TRUE +#define STM32_TIM5_IS_32BITS TRUE +#define STM32_TIM5_CHANNELS 4 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 + +#define STM32_HAS_TIM8 TRUE +#define STM32_TIM8_IS_32BITS FALSE +#define STM32_TIM8_CHANNELS 4 + +#define STM32_HAS_TIM9 TRUE +#define STM32_TIM9_IS_32BITS FALSE +#define STM32_TIM9_CHANNELS 2 + +#define STM32_HAS_TIM10 TRUE +#define STM32_TIM10_IS_32BITS FALSE +#define STM32_TIM10_CHANNELS 1 + +#define STM32_HAS_TIM11 TRUE +#define STM32_TIM11_IS_32BITS FALSE +#define STM32_TIM11_CHANNELS 1 + +#define STM32_HAS_TIM12 TRUE +#define STM32_TIM12_IS_32BITS FALSE +#define STM32_TIM12_CHANNELS 2 + +#define STM32_HAS_TIM13 TRUE +#define STM32_TIM13_IS_32BITS FALSE +#define STM32_TIM13_CHANNELS 1 + +#define STM32_HAS_TIM14 TRUE +#define STM32_TIM14_IS_32BITS FALSE +#define STM32_TIM14_CHANNELS 1 + +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00400400 +#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) +#define STM32_USART1_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_USART2_RX_DMA_CHN 0x00400000 +#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) +#define STM32_USART2_TX_DMA_CHN 0x04000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) +#define STM32_USART3_RX_DMA_CHN 0x00000040 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART3_TX_DMA_CHN 0x00074000 + +#define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_UART4_RX_DMA_CHN 0x00000400 +#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_UART4_TX_DMA_CHN 0x00040000 + +#define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) +#define STM32_UART5_RX_DMA_CHN 0x00000004 +#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_UART5_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART6 TRUE +#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_USART6_RX_DMA_CHN 0x00000550 +#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\ + STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART6_TX_DMA_CHN 0x55000000 + +#define STM32_HAS_UART7 TRUE +#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_UART7_RX_DMA_CHN 0x00004000 +#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) +#define STM32_UART7_TX_DMA_CHN 0x00000050 + +#define STM32_HAS_UART8 TRUE +#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) +#define STM32_UART8_RX_DMA_CHN 0x05000000 +#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) +#define STM32_UART8_TX_DMA_CHN 0x00000005 +#define STM32_HAS_LPUART1 FALSE + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 TRUE +#define STM32_HAS_OTG2 TRUE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED FALSE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC TRUE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D TRUE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC TRUE +#define STM32_FSMC_IS_FMC TRUE +#define STM32_FSMC_HANDLER Vector100 +#define STM32_FSMC_NUMBER 48 + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE FALSE + +#endif /* defined(STM32F469_479xx) */ + /*===========================================================================*/ /* STM32F446xx. */ /*===========================================================================*/