Fixed bug 3575297.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4750 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
gdisirio 2012-10-13 09:24:17 +00:00
parent 61650db8e5
commit 3cc94a9621
3 changed files with 10 additions and 4 deletions

View File

@ -174,8 +174,6 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
*/
void adc_lld_init(void) {
ADC->CCR = STM32_ADC_ADCPRE;
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
@ -270,6 +268,10 @@ void adc_lld_start(ADCDriver *adcp) {
}
#endif /* STM32_ADC_USE_ADC3 */
/* This is a common register but apparently it requires that at least one
of the ADCs is clocked in order to allow writing, see bug 3575297.*/
ADC->CCR = STM32_ADC_ADCPRE << 16;
/* ADC initial setup, starting the analog part here in order to reduce
the latency when starting a conversion.*/
adcp->adc->CR1 = 0;

View File

@ -174,8 +174,6 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
*/
void adc_lld_init(void) {
ADC->CCR = STM32_ADC_ADCPRE;
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
@ -270,6 +268,10 @@ void adc_lld_start(ADCDriver *adcp) {
}
#endif /* STM32_ADC_USE_ADC3 */
/* This is a common register but apparently it requires that at least one
of the ADCs is clocked in order to allow writing, see bug 3575297.*/
ADC->CCR = STM32_ADC_ADCPRE << 16;
/* ADC initial setup, starting the analog part here in order to reduce
the latency when starting a conversion.*/
adcp->adc->CR1 = 0;

View File

@ -83,6 +83,8 @@
*****************************************************************************
*** 2.5.1 ***
- FIX: Fixed STM32F4 ADC prescaler incorrectly initialized (bug 3575297)
(backported to 2.4.3).
- FIX: Fixed RCC_APB2ENR_IOPEEN undeclared on STM32F10X_LD_VL devices (bug
3575098)(backported to 2.4.3).
- FIX: Fixed misplaced declarations in lwip_bindings sys_arch.c (bug 3571053)