Fixed bug 3575297.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4750 35acf78f-673a-0410-8e92-d51de3d6d3f4master
parent
61650db8e5
commit
3cc94a9621
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@ -174,8 +174,6 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
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*/
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void adc_lld_init(void) {
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ADC->CCR = STM32_ADC_ADCPRE;
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#if STM32_ADC_USE_ADC1
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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@ -270,6 +268,10 @@ void adc_lld_start(ADCDriver *adcp) {
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}
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#endif /* STM32_ADC_USE_ADC3 */
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/* This is a common register but apparently it requires that at least one
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of the ADCs is clocked in order to allow writing, see bug 3575297.*/
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ADC->CCR = STM32_ADC_ADCPRE << 16;
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/* ADC initial setup, starting the analog part here in order to reduce
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the latency when starting a conversion.*/
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adcp->adc->CR1 = 0;
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@ -174,8 +174,6 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
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*/
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void adc_lld_init(void) {
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ADC->CCR = STM32_ADC_ADCPRE;
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#if STM32_ADC_USE_ADC1
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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@ -270,6 +268,10 @@ void adc_lld_start(ADCDriver *adcp) {
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}
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#endif /* STM32_ADC_USE_ADC3 */
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/* This is a common register but apparently it requires that at least one
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of the ADCs is clocked in order to allow writing, see bug 3575297.*/
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ADC->CCR = STM32_ADC_ADCPRE << 16;
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/* ADC initial setup, starting the analog part here in order to reduce
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the latency when starting a conversion.*/
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adcp->adc->CR1 = 0;
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@ -83,6 +83,8 @@
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*****************************************************************************
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*** 2.5.1 ***
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- FIX: Fixed STM32F4 ADC prescaler incorrectly initialized (bug 3575297)
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(backported to 2.4.3).
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- FIX: Fixed RCC_APB2ENR_IOPEEN undeclared on STM32F10X_LD_VL devices (bug
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3575098)(backported to 2.4.3).
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- FIX: Fixed misplaced declarations in lwip_bindings sys_arch.c (bug 3571053)
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