Improved preemption for Cortex-M0 port.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2797 35acf78f-673a-0410-8e92-d51de3d6d3f4master
gdisirio
parent
645fce5f28
commit
3cc5ac6d9a
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@ -126,7 +126,7 @@ Settings: CLK=48, (2 wait states)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.8 (Benchmark, round robin context switching)
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--- Score : 253328 ctxswc/S
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--- Score : 253332 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.9 (Benchmark, I/O Queues throughput)
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@ -27,11 +27,6 @@
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#include "ch.h"
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/**
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* @brief PC register temporary storage.
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*/
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regarm_t _port_saved_pc;
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/**
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* @brief System Timer vector.
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* @details This interrupt is used as system tick.
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@ -48,40 +43,39 @@ CH_IRQ_HANDLER(SysTickVector) {
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief NMI vector.
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* @details The NMI vector is used for exception mode re-entering after a
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* context switch.
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*/
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void NMIVector(void) {
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register struct extctx *ctxp;
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/* Discarding the current exception context and positioning the stack to
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point to the real one.*/
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asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
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ctxp++;
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asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
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port_unlock_from_isr();
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}
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/**
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* @brief Post-IRQ switch code.
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* @details On entry the stack and the registers are restored by the exception
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* return, the PC value is stored in @p _port_saved_pc, the interrupts
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* are disabled.
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* @details The switch is performed in thread context then an NMI exception
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* is enforced in order to return to the exact point before the
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* preemption.
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*/
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#if !defined(__DOXYGEN__)
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__attribute__((naked))
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#endif
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void _port_switch_from_isr(void) {
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/* Note, saves r4 to make space for the PC.*/
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asm volatile ("push {r0, r1, r2, r3, r4} \n\t"
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"mrs r0, APSR \n\t"
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"mov r1, r12 \n\t"
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"push {r0, r1, lr} \n\t"
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"ldr r0, =_port_saved_pc \n\t"
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"ldr r0, [r0] \n\t"
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"add r0, r0, #1 \n\t"
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"str r0, [sp, #28]" : : : "memory");
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chSchDoRescheduleI();
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/* Note, the last register is restored alone after re-enabling the
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interrupts in order to minimize the (very remote and unlikely)
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possibility that the stack is filled by continuous and saturating
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interrupts that would not allow that last words to be pulled out of
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the stack.*/
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asm volatile ("pop {r0, r1, r2} \n\t"
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"mov r12, r1 \n\t"
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"msr APSR, r0 \n\t"
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"mov lr, r2 \n\t"
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"pop {r0, r1, r2, r3} \n\t"
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"cpsie i \n\t"
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"pop {pc}" : : : "memory");
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SCB_ICSR = ICSR_NMIPENDSET;
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/* The following loop should never be executed, the NMI will kick in
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immediately.*/
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while (TRUE)
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;
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}
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#define PUSH_CONTEXT(sp) { \
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@ -32,10 +32,8 @@
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/* Port implementation part. */
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/*===========================================================================*/
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/**
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* @brief Cortex-Mx exception context.
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*/
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struct cmxctx {
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#if !defined(__DOXYGEN__)
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struct extctx {
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regarm_t r0;
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regarm_t r1;
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regarm_t r2;
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@ -46,18 +44,6 @@ struct cmxctx {
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regarm_t xpsr;
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};
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#if !defined(__DOXYGEN__)
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struct extctx {
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regarm_t xpsr;
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regarm_t r12;
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regarm_t lr;
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regarm_t r0;
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regarm_t r1;
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regarm_t r2;
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regarm_t r3;
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regarm_t pc;
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};
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struct intctx {
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regarm_t r8;
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regarm_t r9;
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@ -131,11 +117,17 @@ struct intctx {
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if (_saved_lr != (regarm_t)0xFFFFFFF1) { \
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port_lock_from_isr(); \
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if (chSchIsRescRequiredExI()) { \
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register struct cmxctx *ctxp; \
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register struct extctx *ctxp; \
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\
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asm volatile ("mrs %0, PSP" : "=r" (ctxp) : ); \
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_port_saved_pc = ctxp->pc; \
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/* Adding an artificial exception return context, there is no need to \
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populate it fully.*/ \
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asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); \
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ctxp--; \
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asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); \
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ctxp->pc = _port_switch_from_isr; \
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ctxp->xpsr = (regarm_t)0x01000000; \
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/* Note, returning without unlocking is intentional, this is done in \
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order to keep the rest of the context switching atomic.*/ \
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return; \
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} \
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port_unlock_from_isr(); \
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@ -84,6 +84,9 @@
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2.2.1).
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- FIX: Error in MAC driver (bug 3179783)(backported to 2.2.1).
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- FIX: Fixed wrong serial driver macros (bug 3173336)(backported to 2.2.1).
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- NEW: Inproved preemption implementation for the Cortex-M0, now it uses
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the NMI vector in order to restore the original context. The change makes
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IRQ handling faster and also saves some RAM/ROM space (backported to 2.2.3).
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- NEW: Added "IRQ STORM" long duration tests for the STM32 and LPC11xx. The
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test demonstrates the system stability in a thread-intensive, progressively
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CPU-saturating, IRQ-intensive long duration test.
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