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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5423 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-03-13 13:07:43 +00:00
parent 68c2e740e8
commit 3670cd18fa
13 changed files with 2100 additions and 8 deletions
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57
boards/GENERIC_SPC564A/board.c Normal file
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/*
* Licensed under ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/* Initial setup of all defined pads, the list is terminated by a {0, 0, 0}.*/
static const spc_siu_init_t spc_siu_init[] = {
{PCR(PORT5, P5_ESCI_A_TX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
{PCR(PORT5, P5_ESCI_A_RX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
{PCR(PORT11, P11_BUTTON1), PAL_LOW, PAL_MODE_INPUT},
{PCR(PORT11, P11_BUTTON2), PAL_LOW, PAL_MODE_INPUT},
{PCR(PORT11, P11_BUTTON3), PAL_LOW, PAL_MODE_INPUT},
{PCR(PORT11, P11_BUTTON4), PAL_LOW, PAL_MODE_INPUT},
{PCR(PORT11, P11_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
{PCR(PORT11, P11_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
{PCR(PORT11, P11_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
{PCR(PORT11, P11_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
{0, 0, 0}
};
/**
* @brief PAL setup.
*/
const PALConfig pal_default_config = {
spc_siu_init
};
#endif
/*
* Early initialization code.
* This initialization must be performed just after stack setup and before
* any other initialization.
*/
void __early_init(void) {
spc_clock_init();
}
/*
* Board-specific initialization code.
*/
void boardInit(void) {
}

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boards/GENERIC_SPC564A/board.h Normal file
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/*
* Licensed under ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for a generic SPC563Mxx proto board.
*/
/*
* Board identifiers.
*/
#define BOARD_GENERIC_SPC564A
#define BOARD_NAME "Generic SPC564Axx"
/*
* Board frequencies.
*/
#if !defined(SPC5_XOSC_CLK)
#define SPC5_XOSC_CLK 8000000
#endif
/*
* I/O definitions.
*/
#define P5_ESCI_A_TX 9
#define P5_ESCI_A_RX 10
#define P11_BUTTON1 3
#define P11_BUTTON2 5
#define P11_BUTTON3 7
#define P11_BUTTON4 9
#define P11_LED1 12
#define P11_LED2 13
#define P11_LED3 14
#define P11_LED4 15
/*
* Support macros.
*/
#define PCR(port, pin) (((port) * 16) + (pin))
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

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boards/GENERIC_SPC564A/board.mk Normal file
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# List of all the board related files.
BOARDSRC = ${CHIBIOS}/boards/GENERIC_SPC564A/board.c
# Required include directories
BOARDINC = ${CHIBIOS}/boards/GENERIC_SPC564A

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demos/PPC-SPC564A-GCC/Makefile Normal file
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##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data.
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# If enabled, this option allows to compile the application in VLE mode.
ifeq ($(USE_VLE),)
USE_VLE = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
#
# Build global options
##############################################################################
##############################################################################
# Project, sources and paths
#
# Define project name here
PROJECT = ch
# Imported source files
CHIBIOS = ../..
include $(CHIBIOS)/boards/GENERIC_SPC564A/board.mk
include $(CHIBIOS)/os/hal/platforms/SPC564Axx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/PPC/SPC564Axx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/SPC564A80.ld
# C sources here.
CSRC = $(PORTSRC) \
$(KERNSRC) \
$(TESTSRC) \
$(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
$(CHIBIOS)/os/various/evtimer.c \
$(CHIBIOS)/os/various/shell.c \
$(CHIBIOS)/os/various/chprintf.c \
main.c
# C++ sources here.
CPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM)
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \
$(CHIBIOS)/os/various
#
# Project, sources and paths
##############################################################################
##############################################################################
# Compiler settings
#
#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames
MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames
#TRGT = powerpc-eabi-
TRGT = ppc-vle-
CC = $(TRGT)gcc
CPPC = $(TRGT)g++
# Enable loading with g++ only if you need C++ runtime support.
# NOTE: You can use C++ even without C++ support if you are careful. C++
# runtime support makes code size explode.
LD = $(TRGT)gcc
#LD = $(TRGT)g++
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
OD = $(TRGT)objdump
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
# Define C warning options here
CWARN = -Wall -Wextra -Wstrict-prototypes
# Define C++ warning options here
CPPWARN = -Wall -Wextra
#
# Compiler settings
##############################################################################
##############################################################################
# Start of default section
#
# List all default C defines here, like -D_DEBUG=1
DDEFS =
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =
# List all default directories to look for include files here
DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
DLIBS =
#
# End of default section
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user defines
##############################################################################
include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk

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demos/PPC-SPC564A-GCC/UDE/__connection_failed_report__Controller0_Core.txt Normal file
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----------------------------------------------------------
Connection Failed Report from
Basic UDE Target Interface, Version: 1.10.4
created: 03/05/13, 10:41:20
----------------------------------------------------------
Windows version:
WinXP (Service Pack 3)
Admin: yes
UDE version:
Release: 3.03.05
Build: 2517
Path: C:\Program Files\pls\UDE 4.0
Target configuration file:
C:\ChibiStudio\chibios\demos\PPC-SPC563M-GCC\UDE\stm_xpc563m64_minimodule_debug_jtag.cfg
Error messages:
PpcJtagTargIntf: Can't connect target !
PpcJtagTargIntf: Failed to open communication channel !
UAD2CommDev: Can't connect Universal Access Device 2 !
Please check:
- Power supply of UAD2
- Communication cable to UAD2
Settings:
PortType: CommDev
CommDevSel: PortType=USB,Type=UAD2
JtagViaPod: y
TargetPort: Default
JtagTapNumber: 0
JtagNumOfTaps: 1
JtagNumIrBefore: 0
JtagNumIrAfter: 0
MaxJtagClk: 1000
AdaptiveJtagPhaseShift: y
JtagMuxPort: -1
JtagMuxWaitTime: 5
JtagIoType: Jtag
EtksArbiterMode: 0
ConnOption: Reset
UseExtReset: y
ResetWaitTime: 50
HaltAfterReset: y
ChangeJtagClk: -1
ExecInitCmds: y
InvalidateCache: n
ChangeMsr: n
ChangeMsrValue: 0x00000000
ResetPulseLen: 10
InitScript Script:
// TLB invalidate
SETSPR 0x3F4 0x2 0xFFFFFFFF
// select TLB 1
SETSPR 0x274 0x10000108 0xFFFFFFFF
// programm peripheral B modules
// TLB 1, entry 0
SETSPR 0x270 0x10000000 0xFFFFFFFF
// Valid, protect against invalidation, global entry, size=1MB
SETSPR 0x271 0xC0000500 0xFFFFFFFF
// effective page number FFF00000, I,G
SETSPR 0x272 0xFFF0000A 0xFFFFFFFF
// real page FFF00000, UX,SX,UW,SW,UR,SR
SETSPR 0x273 0xFFF0003F 0xFFFFFFFF
// execute TLB write instruction
EXECOPCODE 0x7C0007A4
// programm internal Flash, no cache because of flash
// TLB 1, entry 1
SETSPR 0x270 0x10010000 0xFFFFFFFF
// Valid, protect against invalidation, global entry, size=16MB
SETSPR 0x271 0xC0000700 0xFFFFFFFF
// effective page number 00000000
SETSPR 0x272 0x28 0xFFFFFFFF
// real page 00000000, UX,SX,UW,SW,UR,SR
SETSPR 0x273 0x3F 0xFFFFFFFF
// execute TLB write instruction
EXECOPCODE 0x7C0007A4
// programm internal SRAM
// TLB 1, entry 2
SETSPR 0x270 0x10020000 0xFFFFFFFF
// Valid, protect against invalidation, global entry, size=256k
SETSPR 0x271 0xC0000400 0xFFFFFFFF
// effective page number 40000000, I
SETSPR 0x272 0x40000028 0xFFFFFFFF
// real page 0x40000028, UX,SX,UW,SW,UR,SR
SETSPR 0x273 0x4000003F 0xFFFFFFFF
// execute TLB write instruction
EXECOPCODE 0x7C0007A4
// programm peripheral A modules
// TLB 1, entry 4
SETSPR 0x270 0x10030000 0xFFFFFFFF
// Valid, protect against invalidation, global entry, size=1MB
SETSPR 0x271 0xC0000500 0xFFFFFFFF
// effective page number C3F00000, I
SETSPR 0x272 0xC3F0000A 0xFFFFFFFF
// real page C3F00000, UX,SX,UW,SW,UR,SR
SETSPR 0x273 0xC3F0003F 0xFFFFFFFF
// execute TLB write instruction
EXECOPCODE 0x7C0007A4
// setup IVOPR
// points to internal memory at 0x40000000
SETSPR 0x3F 0x40000000 0xFFFFFFFF
// MMU data error vector offset
SETSPR 0x19D 0x0 0xFFFFFFFF
// MMU instruction error vector offset
// setup clock to 80MHz
//SET FMPLL_SYNCR 0x28000000 0xFFFFFFFF
//WAIT 0x5
// disable watchdog
SET SWT_CR 0xFF00000A
// set NEXUS priority to above cpu instruction for runtime access
//SET XBAR_MPR3 0x321
SimioAddr: g_JtagSimioAccess
FreezeTimers: y
AllowMmuSetup: y
ExecOnStartCmds: n
OnStartScript Script:
ExecOnHaltCmds: n
ExecOnHaltCmdsWhileHalted: n
OnHaltScript Script:
Script is empty
EnableProgramTimeMeasurement: n
TimerForPTM: Default
DefUserStreamChannel: 0
DontUseCachedRegisters: n
AllowBreakOnUpdateBreakpoints: n
ClearDebugStatusOnHalt: y
UseRestartWhileRunningHandling: n
UseNexus: y
DoSramInit: y
ForceCacheFlush: n
IgnoreLockedLines: n
HandleWdtBug: n
ForceEndOfReset: n
UseHwResetMode: y
HwResetMode: Execute
HandleNexusAccessBug: n
UseMasterNexusIfResetState: y
UseLocalAddressTranslation: y
Use64BitNexus: n
InitSramOnlyWhenNotInitialized: n
InvalidTlbOnReset: y
DoNotEnableTrapSwBrp: n
AllowResetOnCheck: n
BootPasswd0: 0xFEEDFACE
BootPasswd1: 0xCAFEBEEF
BootPasswd2: 0xFFFFFFFF
BootPasswd3: 0xFFFFFFFF
BootPasswd4: 0xFFFFFFFF
BootPasswd5: 0xFFFFFFFF
BootPasswd6: 0xFFFFFFFF
BootPasswd7: 0xFFFFFFFF
DisableE2EECC: n
IsUsedByTester: n
Mpc57xxClearPeripheralDebugAtNextCheckUserAppWhenRunning: n
JTAG target infos:
JTAG-ID: 0x00000000
UsedJtagClk: 0 kHz
ExtVoltage: 0.0 V
IntVoltageUsed: n
Target infos:
CoreName: Core
FullCoreName: Controller0.Core
ExtClock: 12000000
IntClock: 80000000
SysClock: 0
HasNexus: n
BigEndian: n
CanSimio: n
CanPhysicalAccess: n
HasSpe: n
NumOfSimioChannels: 0
JtagId: 0x00000000
IsEarlyStep: n
IsMaster: y
MasterCoreName:
IsMasterEnabled: y
IsSlave: n
BuddyDeviceDetected: n
EtkConnected: n
Data TLB size on target: 0x00000000
Instruction TLB size on target: 0x00000000
Shared TLB size on target: 0x00000000
Number of data TLB entries: 0x00000000
Number of instruction TLB entries: 0x00000000
Number of shared TLB entries: 0x00000000
Extended E200 MMU: n
E200 MPU: n
Data cache size: 0x00000000
Data cache ways: 0x00000000
Data cache sets: 0x00000000
Data cache entry size: 0x00000000
Instruction cache size: 0x00000000
Instruction cache ways: 0x00000000
Instruction cache sets: 0x00000000
Instruction cache entry size: 0x00000000
Unified Cache: n
MCM base address: 0xFFF40000
SIU base address: 0xC3F90000
Nexus On Slave: n
Core Number: 0
Has Wdt bug: n
Length of IR register: 0x00000005
Has Data Value comparators: y
Reset Mode: 0x00000002
STM timer base address: 0xFFF3C000
MC_ME base address: 0x00000000
Core in Lockstep mode: n
Core in DPM mode: n
Core is HSM: n
Target has Nexus access bug: n
Target has unlock JTAG capability: y
Unlock JTAG password len: 0x00000040
Has JTAG unlock enable bit: n
ExecuteOpcodeAddr: 0xFFFFC000
IMEMBaseAddr: 0xFFFFFFFF
IMEMSize: 0x00000000
DMEMBaseAddr: 0xFFFFFFFF
DMEMSize: 0x00000000
BootCodeStartAddr: 0xFFFFFFFC
HasCJtag: n
ChipJtagTapNumber: 0x00000000
ChipJtagTapNumber: 0x00000001
ChipJtagTapNumber: 0x00000000
ChipJtagTapNumber: 0x00000000
JtagChainType: UNKNOWN
JtagChainNumber: 0x00000000
PowerPc system type: MPC56XX
PowerPc synchonized GO type: NONE
InactiveAfterReset: n
Communication device:
Type/Firmware:
Serial Number: 0
Communication protocol handler:
LastCmd: 0x0000
LastResult: 0x0000
ExpBytes: 0 (0x0000)
RetBytes: 0 (0x0000)
LastTimeout: 0
Protocol diagnostic output:
Diagnostic output invalid !

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183
demos/PPC-SPC564A-GCC/UDE/stm_xpc563m64_minimodule_debug_jtag.cfg Normal file
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[Main]
Signature=UDE_TARGINFO_2.0
Description=STM XPC563M Mini Module with SPC563M64 1.5M (Jtag)
Description1=MMU preinitialized, memory mapping 1:1, VLE enabled for SRAM and Flash
Description2=PLL set for 80MHz
Description3=FLASH programming prepared but not enabled
Description4=Write Filter for BAM Module
MCUs=Controller0
Architecture=PowerPC
Vendor=STM
Board=XPC563M Mini Module
[Controller0]
Family=PowerPC
Type=SPC563M64
Enabled=1
IntClock=80000
MemDevs=BAMWriteFilter
ExtClock=12000
[Controller0.Core]
Protocol=PPCJTAG
Enabled=1
[Controller0.Core.LoadedAddOn]
UDEMemtool=1
[Controller0.Core.PpcJtagTargIntf]
PortType=UAD2
ResetWaitTime=50
MaxJtagClk=1000
DoSramInit=1
UseNexus=1
AdaptiveJtagPhaseShift=1
ConnOption=Reset
ChangeJtagClk=-1
HaltAfterReset=1
SimioAddr=g_JtagSimioAccess
FreezeTimers=1
InvalidTlbOnReset=1
InvalidateCache=0
ForceCacheFlush=0
IgnoreLockedLines=0
ExecInitCmds=1
JtagTapNumber=0
JtagNumOfTaps=1
JtagNumIrBefore=0
JtagNumIrAfter=0
SimioAddr=g_JtagSimioAccess
FlushCache=0
AllowMmuSetup=1
UseExtReset=1
HandleWdtBug=0
ForceEndOfReset=0
CommDevSel=PortType=USB,Type=UAD2
JtagViaPod=1
TargetPort=Default
ChangeMsr=0
ChangeMsrValue=0x0
ExecOnStartCmds=0
ExecOnHaltCmds=0
EnableProgramTimeMeasurement=0
UseHwResetMode=1
HandleNexusAccessBug=0
DoNotEnableTrapSwBrp=0
AllowResetOnCheck=0
BootPasswd0=0xFEEDFACE
BootPasswd1=0xCAFEBEEF
BootPasswd2=0xFFFFFFFF
BootPasswd3=0xFFFFFFFF
BootPasswd4=0xFFFFFFFF
BootPasswd5=0xFFFFFFFF
BootPasswd6=0xFFFFFFFF
BootPasswd7=0xFFFFFFFF
JtagIoType=Jtag
ExecOnHaltCmdsWhileHalted=0
TimerForPTM=Default
AllowBreakOnUpdateBreakpoints=0
ClearDebugStatusOnHalt=1
HwResetMode=Execute
UseMasterNexusIfResetState=1
UseLocalAddressTranslation=1
Use64BitNexus=0
InitSramOnlyWhenNotInitialized=0
DisableE2EECC=0
[Controller0.BAMWriteFilter]
Description=BAM WriteAccess Filter
Range0Start=0xFFFFC000
Range0Size=0x4000
Enabled=1
Handler=AccessFilter
Mode=ReadOnly
[Controller0.PFLASH0]
Enabled=1
EnableMemtoolByDefault=1
[Controller0.PFLASH1]
Enabled=1
EnableMemtoolByDefault=1
[Controller0.PFLASH2]
Enabled=1
EnableMemtoolByDefault=1
[Controller0.Core.PpcJtagTargIntf.InitScript]
// TLB invalidate
SETSPR 0x3F4 0x2 0xFFFFFFFF
// select TLB 1
SETSPR 0x274 0x10000108 0xFFFFFFFF
// programm peripheral B modules
// TLB 1, entry 0
SETSPR 0x270 0x10000000 0xFFFFFFFF
// Valid, protect against invalidation, global entry, size=1MB
SETSPR 0x271 0xC0000500 0xFFFFFFFF
// effective page number FFF00000, I,G
SETSPR 0x272 0xFFF0000A 0xFFFFFFFF
// real page FFF00000, UX,SX,UW,SW,UR,SR
SETSPR 0x273 0xFFF0003F 0xFFFFFFFF
// execute TLB write instruction
EXECOPCODE 0x7C0007A4
// programm internal Flash, no cache because of flash
// TLB 1, entry 1
SETSPR 0x270 0x10010000 0xFFFFFFFF
// Valid, protect against invalidation, global entry, size=16MB
SETSPR 0x271 0xC0000700 0xFFFFFFFF
// effective page number 00000000
SETSPR 0x272 0x28 0xFFFFFFFF
// real page 00000000, UX,SX,UW,SW,UR,SR
SETSPR 0x273 0x3F 0xFFFFFFFF
// execute TLB write instruction
EXECOPCODE 0x7C0007A4
// programm internal SRAM
// TLB 1, entry 2
SETSPR 0x270 0x10020000 0xFFFFFFFF
// Valid, protect against invalidation, global entry, size=256k
SETSPR 0x271 0xC0000400 0xFFFFFFFF
// effective page number 40000000, I
SETSPR 0x272 0x40000028 0xFFFFFFFF
// real page 0x40000028, UX,SX,UW,SW,UR,SR
SETSPR 0x273 0x4000003F 0xFFFFFFFF
// execute TLB write instruction
EXECOPCODE 0x7C0007A4
// programm peripheral A modules
// TLB 1, entry 4
SETSPR 0x270 0x10030000 0xFFFFFFFF
// Valid, protect against invalidation, global entry, size=1MB
SETSPR 0x271 0xC0000500 0xFFFFFFFF
// effective page number C3F00000, I
SETSPR 0x272 0xC3F0000A 0xFFFFFFFF
// real page C3F00000, UX,SX,UW,SW,UR,SR
SETSPR 0x273 0xC3F0003F 0xFFFFFFFF
// execute TLB write instruction
EXECOPCODE 0x7C0007A4
// setup IVOPR
// points to internal memory at 0x40000000
SETSPR 0x3F 0x40000000 0xFFFFFFFF
// MMU data error vector offset
SETSPR 0x19D 0x0 0xFFFFFFFF
// MMU instruction error vector offset
// setup clock to 80MHz
//SET FMPLL_SYNCR 0x28000000 0xFFFFFFFF
//WAIT 0x5
// disable watchdog
SET SWT_CR 0xFF00000A
// set NEXUS priority to above cpu instruction for runtime access
//SET XBAR_MPR3 0x321
[Controller0.Core.PpcJtagTargIntf.OnStartScript]
[Controller0.Core.PpcJtagTargIntf.OnHaltScript]

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000
#endif
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
*/
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE.
*/
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has
* then the responsibility to do one of the following:
* - Spawn a custom idle thread at priority @p IDLEPRIO.
* - Change the main() thread priority to @p IDLEPRIO then enter
* an endless loop. In this scenario the @p main() thread acts as
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES.
*/
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS.
*/
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS.
*/
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_MESSAGES.
*/
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE
#endif
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
* @p CH_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
*/
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_TRACE FALSE
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p TRUE.
* @note This debug option is defaulted to TRUE because it is required by
* some test cases into the test suite.
*/
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure.
*/
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
#endif
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \
}
#endif
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \
/* System tick event code here.*/ \
}
#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \
/* System halt code here.*/ \
}
#endif
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM FALSE
#endif
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <stdio.h>
#include "ch.h"
#include "hal.h"
#include "test.h"
#include "shell.h"
#include "chprintf.h"
#define SHELL_WA_SIZE THD_WA_SIZE(1024)
#define TEST_WA_SIZE THD_WA_SIZE(256)
static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) {
size_t n, size;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: mem\r\n");
return;
}
n = chHeapStatus(NULL, &size);
chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus());
chprintf(chp, "heap fragments : %u\r\n", n);
chprintf(chp, "heap free total : %u bytes\r\n", size);
}
static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) {
static const char *states[] = {THD_STATE_NAMES};
Thread *tp;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: threads\r\n");
return;
}
chprintf(chp, " addr stack prio refs state time\r\n");
tp = chRegFirstThread();
do {
chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n",
(uint32_t)tp, (uint32_t)tp->p_ctx.sp,
(uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1),
states[tp->p_state], (uint32_t)tp->p_time);
tp = chRegNextThread(tp);
} while (tp != NULL);
}
static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) {
Thread *tp;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: test\r\n");
return;
}
tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(),
TestThread, chp);
if (tp == NULL) {
chprintf(chp, "out of memory\r\n");
return;
}
chThdWait(tp);
}
static const ShellCommand commands[] = {
{"mem", cmd_mem},
{"threads", cmd_threads},
{"test", cmd_test},
{NULL, NULL}
};
static const ShellConfig shell_cfg1 = {
(BaseSequentialStream *)&SD1,
commands
};
/*
* LEDs blinker thread, times are in milliseconds.
*/
static WORKING_AREA(waThread1, 128);
static msg_t Thread1(void *arg) {
(void)arg;
chRegSetThreadName("blinker");
while (TRUE) {
palClearPad(PORT11, P11_LED1);
chThdSleepMilliseconds(100);
palClearPad(PORT11, P11_LED2);
chThdSleepMilliseconds(100);
palClearPad(PORT11, P11_LED3);
chThdSleepMilliseconds(100);
palClearPad(PORT11, P11_LED4);
chThdSleepMilliseconds(100);
palSetPad(PORT11, P11_LED1);
chThdSleepMilliseconds(100);
palSetPad(PORT11, P11_LED2);
chThdSleepMilliseconds(100);
palSetPad(PORT11, P11_LED3);
chThdSleepMilliseconds(100);
palSetPad(PORT11, P11_LED4);
chThdSleepMilliseconds(300);
}
return 0;
}
/*
* Application entry point.
*/
int main(void) {
Thread *shelltp = NULL;
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/*
* Activates the serial driver 1 using the driver default configuration.
*/
sdStart(&SD1, NULL);
/*
* Shell manager initialization.
*/
shellInit();
/*
* Creates the blinker thread.
*/
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
/*
* Normal main() thread activity.
*/
while (TRUE) {
if (!shelltp)
shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
else if (chThdTerminated(shelltp)) {
chThdRelease(shelltp); /* Recovers memory of the previous shell. */
shelltp = NULL; /* Triggers spawning of a new shell. */
}
chThdSleepMilliseconds(1000);
}
return 0;
}

64
demos/PPC-SPC564A-GCC/mcuconf.h Normal file
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@ -0,0 +1,64 @@
/*
* Licensed under ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* SPC563Mxx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 1...15 Lowest...Highest.
*/
#define SPC564Axx_MCUCONF
/*
* HAL driver system settings.
*/
#define SPC5_NO_INIT FALSE
#define SPC5_CLK_BYPASS FALSE
#define SPC5_ALLOW_OVERCLOCK FALSE
#define SPC5_CLK_PREDIV_VALUE 2
#define SPC5_CLK_MFD_VALUE 150
#define SPC5_CLK_RFD SPC5_RFD_DIV4
#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \
BIUCR_MASTER4_PREFETCH | \
BIUCR_MASTER0_PREFETCH | \
BIUCR_DPFEN | \
BIUCR_IPFEN | \
BIUCR_PFLIM_ON_MISS | \
BIUCR_BFEN)
/*
* ADC driver settings.
*/
#define SPC5_ADC_USE_ADC0_Q0 FALSE
#define SPC5_ADC_USE_ADC0_Q1 FALSE
#define SPC5_ADC_USE_ADC0_Q2 FALSE
#define SPC5_ADC_USE_ADC1_Q3 FALSE
#define SPC5_ADC_USE_ADC1_Q4 FALSE
#define SPC5_ADC_USE_ADC1_Q5 FALSE
#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5)
/*
* SERIAL driver system settings.
*/
#define SPC5_USE_ESCIA TRUE
#define SPC5_USE_ESCIB TRUE
#define SPC5_USE_ESCIC TRUE
#define SPC5_ESCIA_PRIORITY 8
#define SPC5_ESCIB_PRIORITY 8
#define SPC5_ESCIC_PRIORITY 8

8
os/hal/platforms/SPC563Mxx/hal_lld.h
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@ -106,7 +106,7 @@
* @brief Disables the clocks initialization in the HAL.
*/
#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
#define SPC5_NO_INIT FALSE
#define SPC5_NO_INIT FALSE
#endif
/**
@ -116,14 +116,14 @@
* are ignored.
*/
#if !defined(SPC5_CLK_BYPASS) || defined(__DOXYGEN__)
#define SPC5_CLK_BYPASS FALSE
#define SPC5_CLK_BYPASS FALSE
#endif
/**
* @brief Disables the overclock checks.
*/
#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
#define SPC5_ALLOW_OVERCLOCK FALSE
#define SPC5_ALLOW_OVERCLOCK FALSE
#endif
/**
@ -132,7 +132,7 @@
* @note The effective divider factor is this value.
*/
#if !defined(SPC5_CLK_PREDIV) || defined(__DOXYGEN__)
#define SPC5_CLK_PREDIV_VALUE 2
#define SPC5_CLK_PREDIV_VALUE 2
#endif
/**

8
os/hal/platforms/SPC564Axx/hal_lld.h
View File

@ -106,7 +106,7 @@
* @brief Disables the clocks initialization in the HAL.
*/
#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
#define SPC5_NO_INIT FALSE
#define SPC5_NO_INIT FALSE
#endif
/**
@ -116,14 +116,14 @@
* are ignored.
*/
#if !defined(SPC5_CLK_BYPASS) || defined(__DOXYGEN__)
#define SPC5_CLK_BYPASS FALSE
#define SPC5_CLK_BYPASS FALSE
#endif
/**
* @brief Disables the overclock checks.
*/
#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
#define SPC5_ALLOW_OVERCLOCK FALSE
#define SPC5_ALLOW_OVERCLOCK FALSE
#endif
/**
@ -132,7 +132,7 @@
* @note The effective divider factor is this value.
*/
#if !defined(SPC5_CLK_PREDIV) || defined(__DOXYGEN__)
#define SPC5_CLK_PREDIV_VALUE 2
#define SPC5_CLK_PREDIV_VALUE 2
#endif
/**