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Fixed bugs 3534767, 3534819, 3535887 and 3535938. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4293 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
gdisirio 2012-06-18 08:52:26 +00:00
parent fa2cedd0d0
commit 3626647d7b
11 changed files with 52 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
boards/ST_STM32F4_DISCOVERY/board.h
View File

@ -259,7 +259,7 @@
PIN_PUDR_PULLUP(14) | \
PIN_PUDR_PULLUP(15))
#define VAL_GPIOC_ODR 0xFFFFFFFF
#define VAL_GPIOC_AFRL PIN_AFIO_AF(GPIOC_MCLK, 6))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_MCLK, 6))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SCLK, 6) | \
PIN_AFIO_AF(GPIOC_SDIN, 6))

6
os/hal/include/adc.h
View File

@ -210,7 +210,8 @@ typedef enum {
if ((adcp)->depth > 1) { \
/* Invokes the callback passing the 2nd half of the buffer.*/ \
size_t half = (adcp)->depth / 2; \
(adcp)->grpp->end_cb(adcp, (adcp)->samples + half, half); \
size_t half_index = half * (adcp)->grpp->num_channels; \
(adcp)->grpp->end_cb(adcp, (adcp)->samples + half_index, half); \
} \
else { \
/* Invokes the callback passing the whole buffer.*/ \
@ -226,7 +227,8 @@ typedef enum {
if ((adcp)->depth > 1) { \
/* Invokes the callback passing the 2nd half of the buffer.*/ \
size_t half = (adcp)->depth / 2; \
(adcp)->grpp->end_cb(adcp, (adcp)->samples + half, half); \
size_t half_index = half * (adcp)->grpp->num_channels; \
(adcp)->grpp->end_cb(adcp, (adcp)->samples + half_index, half); \
} \
else { \
/* Invokes the callback passing the whole buffer.*/ \

3
os/hal/platforms/STM32/mac_lld.c
View File

@ -265,6 +265,9 @@ void mac_lld_init(void) {
#else
/* PHY soft reset procedure.*/
mii_write(&ETHD1, MII_BMCR, BMCR_RESET);
#if defined(BOARD_PHY_RESET_DELAY)
halPolledDelay(BOARD_PHY_RESET_DELAY);
#endif
while (mii_read(&ETHD1, MII_BMCR) & BMCR_RESET)
;
#endif

34
os/hal/platforms/STM32/spi_lld.c
View File

@ -372,11 +372,14 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) {
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_EN);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
dmaStreamSetMemory0(spip->dmatx, &dummytx);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_EN);
dmaStreamSetMode(spip->dmatx, spip->txdmamode);
dmaStreamEnable(spip->dmarx);
dmaStreamEnable(spip->dmatx);
}
/**
@ -399,12 +402,14 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC |
STM32_DMA_CR_EN);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC);
dmaStreamSetMemory0(spip->dmatx, txbuf);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC |
STM32_DMA_CR_EN);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
dmaStreamEnable(spip->dmarx);
dmaStreamEnable(spip->dmatx);
}
/**
@ -424,12 +429,14 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_EN);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
dmaStreamSetMemory0(spip->dmatx, txbuf);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC |
STM32_DMA_CR_EN);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
dmaStreamEnable(spip->dmarx);
dmaStreamEnable(spip->dmatx);
}
/**
@ -449,11 +456,14 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC |
STM32_DMA_CR_EN);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
dmaStreamSetMemory0(spip->dmatx, &dummytx);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_EN);
dmaStreamSetMode(spip->dmatx, spip->txdmamode);
dmaStreamEnable(spip->dmarx);
dmaStreamEnable(spip->dmatx);
}
/**

4
os/hal/platforms/STM32F0xx/adc_lld.c
View File

@ -151,8 +151,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_EN;
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
/* The shared vector is initialized on driver initialization and never
@ -265,6 +264,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
(uint32_t)adcp->depth);
dmaStreamSetMode(adcp->dmastp, mode);
dmaStreamEnable(adcp->dmastp);
/* ADC setup, if it is defined a callback for the analog watch dog then it
is enabled.*/

3
os/hal/platforms/STM32F1xx/adc_lld.c
View File

@ -97,7 +97,7 @@ void adc_lld_init(void) {
ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_TEIE | STM32_DMA_CR_EN;
STM32_DMA_CR_TEIE;
/* Temporary activation.*/
rccEnableADC1(FALSE);
@ -199,6 +199,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
dmaStreamSetTransactionSize(adcp->dmastp, n);
dmaStreamSetMode(adcp->dmastp, mode);
dmaStreamEnable(adcp->dmastp);
/* ADC setup.*/
adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN;

10
os/hal/platforms/STM32F2xx/adc_lld.c
View File

@ -186,8 +186,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_EN;
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
#if STM32_ADC_USE_ADC2
@ -200,8 +199,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_EN;
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
#if STM32_ADC_USE_ADC3
@ -214,8 +212,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_EN;
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
/* The shared vector is initialized on driver initialization and never
@ -338,6 +335,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
(uint32_t)adcp->depth);
dmaStreamSetMode(adcp->dmastp, mode);
dmaStreamEnable(adcp->dmastp);
/* ADC setup.*/
adcp->adc->SR = 0;

10
os/hal/platforms/STM32F4xx/adc_lld.c
View File

@ -186,8 +186,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_EN;
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
#if STM32_ADC_USE_ADC2
@ -200,8 +199,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_EN;
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
#if STM32_ADC_USE_ADC3
@ -214,8 +212,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_EN;
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
/* The shared vector is initialized on driver initialization and never
@ -338,6 +335,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
(uint32_t)adcp->depth);
dmaStreamSetMode(adcp->dmastp, mode);
dmaStreamEnable(adcp->dmastp);
/* ADC setup.*/
adcp->adc->SR = 0;

4
os/hal/platforms/STM32L1xx/adc_lld.c
View File

@ -129,8 +129,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_EN;
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
/* The shared vector is initialized on driver initialization and never
@ -217,6 +216,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
(uint32_t)adcp->depth);
dmaStreamSetMode(adcp->dmastp, mode);
dmaStreamEnable(adcp->dmastp);
/* ADC setup.*/
adcp->adc->SR = 0;

4
os/hal/src/mmc_spi.c
View File

@ -423,13 +423,13 @@ void mmcObjectInit(MMCDriver *mmcp) {
* @brief Configures and activates the MMC peripheral.
*
* @param[in] mmcp pointer to the @p MMCDriver object
* @param[in] config pointer to the @p MMCConfig object. Must be @p NULL.
* @param[in] config pointer to the @p MMCConfig object.
*
* @api
*/
void mmcStart(MMCDriver *mmcp, const MMCConfig *config) {
chDbgCheck((mmcp != NULL) && (config == NULL), "mmcStart");
chDbgCheck((mmcp != NULL) && (config != NULL), "mmcStart");
chSysLock();
chDbgAssert(mmcp->state == MMC_STOP, "mmcStart(), #1", "invalid state");

6
readme.txt
View File

@ -81,6 +81,12 @@
*****************************************************************************
*** 2.5.0 ***
- FIX: Fixed issue with DMA channel init in STM32 ADC and SPI drivers (bug
3535938)(backported to 2.2.10 and 2.4.2).
- FIX: Fixed issue debugging mmc_spi (bug 3535887)(trunk only).
- FIX: Fixed unreliable PHY initialization (bug 3534819)(backported to 2.4.2).
- FIX: Fixed wrong ADC callback buffer pointer in ADC driver (bug 3534767)
(backported to 2.2.10 and 2.4.2).
- FIX: Fixed STM32F2 RTC subseconds (bug 3533414)(trunk only).
- FIX: Fixed problem with arm-v6m and state checker (bug 3532591)(backported
to 2.4.2).