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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6207 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-08-23 08:31:11 +00:00
parent b5dfe4685f
commit 32c2d2fca0
8 changed files with 234 additions and 209 deletions
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8
demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h
View File

@ -191,7 +191,7 @@
#define STM32_PWM_USE_TIM1 FALSE #define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 TRUE #define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE #define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE #define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM9 FALSE #define STM32_PWM_USE_TIM9 FALSE
@ -222,8 +222,8 @@
/* /*
* SPI driver system settings. * SPI driver system settings.
*/ */
#define STM32_SPI_USE_SPI1 TRUE #define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 TRUE #define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE #define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
@ -267,7 +267,7 @@
/* /*
* USB driver system settings. * USB driver system settings.
*/ */
#define STM32_USB_USE_OTG1 TRUE #define STM32_USB_USE_OTG1 FALSE
#define STM32_USB_USE_OTG2 FALSE #define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14 #define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14 #define STM32_USB_OTG2_IRQ_PRIORITY 14

20
os/hal/platforms/STM32F4xx/adc_lld.c
View File

@ -107,10 +107,10 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { OSAL_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
uint32_t sr; uint32_t sr;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
#if STM32_ADC_USE_ADC1 #if STM32_ADC_USE_ADC1
sr = ADC1->SR; sr = ADC1->SR;
@ -154,7 +154,7 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
/* TODO: Add here analog watchdog handling.*/ /* TODO: Add here analog watchdog handling.*/
#endif /* STM32_ADC_USE_ADC3 */ #endif /* STM32_ADC_USE_ADC3 */
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
#endif #endif
@ -210,7 +210,7 @@ void adc_lld_init(void) {
/* The shared vector is initialized on driver initialization and never /* The shared vector is initialized on driver initialization and never
disabled.*/ disabled.*/
nvicEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); nvicEnableVector(ADC_IRQn, STM32_ADC_IRQ_PRIORITY);
} }
/** /**
@ -226,12 +226,12 @@ void adc_lld_start(ADCDriver *adcp) {
if (adcp->state == ADC_STOP) { if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1 #if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) { if (&ADCD1 == adcp) {
bool_t b; bool b;
b = dmaStreamAllocate(adcp->dmastp, b = dmaStreamAllocate(adcp->dmastp,
STM32_ADC_ADC1_DMA_IRQ_PRIORITY, STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt, (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp); (void *)adcp);
chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
rccEnableADC1(FALSE); rccEnableADC1(FALSE);
} }
@ -239,12 +239,12 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC2 #if STM32_ADC_USE_ADC2
if (&ADCD2 == adcp) { if (&ADCD2 == adcp) {
bool_t b; bool b;
b = dmaStreamAllocate(adcp->dmastp, b = dmaStreamAllocate(adcp->dmastp,
STM32_ADC_ADC2_DMA_IRQ_PRIORITY, STM32_ADC_ADC2_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt, (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp); (void *)adcp);
chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR); dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR);
rccEnableADC2(FALSE); rccEnableADC2(FALSE);
} }
@ -252,12 +252,12 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC3 #if STM32_ADC_USE_ADC3
if (&ADCD3 == adcp) { if (&ADCD3 == adcp) {
bool_t b; bool b;
b = dmaStreamAllocate(adcp->dmastp, b = dmaStreamAllocate(adcp->dmastp,
STM32_ADC_ADC3_DMA_IRQ_PRIORITY, STM32_ADC_ADC3_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt, (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp); (void *)adcp);
chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR); dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR);
rccEnableADC3(FALSE); rccEnableADC3(FALSE);
} }

8
os/hal/platforms/STM32F4xx/adc_lld.h
View File

@ -437,17 +437,13 @@ struct ADCDriver {
/** /**
* @brief Waiting thread. * @brief Waiting thread.
*/ */
Thread *thread; thread_reference_t thread;
#endif #endif
#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) #if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
#if CH_USE_MUTEXES || defined(__DOXYGEN__)
/** /**
* @brief Mutex protecting the peripheral. * @brief Mutex protecting the peripheral.
*/ */
Mutex mutex; mutex_t mutex;
#elif CH_USE_SEMAPHORES
Semaphore semaphore;
#endif
#endif /* ADC_USE_MUTUAL_EXCLUSION */ #endif /* ADC_USE_MUTUAL_EXCLUSION */
#if defined(ADC_DRIVER_EXT_FIELDS) #if defined(ADC_DRIVER_EXT_FIELDS)
ADC_DRIVER_EXT_FIELDS ADC_DRIVER_EXT_FIELDS

106
os/hal/platforms/STM32F4xx/stm32_dma.c
View File

@ -124,17 +124,17 @@ static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) { OSAL_IRQ_HANDLER(Vector6C) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK; flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = STM32_DMA_ISR_MASK << 0; DMA1->LIFCR = STM32_DMA_ISR_MASK << 0;
if (dma_isr_redir[0].dma_func) if (dma_isr_redir[0].dma_func)
dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -142,17 +142,17 @@ CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) { OSAL_IRQ_HANDLER(Vector70) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK; flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = STM32_DMA_ISR_MASK << 6; DMA1->LIFCR = STM32_DMA_ISR_MASK << 6;
if (dma_isr_redir[1].dma_func) if (dma_isr_redir[1].dma_func)
dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -160,17 +160,17 @@ CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) { OSAL_IRQ_HANDLER(Vector74) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK; flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = STM32_DMA_ISR_MASK << 16; DMA1->LIFCR = STM32_DMA_ISR_MASK << 16;
if (dma_isr_redir[2].dma_func) if (dma_isr_redir[2].dma_func)
dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -178,17 +178,17 @@ CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) { OSAL_IRQ_HANDLER(Vector78) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK; flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = STM32_DMA_ISR_MASK << 22; DMA1->LIFCR = STM32_DMA_ISR_MASK << 22;
if (dma_isr_redir[3].dma_func) if (dma_isr_redir[3].dma_func)
dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -196,17 +196,17 @@ CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) { OSAL_IRQ_HANDLER(Vector7C) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK; flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = STM32_DMA_ISR_MASK << 0; DMA1->HIFCR = STM32_DMA_ISR_MASK << 0;
if (dma_isr_redir[4].dma_func) if (dma_isr_redir[4].dma_func)
dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -214,17 +214,17 @@ CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) { OSAL_IRQ_HANDLER(Vector80) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK; flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = STM32_DMA_ISR_MASK << 6; DMA1->HIFCR = STM32_DMA_ISR_MASK << 6;
if (dma_isr_redir[5].dma_func) if (dma_isr_redir[5].dma_func)
dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -232,17 +232,17 @@ CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) { OSAL_IRQ_HANDLER(Vector84) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK; flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = STM32_DMA_ISR_MASK << 16; DMA1->HIFCR = STM32_DMA_ISR_MASK << 16;
if (dma_isr_redir[6].dma_func) if (dma_isr_redir[6].dma_func)
dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -250,17 +250,17 @@ CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) { OSAL_IRQ_HANDLER(VectorFC) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK; flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = STM32_DMA_ISR_MASK << 22; DMA1->HIFCR = STM32_DMA_ISR_MASK << 22;
if (dma_isr_redir[7].dma_func) if (dma_isr_redir[7].dma_func)
dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -268,17 +268,17 @@ CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) { OSAL_IRQ_HANDLER(Vector120) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK; flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = STM32_DMA_ISR_MASK << 0; DMA2->LIFCR = STM32_DMA_ISR_MASK << 0;
if (dma_isr_redir[8].dma_func) if (dma_isr_redir[8].dma_func)
dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -286,17 +286,17 @@ CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) { OSAL_IRQ_HANDLER(Vector124) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK; flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = STM32_DMA_ISR_MASK << 6; DMA2->LIFCR = STM32_DMA_ISR_MASK << 6;
if (dma_isr_redir[9].dma_func) if (dma_isr_redir[9].dma_func)
dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -304,17 +304,17 @@ CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) { OSAL_IRQ_HANDLER(Vector128) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK; flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = STM32_DMA_ISR_MASK << 16; DMA2->LIFCR = STM32_DMA_ISR_MASK << 16;
if (dma_isr_redir[10].dma_func) if (dma_isr_redir[10].dma_func)
dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -322,17 +322,17 @@ CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) { OSAL_IRQ_HANDLER(Vector12C) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK; flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = STM32_DMA_ISR_MASK << 22; DMA2->LIFCR = STM32_DMA_ISR_MASK << 22;
if (dma_isr_redir[11].dma_func) if (dma_isr_redir[11].dma_func)
dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -340,17 +340,17 @@ CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) { OSAL_IRQ_HANDLER(Vector130) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK; flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = STM32_DMA_ISR_MASK << 0; DMA2->HIFCR = STM32_DMA_ISR_MASK << 0;
if (dma_isr_redir[12].dma_func) if (dma_isr_redir[12].dma_func)
dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags); dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -358,17 +358,17 @@ CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) { OSAL_IRQ_HANDLER(Vector150) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK; flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = STM32_DMA_ISR_MASK << 6; DMA2->HIFCR = STM32_DMA_ISR_MASK << 6;
if (dma_isr_redir[13].dma_func) if (dma_isr_redir[13].dma_func)
dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags); dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -376,17 +376,17 @@ CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) { OSAL_IRQ_HANDLER(Vector154) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK; flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = STM32_DMA_ISR_MASK << 16; DMA2->HIFCR = STM32_DMA_ISR_MASK << 16;
if (dma_isr_redir[14].dma_func) if (dma_isr_redir[14].dma_func)
dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags); dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/** /**
@ -394,17 +394,17 @@ CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) {
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) { OSAL_IRQ_HANDLER(Vector158) {
uint32_t flags; uint32_t flags;
CH_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK; flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = STM32_DMA_ISR_MASK << 22; DMA2->HIFCR = STM32_DMA_ISR_MASK << 22;
if (dma_isr_redir[15].dma_func) if (dma_isr_redir[15].dma_func)
dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags); dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags);
CH_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
/*===========================================================================*/ /*===========================================================================*/
@ -459,7 +459,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
stm32_dmaisr_t func, stm32_dmaisr_t func,
void *param) { void *param) {
chDbgCheck(dmastp != NULL, "dmaStreamAllocate"); osalDbgCheck(dmastp != NULL);
/* Checks if the stream is already taken.*/ /* Checks if the stream is already taken.*/
if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
@ -483,7 +483,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
/* Enables the associated IRQ vector if a callback is defined.*/ /* Enables the associated IRQ vector if a callback is defined.*/
if (func != NULL) if (func != NULL)
nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); nvicEnableVector(dmastp->vector, priority);
return FALSE; return FALSE;
} }
@ -503,11 +503,11 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
*/ */
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
chDbgCheck(dmastp != NULL, "dmaStreamRelease"); osalDbgCheck(dmastp != NULL);
/* Check if the streams is not taken.*/ /* Check if the streams is not taken.*/
chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
"dmaStreamRelease(), #1", "not allocated"); "not allocated");
/* Disables the associated IRQ vector.*/ /* Disables the associated IRQ vector.*/
nvicDisableVector(dmastp->vector); nvicDisableVector(dmastp->vector);

2
testhal/STM32F4xx/ADC/.project
View File

@ -27,7 +27,7 @@
<link> <link>
<name>board</name> <name>board</name>
<type>2</type> <type>2</type>
<locationURI>CHIBIOS/boards/ST_STM32F4_DISCOVERY</locationURI> <locationURI>CHIBIOS/os/hal/boards/ST_STM32F4_DISCOVERY</locationURI>
</link> </link>
<link> <link>
<name>os</name> <name>os</name>

19
testhal/STM32F4xx/ADC/Makefile
View File

@ -65,12 +65,13 @@ PROJECT = ch
# Imported source files and paths # Imported source files and paths
CHIBIOS = ../../.. CHIBIOS = ../../..
include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk include $(CHIBIOS)/os/hal/osal/chibios/osal.mk
include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk
include $(CHIBIOS)/test/test.mk include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/rt/ports/ARMCMx/devices/STM32F4xx/port.mk
#include $(CHIBIOS)/test/test.mk
# Define linker script file here # Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld LDSCRIPT= $(PORTLD)/STM32F407xG.ld
@ -82,9 +83,9 @@ CSRC = $(PORTSRC) \
$(KERNSRC) \ $(KERNSRC) \
$(TESTSRC) \ $(TESTSRC) \
$(HALSRC) \ $(HALSRC) \
$(OSALSRC) \
$(PLATFORMSRC) \ $(PLATFORMSRC) \
$(BOARDSRC) \ $(BOARDSRC) \
$(CHIBIOS)/os/various/chprintf.c \
main.c main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global # C++ sources that can be compiled in ARM or THUMB mode depending on the global
@ -115,7 +116,7 @@ TCPPSRC =
ASMSRC = $(PORTASM) ASMSRC = $(PORTASM)
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \ $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \
$(CHIBIOS)/os/various $(CHIBIOS)/os/various
# #
@ -208,8 +209,10 @@ ULIBS =
ifeq ($(USE_FPU),yes) ifeq ($(USE_FPU),yes)
USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
DDEFS += -DCORTEX_USE_FPU=TRUE DDEFS += -DCORTEX_USE_FPU=TRUE
DADEFS += -DCORTEX_USE_FPU=TRUE
else else
DDEFS += -DCORTEX_USE_FPU=FALSE DDEFS += -DCORTEX_USE_FPU=FALSE
DADEFS += -DCORTEX_USE_FPU=FALSE
endif endif
ifeq ($(USE_FWLIB),yes) ifeq ($(USE_FWLIB),yes)
@ -219,4 +222,4 @@ ifeq ($(USE_FWLIB),yes)
USE_OPT += -DUSE_STDPERIPH_DRIVER USE_OPT += -DUSE_STDPERIPH_DRIVER
endif endif
include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/rules.mk

261
testhal/STM32F4xx/ADC/chconf.h
View File

@ -40,8 +40,29 @@
* @details Frequency of the system timer that drives the system ticks. This * @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit. * setting also defines the system tick time unit.
*/ */
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #if !defined(CH_CFG_ST_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000 #define CH_CFG_ST_FREQUENCY 10000
#endif
/**
* @brief Realtime Counter frequency.
* @details Frequency of the system counter used for realtime delays and
* measurements.
*/
#if !defined(CH_CFG_RTC_FREQUENCY) || defined(__DOXYGEN__)
#define CH_CFG_RTC_FREQUENCY 168000000
#endif
/**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#if !defined(CH_CFG_TIMEDELTA) || defined(__DOXYGEN__)
#define CH_CFG_TIMEDELTA 2
#endif #endif
/** /**
@ -51,12 +72,13 @@
* disables the preemption for threads with equal priority and the * disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority * round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive. * threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact * @note Disabling the round robin preemption makes the kernel more compact
* and generally faster. * and generally faster.
* @note The round robin preemption is not supported in tickless mode and
* must be set to zero in that case.
*/ */
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #if !defined(CH_CFG_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20 #define CH_CFG_TIME_QUANTUM 0
#endif #endif
/** /**
@ -68,27 +90,20 @@
* *
* @note In order to let the OS manage the whole RAM the linker script must * @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols. * provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE. * @note Requires @p CH_CFG_USE_MEMCORE.
*/ */
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #if !defined(CH_CFG_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0 #define CH_CFG_MEMCORE_SIZE 0
#endif #endif
/** /**
* @brief Idle thread automatic spawn suppression. * @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit() * @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has * does not spawn the idle thread. The application @p main()
* then the responsibility to do one of the following: * function becomes the idle thread and must implement an
* - Spawn a custom idle thread at priority @p IDLEPRIO. * infinite loop. */
* - Change the main() thread priority to @p IDLEPRIO then enter #if !defined(CH_CFG_NO_IDLE_THREAD) || defined(__DOXYGEN__)
* an endless loop. In this scenario the @p main() thread acts as #define CH_CFG_NO_IDLE_THREAD FALSE
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif #endif
/** @} */ /** @} */
@ -108,8 +123,8 @@
* @note This is not related to the compiler optimization options. * @note This is not related to the compiler optimization options.
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #if !defined(CH_CFG_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE #define CH_CFG_OPTIMIZE_SPEED TRUE
#endif #endif
/** @} */ /** @} */
@ -121,14 +136,25 @@
*/ */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief Time Measurement APIs.
* @details If enabled then the time measurement APIs are included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_TM) || defined(__DOXYGEN__)
#define CH_CFG_USE_TM TRUE
#endif
/** /**
* @brief Threads registry APIs. * @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel. * @details If enabled then the registry APIs are included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE #define CH_CFG_USE_REGISTRY TRUE
#endif #endif
/** /**
@ -138,8 +164,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE #define CH_CFG_USE_WAITEXIT TRUE
#endif #endif
/** /**
@ -148,8 +174,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE #define CH_CFG_USE_SEMAPHORES TRUE
#endif #endif
/** /**
@ -157,23 +183,12 @@
* @details If enabled then the threads are enqueued on semaphores by * @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order. * priority rather than in FIFO order.
* *
* @note The default is @p FALSE. Enable this if you have special requirements. * @note The default is @p FALSE. Enable this if you have special
* @note Requires @p CH_USE_SEMAPHORES. * requirements.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/ */
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE #define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif #endif
/** /**
@ -182,8 +197,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE #define CH_CFG_USE_MUTEXES TRUE
#endif #endif
/** /**
@ -192,10 +207,10 @@
* in the kernel. * in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES. * @note Requires @p CH_CFG_USE_MUTEXES.
*/ */
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE #define CH_CFG_USE_CONDVARS TRUE
#endif #endif
/** /**
@ -204,10 +219,10 @@
* specification are included in the kernel. * specification are included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS. * @note Requires @p CH_CFG_USE_CONDVARS.
*/ */
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE #define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
#endif #endif
/** /**
@ -216,8 +231,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE #define CH_CFG_USE_EVENTS TRUE
#endif #endif
/** /**
@ -226,10 +241,10 @@
* are included in the kernel. * are included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS. * @note Requires @p CH_CFG_USE_EVENTS.
*/ */
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE #define CH_CFG_USE_EVENTS_TIMEOUT TRUE
#endif #endif
/** /**
@ -239,8 +254,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE #define CH_CFG_USE_MESSAGES TRUE
#endif #endif
/** /**
@ -248,11 +263,12 @@
* @details If enabled then messages are served by priority rather than in * @details If enabled then messages are served by priority rather than in
* FIFO order. * FIFO order.
* *
* @note The default is @p FALSE. Enable this if you have special requirements. * @note The default is @p FALSE. Enable this if you have special
* @note Requires @p CH_USE_MESSAGES. * requirements.
* @note Requires @p CH_CFG_USE_MESSAGES.
*/ */
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE #define CH_CFG_USE_MESSAGES_PRIORITY FALSE
#endif #endif
/** /**
@ -261,10 +277,10 @@
* included in the kernel. * included in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES. * @note Requires @p CH_CFG_USE_SEMAPHORES.
*/ */
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE #define CH_CFG_USE_MAILBOXES TRUE
#endif #endif
/** /**
@ -273,8 +289,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE #define CH_CFG_USE_QUEUES TRUE
#endif #endif
/** /**
@ -284,8 +300,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE #define CH_CFG_USE_MEMCORE TRUE
#endif #endif
/** /**
@ -294,26 +310,12 @@
* in the kernel. * in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
* @p CH_USE_SEMAPHORES. * @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended. * @note Mutexes are recommended.
*/ */
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE #define CH_CFG_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif #endif
/** /**
@ -323,8 +325,8 @@
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE #define CH_CFG_USE_MEMPOOLS TRUE
#endif #endif
/** /**
@ -333,11 +335,11 @@
* in the kernel. * in the kernel.
* *
* @note The default is @p TRUE. * @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT. * @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/ */
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #if !defined(CH_CFG_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE #define CH_CFG_USE_DYNAMIC TRUE
#endif #endif
/** @} */ /** @} */
@ -349,6 +351,15 @@
*/ */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief Debug option, kernel statistics.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_STATISTICS) || defined(__DOXYGEN__)
#define CH_DBG_STATISTICS TRUE
#endif
/** /**
* @brief Debug option, system state check. * @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked * @details If enabled the correct call protocol for system APIs is checked
@ -422,15 +433,15 @@
/** /**
* @brief Debug option, threads profiling. * @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that * @details If enabled then a field is added to the @p thread_t structure that
* counts the system ticks occurred while executing the thread. * counts the system ticks occurred while executing the thread.
* *
* @note The default is @p TRUE. * @note The default is @p FALSE.
* @note This debug option is defaulted to TRUE because it is required by * @note This debug option is not currently compatible with the
* some test cases into the test suite. * tickless mode.
*/ */
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING TRUE #define CH_DBG_THREADS_PROFILING FALSE
#endif #endif
/** @} */ /** @} */
@ -444,10 +455,10 @@
/** /**
* @brief Threads descriptor structure extension. * @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure. * @details User fields added to the end of the @p thread_t structure.
*/ */
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #if !defined(CH_CFG_THREAD_EXTRA_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \ #define CH_CFG_THREAD_EXTRA_FIELDS \
/* Add threads custom fields here.*/ /* Add threads custom fields here.*/
#endif #endif
@ -458,8 +469,8 @@
* @note It is invoked from within @p chThdInit() and implicitly from all * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs. * the threads creation APIs.
*/ */
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_THREAD_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \ #define CH_CFG_THREAD_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \ /* Add threads initialization code here.*/ \
} }
#endif #endif
@ -472,8 +483,8 @@
* @note It is also invoked when the threads simply return in order to * @note It is also invoked when the threads simply return in order to
* terminate. * terminate.
*/ */
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_THREAD_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \ #define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \ /* Add threads finalization code here.*/ \
} }
#endif #endif
@ -482,18 +493,40 @@
* @brief Context switch hook. * @brief Context switch hook.
* @details This hook is invoked just before switching between threads. * @details This hook is invoked just before switching between threads.
*/ */
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ #define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \ /* System halt code here.*/ \
} }
#endif #endif
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#if !defined(CH_CFG_IDLE_ENTER_HOOK) || defined(__DOXYGEN__)
#define CH_CFG_IDLE_ENTER_HOOK() { \
}
#endif
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#if !defined(CH_CFG_IDLE_LEAVE_HOOK) || defined(__DOXYGEN__)
#define CH_CFG_IDLE_LEAVE_HOOK() { \
}
#endif
/** /**
* @brief Idle Loop hook. * @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop. * @details This hook is continuously invoked by the idle thread loop.
*/ */
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \ #define CH_CFG_IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \ /* Idle loop code here.*/ \
} }
#endif #endif
@ -503,8 +536,8 @@
* @details This hook is invoked in the system tick handler immediately * @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue. * after processing the virtual timers queue.
*/ */
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_SYSTEM_TICK_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \ #define CH_CFG_SYSTEM_TICK_HOOK() { \
/* System tick event code here.*/ \ /* System tick event code here.*/ \
} }
#endif #endif
@ -514,8 +547,8 @@
* @details This hook is invoked in case to a system halting error before * @details This hook is invoked in case to a system halting error before
* the system is halted. * the system is halted.
*/ */
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) #if !defined(CH_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \ #define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \ /* System halt code here.*/ \
} }
#endif #endif

7
testhal/STM32F4xx/ADC/halconf.h
View File

@ -30,13 +30,6 @@
#include "mcuconf.h" #include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM TRUE
#endif
/** /**
* @brief Enables the PAL subsystem. * @brief Enables the PAL subsystem.
*/ */