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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7065 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2014-07-24 07:37:17 +00:00
parent dd1dc10973
commit 30522d3ac0
1 changed files with 10 additions and 2 deletions
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12
os/rt/ports/e200/chcore.h
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@ -29,6 +29,8 @@
#ifndef _CHCORE_H_ #ifndef _CHCORE_H_
#define _CHCORE_H_ #define _CHCORE_H_
#include "intc.h"
/*===========================================================================*/ /*===========================================================================*/
/* Module constants. */ /* Module constants. */
/*===========================================================================*/ /*===========================================================================*/
@ -410,6 +412,7 @@ extern "C" {
*/ */
static inline void port_init(void) { static inline void port_init(void) {
uint32_t n; uint32_t n;
unsigned i;
/* Initializing the SPRG0 register to zero, it is required for interrupts /* Initializing the SPRG0 register to zero, it is required for interrupts
handling.*/ handling.*/
@ -425,8 +428,13 @@ static inline void port_init(void) {
"mtIVOR10 %%r3" : : : "r3", "memory"); "mtIVOR10 %%r3" : : : "r3", "memory");
#endif #endif
/* Interrupt controller initialization.*/ /* INTC initialization, software vector mode, 4 bytes vectors, starting
intc_init(); at priority 0.*/
INTC_BCR = 0;
for (i = 0; i < PPC_CORE_NUMBER; i++) {
INTC_CPR(i) = 0;
INTC_IACKR(i) = (uint32_t)_vectors;
}
} }
/** /**