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RTC. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3357 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
barthess 2011-09-20 07:18:29 +00:00
parent da3d1eae7b
commit 3035afea9d
2 changed files with 10 additions and 0 deletions
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5
os/hal/platforms/STM32F1xx/hal_lld_f100.h
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@ -87,6 +87,11 @@
#define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */ #define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ #define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock */
#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock */
#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock */
#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock */
/*===========================================================================*/ /*===========================================================================*/
/* Platform specific friendly IRQ names. */ /* Platform specific friendly IRQ names. */
/*===========================================================================*/ /*===========================================================================*/

5
os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
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@ -92,6 +92,11 @@
#define STM32_MCO_XT1 (10 << 24) /**< XT1 clock on MCO pin. */ #define STM32_MCO_XT1 (10 << 24) /**< XT1 clock on MCO pin. */
#define STM32_MCO_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */ #define STM32_MCO_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */
#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock */
#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock */
#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock */
#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock */
/* RCC_CFGR2 register bits definitions.*/ /* RCC_CFGR2 register bits definitions.*/
#define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */ #define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */
#define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */ #define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */