diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
index 60e42ece4..5cabd9788 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
@@ -87,6 +87,11 @@
 #define STM32_MCO_HSE           (6 << 24)   /**< HSE clock on MCO pin.      */
 #define STM32_MCO_PLLDIV2       (7 << 24)   /**< PLL/2 clock on MCO pin.    */
 
+#define STM32_RTC_NOCLOCK       (0 << 8)    /**< No clock */
+#define STM32_RTC_LSE           (1 << 8)    /**< LSE used as RTC clock */
+#define STM32_RTC_LSI           (2 << 8)    /**< LSI used as RTC clock */
+#define STM32_RTC_HSE           (3 << 8)    /**< HSE divided by 128 used as RTC clock */
+
 /*===========================================================================*/
 /* Platform specific friendly IRQ names.                                     */
 /*===========================================================================*/
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
index 52c124d2d..caed49aca 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
@@ -92,6 +92,11 @@
 #define STM32_MCO_XT1           (10 << 24)  /**< XT1 clock on MCO pin.      */
 #define STM32_MCO_PLL3          (11 << 24)  /**< PLL3 clock on MCO pin.     */
 
+#define STM32_RTC_NOCLOCK       (0 << 8)    /**< No clock */
+#define STM32_RTC_LSE           (1 << 8)    /**< LSE used as RTC clock */
+#define STM32_RTC_LSI           (2 << 8)    /**< LSI used as RTC clock */
+#define STM32_RTC_HSE           (3 << 8)    /**< HSE divided by 128 used as RTC clock */
+
 /* RCC_CFGR2 register bits definitions.*/
 #define STM32_PREDIV1SRC_HSE    (0 << 16)   /**< PREDIV1 source is HSE.     */
 #define STM32_PREDIV1SRC_PLL2   (1 << 16)   /**< PREDIV1 source is PLL2.    */