diff --git a/os/hal/platforms/STM32F1xx/adc_lld.c b/os/hal/platforms/STM32F1xx/adc_lld.c
index c5fb252a8..d87cc7917 100644
--- a/os/hal/platforms/STM32F1xx/adc_lld.c
+++ b/os/hal/platforms/STM32F1xx/adc_lld.c
@@ -181,7 +181,7 @@ void adc_lld_stop(ADCDriver *adcp) {
  * @notapi
  */
 void adc_lld_start_conversion(ADCDriver *adcp) {
-  uint32_t mode, n;
+  uint32_t mode, n, cr2;
   const ADCConversionGroup *grpp = adcp->grpp;
 
   /* DMA setup.*/
@@ -203,7 +203,10 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
 
   /* ADC setup.*/
   adcp->adc->CR1   = grpp->cr1 | ADC_CR1_SCAN;
-  adcp->adc->CR2   = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON;
+  cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
+  if ((cr2 & (ADC_CR2_EXTTRIG | ADC_CR2_JEXTTRIG)) == 0)
+    cr2 |= ADC_CR2_CONT;
+  adcp->adc->CR2   = grpp->cr2 | cr2;
   adcp->adc->SMPR1 = grpp->smpr1;
   adcp->adc->SMPR2 = grpp->smpr2;
   adcp->adc->SQR1  = grpp->sqr1;
@@ -211,7 +214,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   adcp->adc->SQR3  = grpp->sqr3;
 
   /* ADC start by writing ADC_CR2_ADON a second time.*/
-  adcp->adc->CR2   = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON;
+  adcp->adc->CR2   = cr2;
 }
 
 /**
diff --git a/os/hal/platforms/STM32F2xx/adc_lld.c b/os/hal/platforms/STM32F2xx/adc_lld.c
index 937b26727..229b14da0 100644
--- a/os/hal/platforms/STM32F2xx/adc_lld.c
+++ b/os/hal/platforms/STM32F2xx/adc_lld.c
@@ -348,7 +348,11 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   /* ADC configuration and start, the start is performed using the method
      specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
   adcp->adc->CR1   = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
-  adcp->adc->CR2   = grpp->cr2 | ADC_CR2_CONT  | ADC_CR2_DMA |
+  if ((grpp->cr2 & ADC_CR2_SWSTART) == 0)
+    adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT  | ADC_CR2_DMA |
+                                 ADC_CR2_DDS   | ADC_CR2_ADON;
+  else
+    adcp->adc->CR2 = grpp->cr2 |                 ADC_CR2_DMA |
                                  ADC_CR2_DDS   | ADC_CR2_ADON;
 }
 
diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c
index fbeaf22ec..172b2642c 100644
--- a/os/hal/platforms/STM32F4xx/adc_lld.c
+++ b/os/hal/platforms/STM32F4xx/adc_lld.c
@@ -348,7 +348,11 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   /* ADC configuration and start, the start is performed using the method
      specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
   adcp->adc->CR1   = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
-  adcp->adc->CR2   = grpp->cr2 | ADC_CR2_CONT  | ADC_CR2_DMA |
+  if ((grpp->cr2 & ADC_CR2_SWSTART) == 0)
+    adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT  | ADC_CR2_DMA |
+                                 ADC_CR2_DDS   | ADC_CR2_ADON;
+  else
+    adcp->adc->CR2 = grpp->cr2 |                 ADC_CR2_DMA |
                                  ADC_CR2_DDS   | ADC_CR2_ADON;
 }
 
diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c
index cd24b2583..dead7d635 100644
--- a/os/hal/platforms/STM32L1xx/adc_lld.c
+++ b/os/hal/platforms/STM32L1xx/adc_lld.c
@@ -232,7 +232,11 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   /* ADC configuration and start, the start is performed using the method
      specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
   adcp->adc->CR1   = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
-  adcp->adc->CR2   = grpp->cr2 | ADC_CR2_CONT  | ADC_CR2_DMA |
+  if ((grpp->cr2 & ADC_CR2_SWSTART) == 0)
+    adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT  | ADC_CR2_DMA |
+                                 ADC_CR2_DDS   | ADC_CR2_ADON;
+  else
+    adcp->adc->CR2 = grpp->cr2 |                 ADC_CR2_DMA |
                                  ADC_CR2_DDS   | ADC_CR2_ADON;
 }
 
diff --git a/readme.txt b/readme.txt
index 719d29a56..c389209e7 100644
--- a/readme.txt
+++ b/readme.txt
@@ -103,6 +103,7 @@
   (backported to 2.4.3).
 - FIX: Fixed STM8L, cosmic compiler: c_lreg not saved (bug 3566342)(backported
   to 2.2.10 and 2.4.3).
+- NEW: Updated STM32F1, F2, F4, L1 ADC drivers to allow HW triggering.
 - NEW: Added a new option STM32_ETH1_CHANGE_PHY_STATE to the STM32 MAC driver,
   this change is connected to bug 3570335.
 - NEW: Modified the CAN drivers to use the new event flags mechanism, the